//#############################################################################
//
// FILE:   clockTree.h
//
// TITLE:  Setups device clocking for examples.
//
//#############################################################################
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//###########################################################################

#ifndef CLOCKTREE_H
#define CLOCKTREE_H

//*****************************************************************************
//
// Summary of SYSPLL related clock configuration
//
//*****************************************************************************
//
// Input Clock to SYSPLL (OSCCLK)	= 10 MHz    (INTOSC1 provides OSCCLK)
//
//##### SYSPLL ENABLED #####
//
// PLLRAWCLK				= 400 MHz   (Output of SYSPLL if enabled) 
// PLLSYSCLK				= 200 MHz
// CPU1CLK					= 200 MHz
// CPU2CLK					= 200 MHz 
// CPU1_SYSCLK				= 200 MHz
// CPU2_SYSCLK 				= 200 MHz
// LSPCLK					= 50 MHz 
// EPWMCLK 					= 100 MHz	
	
//*****************************************************************************
//
// Macro definitions used in device.c (SYSPLL / LSPCLK)
//
//*****************************************************************************
//
//	Input Clock to SYSPLL (OSCCLK) = INTOSC1 = 10 MHz
//
#define DEVICE_OSCSRC_FREQ          10000000U
//
// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
// SYSPLL ENABLED
// SYSCLK = 200 MHz = 10 MHz (OSCCLK) * (40 (IMULT) + 0 (FMULT)) / 2 (SYSCLKDIVSEL)	
#define DEVICE_SYSCLK_FREQ          ((DEVICE_OSCSRC_FREQ * (40 + 0)) / 2)
//
#define DEVICE_SETCLOCK_CFG         (SYSCTL_OSCSRC_OSC1 | SYSCTL_IMULT(40) | \
									 SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2)| \
									 SYSCTL_PLL_ENABLE)

//
// Define to pass to SysCtl_setLowSpeedClock().
// Low Speed Clock (LSPCLK) = 200 MHz / 4 = 50 MHz
//
#define DEVICE_LSPCLK_CFG  			SYSCTL_LSPCLK_PRESCALE_4

#define DEVICE_LSPCLK_FREQ          (DEVICE_SYSCLK_FREQ / 4)

//*****************************************************************************
//
// Summary of AUXPLL related clock configuration
//
//*****************************************************************************
//
// Input Clock to AUXOSCCLK	= 10 MHz (XTAL provides AUXOSCCLK)  
//
//##### AUXPLL DISABLED #####
//
// AUXPLLRAWCLK				= 200 MHz (Output of AUXPLL if enabled)
// AUXPLLCLK				= 5 MHz 
//
//*****************************************************************************
//
// Macro definitions used in device.c (AUXPLL)
//
//*****************************************************************************
//
//	Input Clock to AUXPLL (AUXOSCCLK) = XTAL = 10 MHz
//
#define DEVICE_AUXOSCSRC_FREQ 		10000000U
//
// Define to pass to SysCtl_setAuxClock(). Will configure the clock as follows:
// AUXPLL DISABLED
// AUXPLLCLK = 5 MHz = 10 MHz (XTAL) / 2 (AUXCLKDIVSEL)
#define DEVICE_AUXCLK_FREQ			(DEVICE_AUXOSCSRC_FREQ  / 2) 
//
#define DEVICE_SETAUXCLOCK_CFG      (SYSCTL_AUXPLL_OSCSRC_XTAL | SYSCTL_AUXPLL_IMULT(20) | \
									 SYSCTL_AUXPLL_FMULT_NONE | SYSCTL_AUXPLL_DIV_2 | \
									 SYSCTL_AUXPLL_DISABLE)

	
//*****************************************************************************
//
// CPU1CLK / CPU2CLK Domain (200 MHz)
//
//*****************************************************************************
// VCU
// TMU
// FPU
// Flash
// BOOTROM
// Mx/DxRAM
//	

//*****************************************************************************
//
// CPU1 SYSCLK Domain (200 MHz)
//
//*****************************************************************************
// EPIE
// LSxRAMs
// CLAMessageRAM
// DCSM
//	

/////////////////////	
// Gated CPU1 SYSCLK
/////////////////////
// CPU1_CLA1
// CPU1_DMA
// CPU1_Timer
// EMIF2
// uPP
//

//*****************************************************************************
//
// CPU2 SYSCLK Domain (200 MHz)
//
//*****************************************************************************
// EPIE
// LSxRAMs
// CLAMessageRAM
// DCSM
//
	
/////////////////////	
// Gated CPU2 SYSCLK
/////////////////////
// CPU2_CLA1
// CPU2_DMA
// CPU2_Timer
//
//*****************************************************************************
//
// Gated Peripheral EPWM Domain (100 MHz) 
//
//*****************************************************************************
// EPWM
// HRPWM
//
//*****************************************************************************
//
// Gated Peripheral SYSCLK Domain (200 MHz) 
//
//*****************************************************************************
// ADC
// CMPSS
// DAC
// EPWM
// ECAP
// EQEP
// I2C
// SDFM
// EMIF
//	
//*****************************************************************************
//
// Gated LSPCLK Domain (50 MHz) 
//
//*****************************************************************************
// SCI
// SPI
// McBSP

#endif // CLOCKTREE_H