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.tools/python-revlibs/capstone-5.0.9.dist-info/INSTALLER

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+pip

.tools/python-revlibs/capstone-5.0.9.dist-info/LICENSE.TXT

@@ -0,0 +1,31 @@
+This is the software license for Capstone disassembly framework.
+Capstone has been designed & implemented by Nguyen Anh Quynh <aquynh@gmail.com>
+
+See http://www.capstone-engine.org for further information.
+
+Copyright (c) 2013, COSEINC.
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice,
+  this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice,
+  this list of conditions and the following disclaimer in the documentation
+  and/or other materials provided with the distribution.
+* Neither the name of the developer(s) nor the names of its
+  contributors may be used to endorse or promote products derived from this
+  software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.

.tools/python-revlibs/capstone-5.0.9.dist-info/METADATA

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+Metadata-Version: 2.1
+Name: capstone
+Version: 5.0.9
+Summary: Capstone disassembly engine
+Home-page: https://www.capstone-engine.org
+Author: Nguyen Anh Quynh
+Author-email: aquynh@gmail.com
+Classifier: License :: OSI Approved :: BSD License
+Classifier: Programming Language :: Python :: 3
+Provides: capstone
+Requires-Python: >=3.8
+Description-Content-Type: text/markdown
+License-File: LICENSE.TXT
+Requires-Dist: importlib-resources ; python_version < "3.9"
+
+To install Capstone, you should run `pip install capstone`.
+
+If you would like to build Capstone with just the source distribution, without
+pip, just run `python setup.py install` in the folder with setup.py in it.
+
+In order to use this source distribution, you will need an environment that can
+compile C code. On Linux, this is usually easy, but on Windows, this involves
+installing Visual Studio and using the "Developer Command Prompt" to perform the
+installation. See BUILDING.txt for more information.
+
+By default, attempting to install the python bindings will trigger a build of
+the capstone native core. If this is undesirable for whatever reason, for
+instance, you already have a globally installed copy of libcapstone, you may
+inhibit the build by setting the environment variable LIBCAPSTONE_PATH. The
+exact value is not checked, just setting it will inhibit the build. During
+execution, this variable may be set to the path of a directory containing a
+specific version of libcapstone you would like to use.
+
+If you don't want to build your own copy of Capstone, you can use a precompiled
+binary distribution from PyPI. Saying `pip install capstone` should
+automatically obtain an appropriate copy for your system. If it does not, please
+open an issue at https://github.com/aquynh/capstone and tag @rhelmot - she
+will fix this, probably!
+
+--------------------------------------------------------------------------------
+
+Capstone is a disassembly framework with the target of becoming the ultimate
+disasm engine for binary analysis and reversing in the security community.
+
+Created by Nguyen Anh Quynh, then developed and maintained by a small community,
+Capstone offers some unparalleled features:
+
+- Support multiple hardware architectures: ARM, ARM64 (ARMv8), Mips, PPC, Sparc,
+  SystemZ, XCore and X86 (including X86_64).
+
+- Having clean/simple/lightweight/intuitive architecture-neutral API.
+
+- Provide details on disassembled instruction (called “decomposer” by others).
+
+- Provide semantics of the disassembled instruction, such as list of implicit
+  registers read & written.
+
+- Implemented in pure C language, with lightweight wrappers for C++, C#, Go,
+  Java, NodeJS, Ocaml, Python, Ruby & Vala ready (available in main code,
+  or provided externally by the community).
+
+- Native support for all popular platforms: Windows, Mac OSX, iOS, Android,
+  Linux, *BSD, Solaris, etc.
+
+- Thread-safe by design.
+
+- Special support for embedding into firmware or OS kernel.
+
+- High performance & suitable for malware analysis (capable of handling various
+  X86 malware tricks).
+
+- Distributed under the open source BSD license.
+
+Further information is available at http://www.capstone-engine.org
+
+
+[License]
+
+This project is released under the BSD license. If you redistribute the binary
+or source code of Capstone, please attach file LICENSE.TXT with your products.

.tools/python-revlibs/capstone-5.0.9.dist-info/RECORD

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.tools/python-revlibs/capstone-5.0.9.dist-info/WHEEL

@@ -0,0 +1,5 @@
+Wheel-Version: 1.0
+Generator: setuptools (75.3.4)
+Root-Is-Purelib: true
+Tag: py3-none-win_amd64
+

.tools/python-revlibs/capstone-5.0.9.dist-info/top_level.txt

@@ -0,0 +1 @@
+capstone

.tools/python-revlibs/capstone/arm.py

@@ -0,0 +1,83 @@
+# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
+
+import ctypes
+from . import copy_ctypes_list
+from .arm_const import *
+
+# define the API
+class ArmOpMem(ctypes.Structure):
+    _fields_ = (
+        ('base', ctypes.c_uint),
+        ('index', ctypes.c_uint),
+        ('scale', ctypes.c_int),
+        ('disp', ctypes.c_int),
+        ('lshift', ctypes.c_int),
+    )
+
+class ArmOpShift(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', ctypes.c_uint),
+    )
+
+class ArmOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_int32),
+        ('fp', ctypes.c_double),
+        ('mem', ArmOpMem),
+        ('setend', ctypes.c_int),
+    )
+
+class ArmOp(ctypes.Structure):
+    _fields_ = (
+        ('vector_index', ctypes.c_int),
+        ('shift', ArmOpShift),
+        ('type', ctypes.c_uint),
+        ('value', ArmOpValue),
+        ('subtracted', ctypes.c_bool),
+        ('access', ctypes.c_uint8),
+        ('neon_lane', ctypes.c_int8),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def fp(self):
+        return self.value.fp
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+    @property
+    def setend(self):
+        return self.value.setend
+
+
+class CsArm(ctypes.Structure):
+    _fields_ = (
+        ('usermode', ctypes.c_bool),
+        ('vector_size', ctypes.c_int),
+        ('vector_data', ctypes.c_int),
+        ('cps_mode', ctypes.c_int),
+        ('cps_flag', ctypes.c_int),
+        ('cc', ctypes.c_uint),
+        ('update_flags', ctypes.c_bool),
+        ('writeback', ctypes.c_bool),
+        ('post_index', ctypes.c_bool),
+        ('mem_barrier', ctypes.c_int),
+        ('op_count', ctypes.c_uint8),
+        ('operands', ArmOp * 36),
+    )
+
+def get_arch_info(a):
+    return (a.usermode, a.vector_size, a.vector_data, a.cps_mode, a.cps_flag, a.cc, a.update_flags, \
+        a.writeback, a.post_index, a.mem_barrier, copy_ctypes_list(a.operands[:a.op_count]))
+

.tools/python-revlibs/capstone/arm64.py

@@ -0,0 +1,103 @@
+# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
+
+import ctypes
+from . import copy_ctypes_list
+from .arm64_const import *
+
+# define the API
+class Arm64OpMem(ctypes.Structure):
+    _fields_ = (
+        ('base', ctypes.c_uint),
+        ('index', ctypes.c_uint),
+        ('disp', ctypes.c_int32),
+    )
+
+class Arm64OpSmeIndex(ctypes.Structure):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('base', ctypes.c_uint),
+        ('disp', ctypes.c_int32),
+    )
+
+class Arm64OpShift(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', ctypes.c_uint),
+    )
+
+class Arm64OpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_int64),
+        ('fp', ctypes.c_double),
+        ('mem', Arm64OpMem),
+        ('pstate', ctypes.c_int),
+        ('sys', ctypes.c_uint),
+        ('prefetch', ctypes.c_int),
+        ('barrier', ctypes.c_int),
+        ('sme_index', Arm64OpSmeIndex),
+    )
+
+class Arm64Op(ctypes.Structure):
+    _fields_ = (
+        ('vector_index', ctypes.c_int),
+        ('vas', ctypes.c_int),
+        ('shift', Arm64OpShift),
+        ('ext', ctypes.c_uint),
+        ('type', ctypes.c_uint),
+        ('svcr', ctypes.c_uint),
+        ('value', Arm64OpValue),
+        ('access', ctypes.c_uint8),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def fp(self):
+        return self.value.fp
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+    @property
+    def pstate(self):
+        return self.value.pstate
+
+    @property
+    def sys(self):
+        return self.value.sys
+
+    @property
+    def prefetch(self):
+        return self.value.prefetch
+
+    @property
+    def barrier(self):
+        return self.value.barrier
+    
+    @property
+    def sme_index(self):
+        return self.value.sme_index
+
+
+
+class CsArm64(ctypes.Structure):
+    _fields_ = (
+        ('cc', ctypes.c_uint),
+        ('update_flags', ctypes.c_bool),
+        ('writeback', ctypes.c_bool),
+        ('post_index', ctypes.c_bool),
+        ('op_count', ctypes.c_uint8),
+        ('operands', Arm64Op * 8),
+    )
+
+def get_arch_info(a):
+    return (a.cc, a.update_flags, a.writeback, a.post_index, copy_ctypes_list(a.operands[:a.op_count]))
+

.tools/python-revlibs/capstone/arm_const.py

@@ -0,0 +1,831 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [arm_const.py]
+
+ARM_SFT_INVALID = 0
+ARM_SFT_ASR = 1
+ARM_SFT_LSL = 2
+ARM_SFT_LSR = 3
+ARM_SFT_ROR = 4
+ARM_SFT_RRX = 5
+ARM_SFT_ASR_REG = 6
+ARM_SFT_LSL_REG = 7
+ARM_SFT_LSR_REG = 8
+ARM_SFT_ROR_REG = 9
+ARM_SFT_RRX_REG = 10
+
+ARM_CC_INVALID = 0
+ARM_CC_EQ = 1
+ARM_CC_NE = 2
+ARM_CC_HS = 3
+ARM_CC_LO = 4
+ARM_CC_MI = 5
+ARM_CC_PL = 6
+ARM_CC_VS = 7
+ARM_CC_VC = 8
+ARM_CC_HI = 9
+ARM_CC_LS = 10
+ARM_CC_GE = 11
+ARM_CC_LT = 12
+ARM_CC_GT = 13
+ARM_CC_LE = 14
+ARM_CC_AL = 15
+
+ARM_SYSREG_INVALID = 0
+ARM_SYSREG_SPSR_C = 1
+ARM_SYSREG_SPSR_X = 2
+ARM_SYSREG_SPSR_S = 4
+ARM_SYSREG_SPSR_F = 8
+ARM_SYSREG_CPSR_C = 16
+ARM_SYSREG_CPSR_X = 32
+ARM_SYSREG_CPSR_S = 64
+ARM_SYSREG_CPSR_F = 128
+ARM_SYSREG_APSR = 256
+ARM_SYSREG_APSR_G = 257
+ARM_SYSREG_APSR_NZCVQ = 258
+ARM_SYSREG_APSR_NZCVQG = 259
+ARM_SYSREG_IAPSR = 260
+ARM_SYSREG_IAPSR_G = 261
+ARM_SYSREG_IAPSR_NZCVQG = 262
+ARM_SYSREG_IAPSR_NZCVQ = 263
+ARM_SYSREG_EAPSR = 264
+ARM_SYSREG_EAPSR_G = 265
+ARM_SYSREG_EAPSR_NZCVQG = 266
+ARM_SYSREG_EAPSR_NZCVQ = 267
+ARM_SYSREG_XPSR = 268
+ARM_SYSREG_XPSR_G = 269
+ARM_SYSREG_XPSR_NZCVQG = 270
+ARM_SYSREG_XPSR_NZCVQ = 271
+ARM_SYSREG_IPSR = 272
+ARM_SYSREG_EPSR = 273
+ARM_SYSREG_IEPSR = 274
+ARM_SYSREG_MSP = 275
+ARM_SYSREG_PSP = 276
+ARM_SYSREG_PRIMASK = 277
+ARM_SYSREG_BASEPRI = 278
+ARM_SYSREG_BASEPRI_MAX = 279
+ARM_SYSREG_FAULTMASK = 280
+ARM_SYSREG_CONTROL = 281
+ARM_SYSREG_MSPLIM = 282
+ARM_SYSREG_PSPLIM = 283
+ARM_SYSREG_MSP_NS = 284
+ARM_SYSREG_PSP_NS = 285
+ARM_SYSREG_MSPLIM_NS = 286
+ARM_SYSREG_PSPLIM_NS = 287
+ARM_SYSREG_PRIMASK_NS = 288
+ARM_SYSREG_BASEPRI_NS = 289
+ARM_SYSREG_FAULTMASK_NS = 290
+ARM_SYSREG_CONTROL_NS = 291
+ARM_SYSREG_SP_NS = 292
+ARM_SYSREG_R8_USR = 293
+ARM_SYSREG_R9_USR = 294
+ARM_SYSREG_R10_USR = 295
+ARM_SYSREG_R11_USR = 296
+ARM_SYSREG_R12_USR = 297
+ARM_SYSREG_SP_USR = 298
+ARM_SYSREG_LR_USR = 299
+ARM_SYSREG_R8_FIQ = 300
+ARM_SYSREG_R9_FIQ = 301
+ARM_SYSREG_R10_FIQ = 302
+ARM_SYSREG_R11_FIQ = 303
+ARM_SYSREG_R12_FIQ = 304
+ARM_SYSREG_SP_FIQ = 305
+ARM_SYSREG_LR_FIQ = 306
+ARM_SYSREG_LR_IRQ = 307
+ARM_SYSREG_SP_IRQ = 308
+ARM_SYSREG_LR_SVC = 309
+ARM_SYSREG_SP_SVC = 310
+ARM_SYSREG_LR_ABT = 311
+ARM_SYSREG_SP_ABT = 312
+ARM_SYSREG_LR_UND = 313
+ARM_SYSREG_SP_UND = 314
+ARM_SYSREG_LR_MON = 315
+ARM_SYSREG_SP_MON = 316
+ARM_SYSREG_ELR_HYP = 317
+ARM_SYSREG_SP_HYP = 318
+ARM_SYSREG_SPSR_FIQ = 319
+ARM_SYSREG_SPSR_IRQ = 320
+ARM_SYSREG_SPSR_SVC = 321
+ARM_SYSREG_SPSR_ABT = 322
+ARM_SYSREG_SPSR_UND = 323
+ARM_SYSREG_SPSR_MON = 324
+ARM_SYSREG_SPSR_HYP = 325
+
+ARM_MB_INVALID = 0
+ARM_MB_RESERVED_0 = 1
+ARM_MB_OSHLD = 2
+ARM_MB_OSHST = 3
+ARM_MB_OSH = 4
+ARM_MB_RESERVED_4 = 5
+ARM_MB_NSHLD = 6
+ARM_MB_NSHST = 7
+ARM_MB_NSH = 8
+ARM_MB_RESERVED_8 = 9
+ARM_MB_ISHLD = 10
+ARM_MB_ISHST = 11
+ARM_MB_ISH = 12
+ARM_MB_RESERVED_12 = 13
+ARM_MB_LD = 14
+ARM_MB_ST = 15
+ARM_MB_SY = 16
+
+ARM_OP_INVALID = 0
+ARM_OP_REG = 1
+ARM_OP_IMM = 2
+ARM_OP_MEM = 3
+ARM_OP_FP = 4
+ARM_OP_CIMM = 64
+ARM_OP_PIMM = 65
+ARM_OP_SETEND = 66
+ARM_OP_SYSREG = 67
+
+ARM_SETEND_INVALID = 0
+ARM_SETEND_BE = 1
+ARM_SETEND_LE = 2
+
+ARM_CPSMODE_INVALID = 0
+ARM_CPSMODE_IE = 2
+ARM_CPSMODE_ID = 3
+
+ARM_CPSFLAG_INVALID = 0
+ARM_CPSFLAG_F = 1
+ARM_CPSFLAG_I = 2
+ARM_CPSFLAG_A = 4
+ARM_CPSFLAG_NONE = 16
+
+ARM_VECTORDATA_INVALID = 0
+ARM_VECTORDATA_I8 = 1
+ARM_VECTORDATA_I16 = 2
+ARM_VECTORDATA_I32 = 3
+ARM_VECTORDATA_I64 = 4
+ARM_VECTORDATA_S8 = 5
+ARM_VECTORDATA_S16 = 6
+ARM_VECTORDATA_S32 = 7
+ARM_VECTORDATA_S64 = 8
+ARM_VECTORDATA_U8 = 9
+ARM_VECTORDATA_U16 = 10
+ARM_VECTORDATA_U32 = 11
+ARM_VECTORDATA_U64 = 12
+ARM_VECTORDATA_P8 = 13
+ARM_VECTORDATA_F16 = 14
+ARM_VECTORDATA_F32 = 15
+ARM_VECTORDATA_F64 = 16
+ARM_VECTORDATA_F16F64 = 17
+ARM_VECTORDATA_F64F16 = 18
+ARM_VECTORDATA_F32F16 = 19
+ARM_VECTORDATA_F16F32 = 20
+ARM_VECTORDATA_F64F32 = 21
+ARM_VECTORDATA_F32F64 = 22
+ARM_VECTORDATA_S32F32 = 23
+ARM_VECTORDATA_U32F32 = 24
+ARM_VECTORDATA_F32S32 = 25
+ARM_VECTORDATA_F32U32 = 26
+ARM_VECTORDATA_F64S16 = 27
+ARM_VECTORDATA_F32S16 = 28
+ARM_VECTORDATA_F64S32 = 29
+ARM_VECTORDATA_S16F64 = 30
+ARM_VECTORDATA_S16F32 = 31
+ARM_VECTORDATA_S32F64 = 32
+ARM_VECTORDATA_U16F64 = 33
+ARM_VECTORDATA_U16F32 = 34
+ARM_VECTORDATA_U32F64 = 35
+ARM_VECTORDATA_F64U16 = 36
+ARM_VECTORDATA_F32U16 = 37
+ARM_VECTORDATA_F64U32 = 38
+ARM_VECTORDATA_F16U16 = 39
+ARM_VECTORDATA_U16F16 = 40
+ARM_VECTORDATA_F16U32 = 41
+ARM_VECTORDATA_U32F16 = 42
+
+ARM_REG_INVALID = 0
+ARM_REG_APSR = 1
+ARM_REG_APSR_NZCV = 2
+ARM_REG_CPSR = 3
+ARM_REG_FPEXC = 4
+ARM_REG_FPINST = 5
+ARM_REG_FPSCR = 6
+ARM_REG_FPSCR_NZCV = 7
+ARM_REG_FPSID = 8
+ARM_REG_ITSTATE = 9
+ARM_REG_LR = 10
+ARM_REG_PC = 11
+ARM_REG_SP = 12
+ARM_REG_SPSR = 13
+ARM_REG_D0 = 14
+ARM_REG_D1 = 15
+ARM_REG_D2 = 16
+ARM_REG_D3 = 17
+ARM_REG_D4 = 18
+ARM_REG_D5 = 19
+ARM_REG_D6 = 20
+ARM_REG_D7 = 21
+ARM_REG_D8 = 22
+ARM_REG_D9 = 23
+ARM_REG_D10 = 24
+ARM_REG_D11 = 25
+ARM_REG_D12 = 26
+ARM_REG_D13 = 27
+ARM_REG_D14 = 28
+ARM_REG_D15 = 29
+ARM_REG_D16 = 30
+ARM_REG_D17 = 31
+ARM_REG_D18 = 32
+ARM_REG_D19 = 33
+ARM_REG_D20 = 34
+ARM_REG_D21 = 35
+ARM_REG_D22 = 36
+ARM_REG_D23 = 37
+ARM_REG_D24 = 38
+ARM_REG_D25 = 39
+ARM_REG_D26 = 40
+ARM_REG_D27 = 41
+ARM_REG_D28 = 42
+ARM_REG_D29 = 43
+ARM_REG_D30 = 44
+ARM_REG_D31 = 45
+ARM_REG_FPINST2 = 46
+ARM_REG_MVFR0 = 47
+ARM_REG_MVFR1 = 48
+ARM_REG_MVFR2 = 49
+ARM_REG_Q0 = 50
+ARM_REG_Q1 = 51
+ARM_REG_Q2 = 52
+ARM_REG_Q3 = 53
+ARM_REG_Q4 = 54
+ARM_REG_Q5 = 55
+ARM_REG_Q6 = 56
+ARM_REG_Q7 = 57
+ARM_REG_Q8 = 58
+ARM_REG_Q9 = 59
+ARM_REG_Q10 = 60
+ARM_REG_Q11 = 61
+ARM_REG_Q12 = 62
+ARM_REG_Q13 = 63
+ARM_REG_Q14 = 64
+ARM_REG_Q15 = 65
+ARM_REG_R0 = 66
+ARM_REG_R1 = 67
+ARM_REG_R2 = 68
+ARM_REG_R3 = 69
+ARM_REG_R4 = 70
+ARM_REG_R5 = 71
+ARM_REG_R6 = 72
+ARM_REG_R7 = 73
+ARM_REG_R8 = 74
+ARM_REG_R9 = 75
+ARM_REG_R10 = 76
+ARM_REG_R11 = 77
+ARM_REG_R12 = 78
+ARM_REG_S0 = 79
+ARM_REG_S1 = 80
+ARM_REG_S2 = 81
+ARM_REG_S3 = 82
+ARM_REG_S4 = 83
+ARM_REG_S5 = 84
+ARM_REG_S6 = 85
+ARM_REG_S7 = 86
+ARM_REG_S8 = 87
+ARM_REG_S9 = 88
+ARM_REG_S10 = 89
+ARM_REG_S11 = 90
+ARM_REG_S12 = 91
+ARM_REG_S13 = 92
+ARM_REG_S14 = 93
+ARM_REG_S15 = 94
+ARM_REG_S16 = 95
+ARM_REG_S17 = 96
+ARM_REG_S18 = 97
+ARM_REG_S19 = 98
+ARM_REG_S20 = 99
+ARM_REG_S21 = 100
+ARM_REG_S22 = 101
+ARM_REG_S23 = 102
+ARM_REG_S24 = 103
+ARM_REG_S25 = 104
+ARM_REG_S26 = 105
+ARM_REG_S27 = 106
+ARM_REG_S28 = 107
+ARM_REG_S29 = 108
+ARM_REG_S30 = 109
+ARM_REG_S31 = 110
+ARM_REG_ENDING = 111
+ARM_REG_R13 = ARM_REG_SP
+ARM_REG_R14 = ARM_REG_LR
+ARM_REG_R15 = ARM_REG_PC
+ARM_REG_SB = ARM_REG_R9
+ARM_REG_SL = ARM_REG_R10
+ARM_REG_FP = ARM_REG_R11
+ARM_REG_IP = ARM_REG_R12
+
+ARM_INS_INVALID = 0
+ARM_INS_ADC = 1
+ARM_INS_ADD = 2
+ARM_INS_ADDW = 3
+ARM_INS_ADR = 4
+ARM_INS_AESD = 5
+ARM_INS_AESE = 6
+ARM_INS_AESIMC = 7
+ARM_INS_AESMC = 8
+ARM_INS_AND = 9
+ARM_INS_ASR = 10
+ARM_INS_B = 11
+ARM_INS_BFC = 12
+ARM_INS_BFI = 13
+ARM_INS_BIC = 14
+ARM_INS_BKPT = 15
+ARM_INS_BL = 16
+ARM_INS_BLX = 17
+ARM_INS_BLXNS = 18
+ARM_INS_BX = 19
+ARM_INS_BXJ = 20
+ARM_INS_BXNS = 21
+ARM_INS_CBNZ = 22
+ARM_INS_CBZ = 23
+ARM_INS_CDP = 24
+ARM_INS_CDP2 = 25
+ARM_INS_CLREX = 26
+ARM_INS_CLZ = 27
+ARM_INS_CMN = 28
+ARM_INS_CMP = 29
+ARM_INS_CPS = 30
+ARM_INS_CRC32B = 31
+ARM_INS_CRC32CB = 32
+ARM_INS_CRC32CH = 33
+ARM_INS_CRC32CW = 34
+ARM_INS_CRC32H = 35
+ARM_INS_CRC32W = 36
+ARM_INS_CSDB = 37
+ARM_INS_DBG = 38
+ARM_INS_DCPS1 = 39
+ARM_INS_DCPS2 = 40
+ARM_INS_DCPS3 = 41
+ARM_INS_DFB = 42
+ARM_INS_DMB = 43
+ARM_INS_DSB = 44
+ARM_INS_EOR = 45
+ARM_INS_ERET = 46
+ARM_INS_ESB = 47
+ARM_INS_FADDD = 48
+ARM_INS_FADDS = 49
+ARM_INS_FCMPZD = 50
+ARM_INS_FCMPZS = 51
+ARM_INS_FCONSTD = 52
+ARM_INS_FCONSTS = 53
+ARM_INS_FLDMDBX = 54
+ARM_INS_FLDMIAX = 55
+ARM_INS_FMDHR = 56
+ARM_INS_FMDLR = 57
+ARM_INS_FMSTAT = 58
+ARM_INS_FSTMDBX = 59
+ARM_INS_FSTMIAX = 60
+ARM_INS_FSUBD = 61
+ARM_INS_FSUBS = 62
+ARM_INS_HINT = 63
+ARM_INS_HLT = 64
+ARM_INS_HVC = 65
+ARM_INS_ISB = 66
+ARM_INS_IT = 67
+ARM_INS_LDA = 68
+ARM_INS_LDAB = 69
+ARM_INS_LDAEX = 70
+ARM_INS_LDAEXB = 71
+ARM_INS_LDAEXD = 72
+ARM_INS_LDAEXH = 73
+ARM_INS_LDAH = 74
+ARM_INS_LDC = 75
+ARM_INS_LDC2 = 76
+ARM_INS_LDC2L = 77
+ARM_INS_LDCL = 78
+ARM_INS_LDM = 79
+ARM_INS_LDMDA = 80
+ARM_INS_LDMDB = 81
+ARM_INS_LDMIB = 82
+ARM_INS_LDR = 83
+ARM_INS_LDRB = 84
+ARM_INS_LDRBT = 85
+ARM_INS_LDRD = 86
+ARM_INS_LDREX = 87
+ARM_INS_LDREXB = 88
+ARM_INS_LDREXD = 89
+ARM_INS_LDREXH = 90
+ARM_INS_LDRH = 91
+ARM_INS_LDRHT = 92
+ARM_INS_LDRSB = 93
+ARM_INS_LDRSBT = 94
+ARM_INS_LDRSH = 95
+ARM_INS_LDRSHT = 96
+ARM_INS_LDRT = 97
+ARM_INS_LSL = 98
+ARM_INS_LSR = 99
+ARM_INS_MCR = 100
+ARM_INS_MCR2 = 101
+ARM_INS_MCRR = 102
+ARM_INS_MCRR2 = 103
+ARM_INS_MLA = 104
+ARM_INS_MLS = 105
+ARM_INS_MOV = 106
+ARM_INS_MOVS = 107
+ARM_INS_MOVT = 108
+ARM_INS_MOVW = 109
+ARM_INS_MRC = 110
+ARM_INS_MRC2 = 111
+ARM_INS_MRRC = 112
+ARM_INS_MRRC2 = 113
+ARM_INS_MRS = 114
+ARM_INS_MSR = 115
+ARM_INS_MUL = 116
+ARM_INS_MVN = 117
+ARM_INS_NEG = 118
+ARM_INS_NOP = 119
+ARM_INS_ORN = 120
+ARM_INS_ORR = 121
+ARM_INS_PKHBT = 122
+ARM_INS_PKHTB = 123
+ARM_INS_PLD = 124
+ARM_INS_PLDW = 125
+ARM_INS_PLI = 126
+ARM_INS_POP = 127
+ARM_INS_PUSH = 128
+ARM_INS_QADD = 129
+ARM_INS_QADD16 = 130
+ARM_INS_QADD8 = 131
+ARM_INS_QASX = 132
+ARM_INS_QDADD = 133
+ARM_INS_QDSUB = 134
+ARM_INS_QSAX = 135
+ARM_INS_QSUB = 136
+ARM_INS_QSUB16 = 137
+ARM_INS_QSUB8 = 138
+ARM_INS_RBIT = 139
+ARM_INS_REV = 140
+ARM_INS_REV16 = 141
+ARM_INS_REVSH = 142
+ARM_INS_RFEDA = 143
+ARM_INS_RFEDB = 144
+ARM_INS_RFEIA = 145
+ARM_INS_RFEIB = 146
+ARM_INS_ROR = 147
+ARM_INS_RRX = 148
+ARM_INS_RSB = 149
+ARM_INS_RSC = 150
+ARM_INS_SADD16 = 151
+ARM_INS_SADD8 = 152
+ARM_INS_SASX = 153
+ARM_INS_SBC = 154
+ARM_INS_SBFX = 155
+ARM_INS_SDIV = 156
+ARM_INS_SEL = 157
+ARM_INS_SETEND = 158
+ARM_INS_SETPAN = 159
+ARM_INS_SEV = 160
+ARM_INS_SEVL = 161
+ARM_INS_SG = 162
+ARM_INS_SHA1C = 163
+ARM_INS_SHA1H = 164
+ARM_INS_SHA1M = 165
+ARM_INS_SHA1P = 166
+ARM_INS_SHA1SU0 = 167
+ARM_INS_SHA1SU1 = 168
+ARM_INS_SHA256H = 169
+ARM_INS_SHA256H2 = 170
+ARM_INS_SHA256SU0 = 171
+ARM_INS_SHA256SU1 = 172
+ARM_INS_SHADD16 = 173
+ARM_INS_SHADD8 = 174
+ARM_INS_SHASX = 175
+ARM_INS_SHSAX = 176
+ARM_INS_SHSUB16 = 177
+ARM_INS_SHSUB8 = 178
+ARM_INS_SMC = 179
+ARM_INS_SMLABB = 180
+ARM_INS_SMLABT = 181
+ARM_INS_SMLAD = 182
+ARM_INS_SMLADX = 183
+ARM_INS_SMLAL = 184
+ARM_INS_SMLALBB = 185
+ARM_INS_SMLALBT = 186
+ARM_INS_SMLALD = 187
+ARM_INS_SMLALDX = 188
+ARM_INS_SMLALTB = 189
+ARM_INS_SMLALTT = 190
+ARM_INS_SMLATB = 191
+ARM_INS_SMLATT = 192
+ARM_INS_SMLAWB = 193
+ARM_INS_SMLAWT = 194
+ARM_INS_SMLSD = 195
+ARM_INS_SMLSDX = 196
+ARM_INS_SMLSLD = 197
+ARM_INS_SMLSLDX = 198
+ARM_INS_SMMLA = 199
+ARM_INS_SMMLAR = 200
+ARM_INS_SMMLS = 201
+ARM_INS_SMMLSR = 202
+ARM_INS_SMMUL = 203
+ARM_INS_SMMULR = 204
+ARM_INS_SMUAD = 205
+ARM_INS_SMUADX = 206
+ARM_INS_SMULBB = 207
+ARM_INS_SMULBT = 208
+ARM_INS_SMULL = 209
+ARM_INS_SMULTB = 210
+ARM_INS_SMULTT = 211
+ARM_INS_SMULWB = 212
+ARM_INS_SMULWT = 213
+ARM_INS_SMUSD = 214
+ARM_INS_SMUSDX = 215
+ARM_INS_SRSDA = 216
+ARM_INS_SRSDB = 217
+ARM_INS_SRSIA = 218
+ARM_INS_SRSIB = 219
+ARM_INS_SSAT = 220
+ARM_INS_SSAT16 = 221
+ARM_INS_SSAX = 222
+ARM_INS_SSUB16 = 223
+ARM_INS_SSUB8 = 224
+ARM_INS_STC = 225
+ARM_INS_STC2 = 226
+ARM_INS_STC2L = 227
+ARM_INS_STCL = 228
+ARM_INS_STL = 229
+ARM_INS_STLB = 230
+ARM_INS_STLEX = 231
+ARM_INS_STLEXB = 232
+ARM_INS_STLEXD = 233
+ARM_INS_STLEXH = 234
+ARM_INS_STLH = 235
+ARM_INS_STM = 236
+ARM_INS_STMDA = 237
+ARM_INS_STMDB = 238
+ARM_INS_STMIB = 239
+ARM_INS_STR = 240
+ARM_INS_STRB = 241
+ARM_INS_STRBT = 242
+ARM_INS_STRD = 243
+ARM_INS_STREX = 244
+ARM_INS_STREXB = 245
+ARM_INS_STREXD = 246
+ARM_INS_STREXH = 247
+ARM_INS_STRH = 248
+ARM_INS_STRHT = 249
+ARM_INS_STRT = 250
+ARM_INS_SUB = 251
+ARM_INS_SUBS = 252
+ARM_INS_SUBW = 253
+ARM_INS_SVC = 254
+ARM_INS_SWP = 255
+ARM_INS_SWPB = 256
+ARM_INS_SXTAB = 257
+ARM_INS_SXTAB16 = 258
+ARM_INS_SXTAH = 259
+ARM_INS_SXTB = 260
+ARM_INS_SXTB16 = 261
+ARM_INS_SXTH = 262
+ARM_INS_TBB = 263
+ARM_INS_TBH = 264
+ARM_INS_TEQ = 265
+ARM_INS_TRAP = 266
+ARM_INS_TSB = 267
+ARM_INS_TST = 268
+ARM_INS_TT = 269
+ARM_INS_TTA = 270
+ARM_INS_TTAT = 271
+ARM_INS_TTT = 272
+ARM_INS_UADD16 = 273
+ARM_INS_UADD8 = 274
+ARM_INS_UASX = 275
+ARM_INS_UBFX = 276
+ARM_INS_UDF = 277
+ARM_INS_UDIV = 278
+ARM_INS_UHADD16 = 279
+ARM_INS_UHADD8 = 280
+ARM_INS_UHASX = 281
+ARM_INS_UHSAX = 282
+ARM_INS_UHSUB16 = 283
+ARM_INS_UHSUB8 = 284
+ARM_INS_UMAAL = 285
+ARM_INS_UMLAL = 286
+ARM_INS_UMULL = 287
+ARM_INS_UQADD16 = 288
+ARM_INS_UQADD8 = 289
+ARM_INS_UQASX = 290
+ARM_INS_UQSAX = 291
+ARM_INS_UQSUB16 = 292
+ARM_INS_UQSUB8 = 293
+ARM_INS_USAD8 = 294
+ARM_INS_USADA8 = 295
+ARM_INS_USAT = 296
+ARM_INS_USAT16 = 297
+ARM_INS_USAX = 298
+ARM_INS_USUB16 = 299
+ARM_INS_USUB8 = 300
+ARM_INS_UXTAB = 301
+ARM_INS_UXTAB16 = 302
+ARM_INS_UXTAH = 303
+ARM_INS_UXTB = 304
+ARM_INS_UXTB16 = 305
+ARM_INS_UXTH = 306
+ARM_INS_VABA = 307
+ARM_INS_VABAL = 308
+ARM_INS_VABD = 309
+ARM_INS_VABDL = 310
+ARM_INS_VABS = 311
+ARM_INS_VACGE = 312
+ARM_INS_VACGT = 313
+ARM_INS_VACLE = 314
+ARM_INS_VACLT = 315
+ARM_INS_VADD = 316
+ARM_INS_VADDHN = 317
+ARM_INS_VADDL = 318
+ARM_INS_VADDW = 319
+ARM_INS_VAND = 320
+ARM_INS_VBIC = 321
+ARM_INS_VBIF = 322
+ARM_INS_VBIT = 323
+ARM_INS_VBSL = 324
+ARM_INS_VCADD = 325
+ARM_INS_VCEQ = 326
+ARM_INS_VCGE = 327
+ARM_INS_VCGT = 328
+ARM_INS_VCLE = 329
+ARM_INS_VCLS = 330
+ARM_INS_VCLT = 331
+ARM_INS_VCLZ = 332
+ARM_INS_VCMLA = 333
+ARM_INS_VCMP = 334
+ARM_INS_VCMPE = 335
+ARM_INS_VCNT = 336
+ARM_INS_VCVT = 337
+ARM_INS_VCVTA = 338
+ARM_INS_VCVTB = 339
+ARM_INS_VCVTM = 340
+ARM_INS_VCVTN = 341
+ARM_INS_VCVTP = 342
+ARM_INS_VCVTR = 343
+ARM_INS_VCVTT = 344
+ARM_INS_VDIV = 345
+ARM_INS_VDUP = 346
+ARM_INS_VEOR = 347
+ARM_INS_VEXT = 348
+ARM_INS_VFMA = 349
+ARM_INS_VFMS = 350
+ARM_INS_VFNMA = 351
+ARM_INS_VFNMS = 352
+ARM_INS_VHADD = 353
+ARM_INS_VHSUB = 354
+ARM_INS_VINS = 355
+ARM_INS_VJCVT = 356
+ARM_INS_VLD1 = 357
+ARM_INS_VLD2 = 358
+ARM_INS_VLD3 = 359
+ARM_INS_VLD4 = 360
+ARM_INS_VLDMDB = 361
+ARM_INS_VLDMIA = 362
+ARM_INS_VLDR = 363
+ARM_INS_VLLDM = 364
+ARM_INS_VLSTM = 365
+ARM_INS_VMAX = 366
+ARM_INS_VMAXNM = 367
+ARM_INS_VMIN = 368
+ARM_INS_VMINNM = 369
+ARM_INS_VMLA = 370
+ARM_INS_VMLAL = 371
+ARM_INS_VMLS = 372
+ARM_INS_VMLSL = 373
+ARM_INS_VMOV = 374
+ARM_INS_VMOVL = 375
+ARM_INS_VMOVN = 376
+ARM_INS_VMOVX = 377
+ARM_INS_VMRS = 378
+ARM_INS_VMSR = 379
+ARM_INS_VMUL = 380
+ARM_INS_VMULL = 381
+ARM_INS_VMVN = 382
+ARM_INS_VNEG = 383
+ARM_INS_VNMLA = 384
+ARM_INS_VNMLS = 385
+ARM_INS_VNMUL = 386
+ARM_INS_VORN = 387
+ARM_INS_VORR = 388
+ARM_INS_VPADAL = 389
+ARM_INS_VPADD = 390
+ARM_INS_VPADDL = 391
+ARM_INS_VPMAX = 392
+ARM_INS_VPMIN = 393
+ARM_INS_VPOP = 394
+ARM_INS_VPUSH = 395
+ARM_INS_VQABS = 396
+ARM_INS_VQADD = 397
+ARM_INS_VQDMLAL = 398
+ARM_INS_VQDMLSL = 399
+ARM_INS_VQDMULH = 400
+ARM_INS_VQDMULL = 401
+ARM_INS_VQMOVN = 402
+ARM_INS_VQMOVUN = 403
+ARM_INS_VQNEG = 404
+ARM_INS_VQRDMLAH = 405
+ARM_INS_VQRDMLSH = 406
+ARM_INS_VQRDMULH = 407
+ARM_INS_VQRSHL = 408
+ARM_INS_VQRSHRN = 409
+ARM_INS_VQRSHRUN = 410
+ARM_INS_VQSHL = 411
+ARM_INS_VQSHLU = 412
+ARM_INS_VQSHRN = 413
+ARM_INS_VQSHRUN = 414
+ARM_INS_VQSUB = 415
+ARM_INS_VRADDHN = 416
+ARM_INS_VRECPE = 417
+ARM_INS_VRECPS = 418
+ARM_INS_VREV16 = 419
+ARM_INS_VREV32 = 420
+ARM_INS_VREV64 = 421
+ARM_INS_VRHADD = 422
+ARM_INS_VRINTA = 423
+ARM_INS_VRINTM = 424
+ARM_INS_VRINTN = 425
+ARM_INS_VRINTP = 426
+ARM_INS_VRINTR = 427
+ARM_INS_VRINTX = 428
+ARM_INS_VRINTZ = 429
+ARM_INS_VRSHL = 430
+ARM_INS_VRSHR = 431
+ARM_INS_VRSHRN = 432
+ARM_INS_VRSQRTE = 433
+ARM_INS_VRSQRTS = 434
+ARM_INS_VRSRA = 435
+ARM_INS_VRSUBHN = 436
+ARM_INS_VSDOT = 437
+ARM_INS_VSELEQ = 438
+ARM_INS_VSELGE = 439
+ARM_INS_VSELGT = 440
+ARM_INS_VSELVS = 441
+ARM_INS_VSHL = 442
+ARM_INS_VSHLL = 443
+ARM_INS_VSHR = 444
+ARM_INS_VSHRN = 445
+ARM_INS_VSLI = 446
+ARM_INS_VSQRT = 447
+ARM_INS_VSRA = 448
+ARM_INS_VSRI = 449
+ARM_INS_VST1 = 450
+ARM_INS_VST2 = 451
+ARM_INS_VST3 = 452
+ARM_INS_VST4 = 453
+ARM_INS_VSTMDB = 454
+ARM_INS_VSTMIA = 455
+ARM_INS_VSTR = 456
+ARM_INS_VSUB = 457
+ARM_INS_VSUBHN = 458
+ARM_INS_VSUBL = 459
+ARM_INS_VSUBW = 460
+ARM_INS_VSWP = 461
+ARM_INS_VTBL = 462
+ARM_INS_VTBX = 463
+ARM_INS_VTRN = 464
+ARM_INS_VTST = 465
+ARM_INS_VUDOT = 466
+ARM_INS_VUZP = 467
+ARM_INS_VZIP = 468
+ARM_INS_WFE = 469
+ARM_INS_WFI = 470
+ARM_INS_YIELD = 471
+ARM_INS_ENDING = 472
+
+ARM_GRP_INVALID = 0
+ARM_GRP_JUMP = 1
+ARM_GRP_CALL = 2
+ARM_GRP_INT = 4
+ARM_GRP_PRIVILEGE = 6
+ARM_GRP_BRANCH_RELATIVE = 7
+ARM_GRP_CRYPTO = 128
+ARM_GRP_DATABARRIER = 129
+ARM_GRP_DIVIDE = 130
+ARM_GRP_FPARMV8 = 131
+ARM_GRP_MULTPRO = 132
+ARM_GRP_NEON = 133
+ARM_GRP_T2EXTRACTPACK = 134
+ARM_GRP_THUMB2DSP = 135
+ARM_GRP_TRUSTZONE = 136
+ARM_GRP_V4T = 137
+ARM_GRP_V5T = 138
+ARM_GRP_V5TE = 139
+ARM_GRP_V6 = 140
+ARM_GRP_V6T2 = 141
+ARM_GRP_V7 = 142
+ARM_GRP_V8 = 143
+ARM_GRP_VFP2 = 144
+ARM_GRP_VFP3 = 145
+ARM_GRP_VFP4 = 146
+ARM_GRP_ARM = 147
+ARM_GRP_MCLASS = 148
+ARM_GRP_NOTMCLASS = 149
+ARM_GRP_THUMB = 150
+ARM_GRP_THUMB1ONLY = 151
+ARM_GRP_THUMB2 = 152
+ARM_GRP_PREV8 = 153
+ARM_GRP_FPVMLX = 154
+ARM_GRP_MULOPS = 155
+ARM_GRP_CRC = 156
+ARM_GRP_DPVFP = 157
+ARM_GRP_V6M = 158
+ARM_GRP_VIRTUALIZATION = 159
+ARM_GRP_ENDING = 160

.tools/python-revlibs/capstone/bpf.py

@@ -0,0 +1,69 @@
+# Capstone Python bindings
+# BPF by david942j <david942j@gmail.com>, 2019
+
+import ctypes
+from . import copy_ctypes_list
+from .bpf_const import *
+
+class BPFOpMem(ctypes.Structure):
+    _fields_ = (
+        ('base', ctypes.c_uint8),
+        ('disp', ctypes.c_int32),
+    )
+
+class BPFOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint8),
+        ('imm', ctypes.c_uint64),
+        ('off', ctypes.c_uint32),
+        ('mem', BPFOpMem),
+        ('mmem', ctypes.c_uint32),
+        ('msh', ctypes.c_uint32),
+        ('ext', ctypes.c_uint32),
+    )
+
+class BPFOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', BPFOpValue),
+        ('access', ctypes.c_uint8),
+    )
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def off(self):
+        return self.value.off
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+    @property
+    def mmem(self):
+        return self.value.mmem
+
+    @property
+    def msh(self):
+        return self.value.msh
+
+    @property
+    def ext(self):
+        return self.value.ext
+
+
+class CsBPF(ctypes.Structure):
+    _fields_ = (
+        ('op_count', ctypes.c_uint8),
+        ('operands', BPFOp * 4),
+    )
+
+def get_arch_info(a):
+    return (copy_ctypes_list(a.operands[:a.op_count]))
+

.tools/python-revlibs/capstone/bpf_const.py

@@ -0,0 +1,115 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [bpf_const.py]
+
+BPF_OP_INVALID = 0
+BPF_OP_REG = 1
+BPF_OP_IMM = 2
+BPF_OP_OFF = 3
+BPF_OP_MEM = 4
+BPF_OP_MMEM = 5
+BPF_OP_MSH = 6
+BPF_OP_EXT = 7
+
+BPF_REG_INVALID = 0
+BPF_REG_A = 1
+BPF_REG_X = 2
+BPF_REG_R0 = 3
+BPF_REG_R1 = 4
+BPF_REG_R2 = 5
+BPF_REG_R3 = 6
+BPF_REG_R4 = 7
+BPF_REG_R5 = 8
+BPF_REG_R6 = 9
+BPF_REG_R7 = 10
+BPF_REG_R8 = 11
+BPF_REG_R9 = 12
+BPF_REG_R10 = 13
+BPF_REG_ENDING = 14
+
+BPF_EXT_INVALID = 0
+BPF_EXT_LEN = 1
+
+BPF_INS_INVALID = 0
+BPF_INS_ADD = 1
+BPF_INS_SUB = 2
+BPF_INS_MUL = 3
+BPF_INS_DIV = 4
+BPF_INS_OR = 5
+BPF_INS_AND = 6
+BPF_INS_LSH = 7
+BPF_INS_RSH = 8
+BPF_INS_NEG = 9
+BPF_INS_MOD = 10
+BPF_INS_XOR = 11
+BPF_INS_MOV = 12
+BPF_INS_ARSH = 13
+BPF_INS_ADD64 = 14
+BPF_INS_SUB64 = 15
+BPF_INS_MUL64 = 16
+BPF_INS_DIV64 = 17
+BPF_INS_OR64 = 18
+BPF_INS_AND64 = 19
+BPF_INS_LSH64 = 20
+BPF_INS_RSH64 = 21
+BPF_INS_NEG64 = 22
+BPF_INS_MOD64 = 23
+BPF_INS_XOR64 = 24
+BPF_INS_MOV64 = 25
+BPF_INS_ARSH64 = 26
+BPF_INS_LE16 = 27
+BPF_INS_LE32 = 28
+BPF_INS_LE64 = 29
+BPF_INS_BE16 = 30
+BPF_INS_BE32 = 31
+BPF_INS_BE64 = 32
+BPF_INS_LDW = 33
+BPF_INS_LDH = 34
+BPF_INS_LDB = 35
+BPF_INS_LDDW = 36
+BPF_INS_LDXW = 37
+BPF_INS_LDXH = 38
+BPF_INS_LDXB = 39
+BPF_INS_LDXDW = 40
+BPF_INS_STW = 41
+BPF_INS_STH = 42
+BPF_INS_STB = 43
+BPF_INS_STDW = 44
+BPF_INS_STXW = 45
+BPF_INS_STXH = 46
+BPF_INS_STXB = 47
+BPF_INS_STXDW = 48
+BPF_INS_XADDW = 49
+BPF_INS_XADDDW = 50
+BPF_INS_JMP = 51
+BPF_INS_JEQ = 52
+BPF_INS_JGT = 53
+BPF_INS_JGE = 54
+BPF_INS_JSET = 55
+BPF_INS_JNE = 56
+BPF_INS_JSGT = 57
+BPF_INS_JSGE = 58
+BPF_INS_CALL = 59
+BPF_INS_CALLX = 60
+BPF_INS_EXIT = 61
+BPF_INS_JLT = 62
+BPF_INS_JLE = 63
+BPF_INS_JSLT = 64
+BPF_INS_JSLE = 65
+BPF_INS_RET = 66
+BPF_INS_TAX = 67
+BPF_INS_TXA = 68
+BPF_INS_ENDING = 69
+BPF_INS_LD = BPF_INS_LDW
+BPF_INS_LDX = BPF_INS_LDXW
+BPF_INS_ST = BPF_INS_STW
+BPF_INS_STX = BPF_INS_STXW
+
+BPF_GRP_INVALID = 0
+BPF_GRP_LOAD = 1
+BPF_GRP_STORE = 2
+BPF_GRP_ALU = 3
+BPF_GRP_JUMP = 4
+BPF_GRP_CALL = 5
+BPF_GRP_RETURN = 6
+BPF_GRP_MISC = 7
+BPF_GRP_ENDING = 8

.tools/python-revlibs/capstone/evm.py

@@ -0,0 +1,17 @@
+# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
+
+import ctypes
+from . import copy_ctypes_list
+from .evm_const import *
+
+# define the API
+class CsEvm(ctypes.Structure):
+    _fields_ = (
+        ('pop', ctypes.c_byte),
+        ('push', ctypes.c_byte),
+        ('fee', ctypes.c_uint),
+    )
+
+def get_arch_info(a):
+    return (a.pop, a.push, a.fee)
+

.tools/python-revlibs/capstone/evm_const.py

@@ -0,0 +1,152 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [evm_const.py]
+
+EVM_INS_STOP = 0
+EVM_INS_ADD = 1
+EVM_INS_MUL = 2
+EVM_INS_SUB = 3
+EVM_INS_DIV = 4
+EVM_INS_SDIV = 5
+EVM_INS_MOD = 6
+EVM_INS_SMOD = 7
+EVM_INS_ADDMOD = 8
+EVM_INS_MULMOD = 9
+EVM_INS_EXP = 10
+EVM_INS_SIGNEXTEND = 11
+EVM_INS_LT = 16
+EVM_INS_GT = 17
+EVM_INS_SLT = 18
+EVM_INS_SGT = 19
+EVM_INS_EQ = 20
+EVM_INS_ISZERO = 21
+EVM_INS_AND = 22
+EVM_INS_OR = 23
+EVM_INS_XOR = 24
+EVM_INS_NOT = 25
+EVM_INS_BYTE = 26
+EVM_INS_SHA3 = 32
+EVM_INS_ADDRESS = 48
+EVM_INS_BALANCE = 49
+EVM_INS_ORIGIN = 50
+EVM_INS_CALLER = 51
+EVM_INS_CALLVALUE = 52
+EVM_INS_CALLDATALOAD = 53
+EVM_INS_CALLDATASIZE = 54
+EVM_INS_CALLDATACOPY = 55
+EVM_INS_CODESIZE = 56
+EVM_INS_CODECOPY = 57
+EVM_INS_GASPRICE = 58
+EVM_INS_EXTCODESIZE = 59
+EVM_INS_EXTCODECOPY = 60
+EVM_INS_RETURNDATASIZE = 61
+EVM_INS_RETURNDATACOPY = 62
+EVM_INS_BLOCKHASH = 64
+EVM_INS_COINBASE = 65
+EVM_INS_TIMESTAMP = 66
+EVM_INS_NUMBER = 67
+EVM_INS_DIFFICULTY = 68
+EVM_INS_GASLIMIT = 69
+EVM_INS_POP = 80
+EVM_INS_MLOAD = 81
+EVM_INS_MSTORE = 82
+EVM_INS_MSTORE8 = 83
+EVM_INS_SLOAD = 84
+EVM_INS_SSTORE = 85
+EVM_INS_JUMP = 86
+EVM_INS_JUMPI = 87
+EVM_INS_PC = 88
+EVM_INS_MSIZE = 89
+EVM_INS_GAS = 90
+EVM_INS_JUMPDEST = 91
+EVM_INS_PUSH1 = 96
+EVM_INS_PUSH2 = 97
+EVM_INS_PUSH3 = 98
+EVM_INS_PUSH4 = 99
+EVM_INS_PUSH5 = 100
+EVM_INS_PUSH6 = 101
+EVM_INS_PUSH7 = 102
+EVM_INS_PUSH8 = 103
+EVM_INS_PUSH9 = 104
+EVM_INS_PUSH10 = 105
+EVM_INS_PUSH11 = 106
+EVM_INS_PUSH12 = 107
+EVM_INS_PUSH13 = 108
+EVM_INS_PUSH14 = 109
+EVM_INS_PUSH15 = 110
+EVM_INS_PUSH16 = 111
+EVM_INS_PUSH17 = 112
+EVM_INS_PUSH18 = 113
+EVM_INS_PUSH19 = 114
+EVM_INS_PUSH20 = 115
+EVM_INS_PUSH21 = 116
+EVM_INS_PUSH22 = 117
+EVM_INS_PUSH23 = 118
+EVM_INS_PUSH24 = 119
+EVM_INS_PUSH25 = 120
+EVM_INS_PUSH26 = 121
+EVM_INS_PUSH27 = 122
+EVM_INS_PUSH28 = 123
+EVM_INS_PUSH29 = 124
+EVM_INS_PUSH30 = 125
+EVM_INS_PUSH31 = 126
+EVM_INS_PUSH32 = 127
+EVM_INS_DUP1 = 128
+EVM_INS_DUP2 = 129
+EVM_INS_DUP3 = 130
+EVM_INS_DUP4 = 131
+EVM_INS_DUP5 = 132
+EVM_INS_DUP6 = 133
+EVM_INS_DUP7 = 134
+EVM_INS_DUP8 = 135
+EVM_INS_DUP9 = 136
+EVM_INS_DUP10 = 137
+EVM_INS_DUP11 = 138
+EVM_INS_DUP12 = 139
+EVM_INS_DUP13 = 140
+EVM_INS_DUP14 = 141
+EVM_INS_DUP15 = 142
+EVM_INS_DUP16 = 143
+EVM_INS_SWAP1 = 144
+EVM_INS_SWAP2 = 145
+EVM_INS_SWAP3 = 146
+EVM_INS_SWAP4 = 147
+EVM_INS_SWAP5 = 148
+EVM_INS_SWAP6 = 149
+EVM_INS_SWAP7 = 150
+EVM_INS_SWAP8 = 151
+EVM_INS_SWAP9 = 152
+EVM_INS_SWAP10 = 153
+EVM_INS_SWAP11 = 154
+EVM_INS_SWAP12 = 155
+EVM_INS_SWAP13 = 156
+EVM_INS_SWAP14 = 157
+EVM_INS_SWAP15 = 158
+EVM_INS_SWAP16 = 159
+EVM_INS_LOG0 = 160
+EVM_INS_LOG1 = 161
+EVM_INS_LOG2 = 162
+EVM_INS_LOG3 = 163
+EVM_INS_LOG4 = 164
+EVM_INS_CREATE = 240
+EVM_INS_CALL = 241
+EVM_INS_CALLCODE = 242
+EVM_INS_RETURN = 243
+EVM_INS_DELEGATECALL = 244
+EVM_INS_CALLBLACKBOX = 245
+EVM_INS_STATICCALL = 250
+EVM_INS_REVERT = 253
+EVM_INS_SUICIDE = 255
+EVM_INS_INVALID = 512
+EVM_INS_ENDING = 513
+
+EVM_GRP_INVALID = 0
+EVM_GRP_JUMP = 1
+EVM_GRP_MATH = 8
+EVM_GRP_STACK_WRITE = 9
+EVM_GRP_STACK_READ = 10
+EVM_GRP_MEM_WRITE = 11
+EVM_GRP_MEM_READ = 12
+EVM_GRP_STORE_WRITE = 13
+EVM_GRP_STORE_READ = 14
+EVM_GRP_HALT = 15
+EVM_GRP_ENDING = 16

.tools/python-revlibs/capstone/include/capstone/arm.h

@@ -0,0 +1,991 @@
+#ifndef CAPSTONE_ARM_H
+#define CAPSTONE_ARM_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// ARM shift type
+typedef enum arm_shifter {
+	ARM_SFT_INVALID = 0,
+	ARM_SFT_ASR,	///< shift with immediate const
+	ARM_SFT_LSL,	///< shift with immediate const
+	ARM_SFT_LSR,	///< shift with immediate const
+	ARM_SFT_ROR,	///< shift with immediate const
+	ARM_SFT_RRX,	///< shift with immediate const
+	ARM_SFT_ASR_REG,	///< shift with register
+	ARM_SFT_LSL_REG,	///< shift with register
+	ARM_SFT_LSR_REG,	///< shift with register
+	ARM_SFT_ROR_REG,	///< shift with register
+	ARM_SFT_RRX_REG,	///< shift with register
+} arm_shifter;
+
+/// ARM condition code
+typedef enum arm_cc {
+	ARM_CC_INVALID = 0,
+	ARM_CC_EQ,            ///< Equal                      Equal
+	ARM_CC_NE,            ///< Not equal                  Not equal, or unordered
+	ARM_CC_HS,            ///< Carry set                  >, ==, or unordered
+	ARM_CC_LO,            ///< Carry clear                Less than
+	ARM_CC_MI,            ///< Minus, negative            Less than
+	ARM_CC_PL,            ///< Plus, positive or zero     >, ==, or unordered
+	ARM_CC_VS,            ///< Overflow                   Unordered
+	ARM_CC_VC,            ///< No overflow                Not unordered
+	ARM_CC_HI,            ///< Unsigned higher            Greater than, or unordered
+	ARM_CC_LS,            ///< Unsigned lower or same     Less than or equal
+	ARM_CC_GE,            ///< Greater than or equal      Greater than or equal
+	ARM_CC_LT,            ///< Less than                  Less than, or unordered
+	ARM_CC_GT,            ///< Greater than               Greater than
+	ARM_CC_LE,            ///< Less than or equal         <, ==, or unordered
+	ARM_CC_AL             ///< Always (unconditional)     Always (unconditional)
+} arm_cc;
+
+typedef enum arm_sysreg {
+	/// Special registers for MSR
+	ARM_SYSREG_INVALID = 0,
+
+	// SPSR* registers can be OR combined
+	ARM_SYSREG_SPSR_C = 1,
+	ARM_SYSREG_SPSR_X = 2,
+	ARM_SYSREG_SPSR_S = 4,
+	ARM_SYSREG_SPSR_F = 8,
+
+	// CPSR* registers can be OR combined
+	ARM_SYSREG_CPSR_C = 16,
+	ARM_SYSREG_CPSR_X = 32,
+	ARM_SYSREG_CPSR_S = 64,
+	ARM_SYSREG_CPSR_F = 128,
+
+	// independent registers
+	ARM_SYSREG_APSR = 256,
+	ARM_SYSREG_APSR_G,
+	ARM_SYSREG_APSR_NZCVQ,
+	ARM_SYSREG_APSR_NZCVQG,
+
+	ARM_SYSREG_IAPSR,
+	ARM_SYSREG_IAPSR_G,
+	ARM_SYSREG_IAPSR_NZCVQG,
+	ARM_SYSREG_IAPSR_NZCVQ,
+
+	ARM_SYSREG_EAPSR,
+	ARM_SYSREG_EAPSR_G,
+	ARM_SYSREG_EAPSR_NZCVQG,
+	ARM_SYSREG_EAPSR_NZCVQ,
+
+	ARM_SYSREG_XPSR,
+	ARM_SYSREG_XPSR_G,
+	ARM_SYSREG_XPSR_NZCVQG,
+	ARM_SYSREG_XPSR_NZCVQ,
+
+	ARM_SYSREG_IPSR,
+	ARM_SYSREG_EPSR,
+	ARM_SYSREG_IEPSR,
+
+	ARM_SYSREG_MSP,
+	ARM_SYSREG_PSP,
+	ARM_SYSREG_PRIMASK,
+	ARM_SYSREG_BASEPRI,
+	ARM_SYSREG_BASEPRI_MAX,
+	ARM_SYSREG_FAULTMASK,
+	ARM_SYSREG_CONTROL,
+	ARM_SYSREG_MSPLIM,
+	ARM_SYSREG_PSPLIM,
+	ARM_SYSREG_MSP_NS,
+	ARM_SYSREG_PSP_NS,
+	ARM_SYSREG_MSPLIM_NS,
+	ARM_SYSREG_PSPLIM_NS,
+	ARM_SYSREG_PRIMASK_NS,
+	ARM_SYSREG_BASEPRI_NS,
+	ARM_SYSREG_FAULTMASK_NS,
+	ARM_SYSREG_CONTROL_NS,
+	ARM_SYSREG_SP_NS,
+
+	// Banked Registers
+	ARM_SYSREG_R8_USR,
+	ARM_SYSREG_R9_USR,
+	ARM_SYSREG_R10_USR,
+	ARM_SYSREG_R11_USR,
+	ARM_SYSREG_R12_USR,
+	ARM_SYSREG_SP_USR,
+	ARM_SYSREG_LR_USR,
+	ARM_SYSREG_R8_FIQ,
+	ARM_SYSREG_R9_FIQ,
+	ARM_SYSREG_R10_FIQ,
+	ARM_SYSREG_R11_FIQ,
+	ARM_SYSREG_R12_FIQ,
+	ARM_SYSREG_SP_FIQ,
+	ARM_SYSREG_LR_FIQ,
+	ARM_SYSREG_LR_IRQ,
+	ARM_SYSREG_SP_IRQ,
+	ARM_SYSREG_LR_SVC,
+	ARM_SYSREG_SP_SVC,
+	ARM_SYSREG_LR_ABT,
+	ARM_SYSREG_SP_ABT,
+	ARM_SYSREG_LR_UND,
+	ARM_SYSREG_SP_UND,
+	ARM_SYSREG_LR_MON,
+	ARM_SYSREG_SP_MON,
+	ARM_SYSREG_ELR_HYP,
+	ARM_SYSREG_SP_HYP,
+
+	ARM_SYSREG_SPSR_FIQ,
+	ARM_SYSREG_SPSR_IRQ,
+	ARM_SYSREG_SPSR_SVC,
+	ARM_SYSREG_SPSR_ABT,
+	ARM_SYSREG_SPSR_UND,
+	ARM_SYSREG_SPSR_MON,
+	ARM_SYSREG_SPSR_HYP,
+} arm_sysreg;
+
+/// The memory barrier constants map directly to the 4-bit encoding of
+/// the option field for Memory Barrier operations.
+typedef enum arm_mem_barrier {
+	ARM_MB_INVALID = 0,
+	ARM_MB_RESERVED_0,
+	ARM_MB_OSHLD,
+	ARM_MB_OSHST,
+	ARM_MB_OSH,
+	ARM_MB_RESERVED_4,
+	ARM_MB_NSHLD,
+	ARM_MB_NSHST,
+	ARM_MB_NSH,
+	ARM_MB_RESERVED_8,
+	ARM_MB_ISHLD,
+	ARM_MB_ISHST,
+	ARM_MB_ISH,
+	ARM_MB_RESERVED_12,
+	ARM_MB_LD,
+	ARM_MB_ST,
+	ARM_MB_SY,
+} arm_mem_barrier;
+
+/// Operand type for instruction's operands
+typedef enum arm_op_type {
+	ARM_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+	ARM_OP_REG, ///< = CS_OP_REG (Register operand).
+	ARM_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	ARM_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+	ARM_OP_FP,  ///< = CS_OP_FP (Floating-Point operand).
+	ARM_OP_CIMM = 64, ///< C-Immediate (coprocessor registers)
+	ARM_OP_PIMM, ///< P-Immediate (coprocessor registers)
+	ARM_OP_SETEND,	///< operand for SETEND instruction
+	ARM_OP_SYSREG,	///< MSR/MRS special register operand
+} arm_op_type;
+
+/// Operand type for SETEND instruction
+typedef enum arm_setend_type {
+	ARM_SETEND_INVALID = 0,	///< Uninitialized.
+	ARM_SETEND_BE,	///< BE operand.
+	ARM_SETEND_LE, ///< LE operand
+} arm_setend_type;
+
+typedef enum arm_cpsmode_type {
+	ARM_CPSMODE_INVALID = 0,
+	ARM_CPSMODE_IE = 2,
+	ARM_CPSMODE_ID = 3
+} arm_cpsmode_type;
+
+/// Operand type for SETEND instruction
+typedef enum arm_cpsflag_type {
+	ARM_CPSFLAG_INVALID = 0,
+	ARM_CPSFLAG_F = 1,
+	ARM_CPSFLAG_I = 2,
+	ARM_CPSFLAG_A = 4,
+	ARM_CPSFLAG_NONE = 16,	///< no flag
+} arm_cpsflag_type;
+
+/// Data type for elements of vector instructions.
+typedef enum arm_vectordata_type {
+	ARM_VECTORDATA_INVALID = 0,
+
+	// Integer type
+	ARM_VECTORDATA_I8,
+	ARM_VECTORDATA_I16,
+	ARM_VECTORDATA_I32,
+	ARM_VECTORDATA_I64,
+
+	// Signed integer type
+	ARM_VECTORDATA_S8,
+	ARM_VECTORDATA_S16,
+	ARM_VECTORDATA_S32,
+	ARM_VECTORDATA_S64,
+
+	// Unsigned integer type
+	ARM_VECTORDATA_U8,
+	ARM_VECTORDATA_U16,
+	ARM_VECTORDATA_U32,
+	ARM_VECTORDATA_U64,
+
+	// Data type for VMUL/VMULL
+	ARM_VECTORDATA_P8,
+
+	// Floating type
+	ARM_VECTORDATA_F16,
+	ARM_VECTORDATA_F32,
+	ARM_VECTORDATA_F64,
+
+	// Convert float <-> float
+	ARM_VECTORDATA_F16F64,	// f16.f64
+	ARM_VECTORDATA_F64F16,	// f64.f16
+	ARM_VECTORDATA_F32F16,	// f32.f16
+	ARM_VECTORDATA_F16F32,	// f32.f16
+	ARM_VECTORDATA_F64F32,	// f64.f32
+	ARM_VECTORDATA_F32F64,	// f32.f64
+
+	// Convert integer <-> float
+	ARM_VECTORDATA_S32F32,	// s32.f32
+	ARM_VECTORDATA_U32F32,	// u32.f32
+	ARM_VECTORDATA_F32S32,	// f32.s32
+	ARM_VECTORDATA_F32U32,	// f32.u32
+	ARM_VECTORDATA_F64S16,	// f64.s16
+	ARM_VECTORDATA_F32S16,	// f32.s16
+	ARM_VECTORDATA_F64S32,	// f64.s32
+	ARM_VECTORDATA_S16F64,	// s16.f64
+	ARM_VECTORDATA_S16F32,	// s16.f64
+	ARM_VECTORDATA_S32F64,	// s32.f64
+	ARM_VECTORDATA_U16F64,	// u16.f64
+	ARM_VECTORDATA_U16F32,	// u16.f32
+	ARM_VECTORDATA_U32F64,	// u32.f64
+	ARM_VECTORDATA_F64U16,	// f64.u16
+	ARM_VECTORDATA_F32U16,	// f32.u16
+	ARM_VECTORDATA_F64U32,	// f64.u32
+	ARM_VECTORDATA_F16U16,	// f16.u16
+	ARM_VECTORDATA_U16F16,	// u16.f16
+	ARM_VECTORDATA_F16U32,	// f16.u32
+	ARM_VECTORDATA_U32F16,	// u32.f16
+} arm_vectordata_type;
+
+/// ARM registers
+typedef enum arm_reg {
+	ARM_REG_INVALID = 0,
+	ARM_REG_APSR,
+	ARM_REG_APSR_NZCV,
+	ARM_REG_CPSR,
+	ARM_REG_FPEXC,
+	ARM_REG_FPINST,
+	ARM_REG_FPSCR,
+	ARM_REG_FPSCR_NZCV,
+	ARM_REG_FPSID,
+	ARM_REG_ITSTATE,
+	ARM_REG_LR,
+	ARM_REG_PC,
+	ARM_REG_SP,
+	ARM_REG_SPSR,
+	ARM_REG_D0,
+	ARM_REG_D1,
+	ARM_REG_D2,
+	ARM_REG_D3,
+	ARM_REG_D4,
+	ARM_REG_D5,
+	ARM_REG_D6,
+	ARM_REG_D7,
+	ARM_REG_D8,
+	ARM_REG_D9,
+	ARM_REG_D10,
+	ARM_REG_D11,
+	ARM_REG_D12,
+	ARM_REG_D13,
+	ARM_REG_D14,
+	ARM_REG_D15,
+	ARM_REG_D16,
+	ARM_REG_D17,
+	ARM_REG_D18,
+	ARM_REG_D19,
+	ARM_REG_D20,
+	ARM_REG_D21,
+	ARM_REG_D22,
+	ARM_REG_D23,
+	ARM_REG_D24,
+	ARM_REG_D25,
+	ARM_REG_D26,
+	ARM_REG_D27,
+	ARM_REG_D28,
+	ARM_REG_D29,
+	ARM_REG_D30,
+	ARM_REG_D31,
+	ARM_REG_FPINST2,
+	ARM_REG_MVFR0,
+	ARM_REG_MVFR1,
+	ARM_REG_MVFR2,
+	ARM_REG_Q0,
+	ARM_REG_Q1,
+	ARM_REG_Q2,
+	ARM_REG_Q3,
+	ARM_REG_Q4,
+	ARM_REG_Q5,
+	ARM_REG_Q6,
+	ARM_REG_Q7,
+	ARM_REG_Q8,
+	ARM_REG_Q9,
+	ARM_REG_Q10,
+	ARM_REG_Q11,
+	ARM_REG_Q12,
+	ARM_REG_Q13,
+	ARM_REG_Q14,
+	ARM_REG_Q15,
+	ARM_REG_R0,
+	ARM_REG_R1,
+	ARM_REG_R2,
+	ARM_REG_R3,
+	ARM_REG_R4,
+	ARM_REG_R5,
+	ARM_REG_R6,
+	ARM_REG_R7,
+	ARM_REG_R8,
+	ARM_REG_R9,
+	ARM_REG_R10,
+	ARM_REG_R11,
+	ARM_REG_R12,
+	ARM_REG_S0,
+	ARM_REG_S1,
+	ARM_REG_S2,
+	ARM_REG_S3,
+	ARM_REG_S4,
+	ARM_REG_S5,
+	ARM_REG_S6,
+	ARM_REG_S7,
+	ARM_REG_S8,
+	ARM_REG_S9,
+	ARM_REG_S10,
+	ARM_REG_S11,
+	ARM_REG_S12,
+	ARM_REG_S13,
+	ARM_REG_S14,
+	ARM_REG_S15,
+	ARM_REG_S16,
+	ARM_REG_S17,
+	ARM_REG_S18,
+	ARM_REG_S19,
+	ARM_REG_S20,
+	ARM_REG_S21,
+	ARM_REG_S22,
+	ARM_REG_S23,
+	ARM_REG_S24,
+	ARM_REG_S25,
+	ARM_REG_S26,
+	ARM_REG_S27,
+	ARM_REG_S28,
+	ARM_REG_S29,
+	ARM_REG_S30,
+	ARM_REG_S31,
+
+	ARM_REG_ENDING,		// <-- mark the end of the list or registers
+
+	// alias registers
+	ARM_REG_R13 = ARM_REG_SP,
+	ARM_REG_R14 = ARM_REG_LR,
+	ARM_REG_R15 = ARM_REG_PC,
+
+	ARM_REG_SB = ARM_REG_R9,
+	ARM_REG_SL = ARM_REG_R10,
+	ARM_REG_FP = ARM_REG_R11,
+	ARM_REG_IP = ARM_REG_R12,
+} arm_reg;
+
+/// Instruction's operand referring to memory
+/// This is associated with ARM_OP_MEM operand type above
+typedef struct arm_op_mem {
+	arm_reg base;	///< base register
+	arm_reg index;	///< index register
+	int scale;	///< scale for index register (can be 1, or -1)
+	int disp;	///< displacement/offset value
+	/// left-shift on index register, or 0 if irrelevant
+	/// NOTE: this value can also be fetched via operand.shift.value
+	int lshift;
+} arm_op_mem;
+
+/// Instruction operand
+typedef struct cs_arm_op {
+	int vector_index;	///< Vector Index for some vector operands (or -1 if irrelevant)
+
+	struct {
+		arm_shifter type;
+		unsigned int value;
+	} shift;
+
+	arm_op_type type;	///< operand type
+
+	union {
+		int reg;	///< register value for REG/SYSREG operand
+		int32_t imm;			///< immediate value for C-IMM, P-IMM or IMM operand
+		double fp;			///< floating point value for FP operand
+		arm_op_mem mem;		///< base/index/scale/disp value for MEM operand
+		arm_setend_type setend; ///< SETEND instruction's operand type
+	};
+
+	/// in some instructions, an operand can be subtracted or added to
+	/// the base register,
+	/// if TRUE, this operand is subtracted. otherwise, it is added.
+	bool subtracted;
+
+	/// How is this operand accessed? (READ, WRITE or READ|WRITE)
+	/// This field is combined of cs_ac_type.
+	/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
+	uint8_t access;
+
+	/// Neon lane index for NEON instructions (or -1 if irrelevant)
+	int8_t neon_lane;
+} cs_arm_op;
+
+/// Instruction structure
+typedef struct cs_arm {
+	bool usermode;	///< User-mode registers to be loaded (for LDM/STM instructions)
+	int vector_size; 	///< Scalar size for vector instructions
+	arm_vectordata_type vector_data; ///< Data type for elements of vector instructions
+	arm_cpsmode_type cps_mode;	///< CPS mode for CPS instruction
+	arm_cpsflag_type cps_flag;	///< CPS mode for CPS instruction
+	arm_cc cc;			///< conditional code for this insn
+	bool update_flags;	///< does this insn update flags?
+	bool writeback;		///< does this insn write-back?
+	bool post_index;	///< only set if writeback is 'True', if 'False' pre-index, otherwise post.
+	arm_mem_barrier mem_barrier;	///< Option for some memory barrier instructions
+
+	/// Number of operands of this instruction,
+	/// or 0 when instruction has no operand.
+	uint8_t op_count;
+
+	cs_arm_op operands[36];	///< operands for this instruction.
+} cs_arm;
+
+/// ARM instruction
+typedef enum arm_insn {
+	ARM_INS_INVALID = 0,
+
+	ARM_INS_ADC,
+	ARM_INS_ADD,
+	ARM_INS_ADDW,
+	ARM_INS_ADR,
+	ARM_INS_AESD,
+	ARM_INS_AESE,
+	ARM_INS_AESIMC,
+	ARM_INS_AESMC,
+	ARM_INS_AND,
+	ARM_INS_ASR,
+	ARM_INS_B,
+	ARM_INS_BFC,
+	ARM_INS_BFI,
+	ARM_INS_BIC,
+	ARM_INS_BKPT,
+	ARM_INS_BL,
+	ARM_INS_BLX,
+	ARM_INS_BLXNS,
+	ARM_INS_BX,
+	ARM_INS_BXJ,
+	ARM_INS_BXNS,
+	ARM_INS_CBNZ,
+	ARM_INS_CBZ,
+	ARM_INS_CDP,
+	ARM_INS_CDP2,
+	ARM_INS_CLREX,
+	ARM_INS_CLZ,
+	ARM_INS_CMN,
+	ARM_INS_CMP,
+	ARM_INS_CPS,
+	ARM_INS_CRC32B,
+	ARM_INS_CRC32CB,
+	ARM_INS_CRC32CH,
+	ARM_INS_CRC32CW,
+	ARM_INS_CRC32H,
+	ARM_INS_CRC32W,
+	ARM_INS_CSDB,
+	ARM_INS_DBG,
+	ARM_INS_DCPS1,
+	ARM_INS_DCPS2,
+	ARM_INS_DCPS3,
+	ARM_INS_DFB,
+	ARM_INS_DMB,
+	ARM_INS_DSB,
+	ARM_INS_EOR,
+	ARM_INS_ERET,
+	ARM_INS_ESB,
+	ARM_INS_FADDD,
+	ARM_INS_FADDS,
+	ARM_INS_FCMPZD,
+	ARM_INS_FCMPZS,
+	ARM_INS_FCONSTD,
+	ARM_INS_FCONSTS,
+	ARM_INS_FLDMDBX,
+	ARM_INS_FLDMIAX,
+	ARM_INS_FMDHR,
+	ARM_INS_FMDLR,
+	ARM_INS_FMSTAT,
+	ARM_INS_FSTMDBX,
+	ARM_INS_FSTMIAX,
+	ARM_INS_FSUBD,
+	ARM_INS_FSUBS,
+	ARM_INS_HINT,
+	ARM_INS_HLT,
+	ARM_INS_HVC,
+	ARM_INS_ISB,
+	ARM_INS_IT,
+	ARM_INS_LDA,
+	ARM_INS_LDAB,
+	ARM_INS_LDAEX,
+	ARM_INS_LDAEXB,
+	ARM_INS_LDAEXD,
+	ARM_INS_LDAEXH,
+	ARM_INS_LDAH,
+	ARM_INS_LDC,
+	ARM_INS_LDC2,
+	ARM_INS_LDC2L,
+	ARM_INS_LDCL,
+	ARM_INS_LDM,
+	ARM_INS_LDMDA,
+	ARM_INS_LDMDB,
+	ARM_INS_LDMIB,
+	ARM_INS_LDR,
+	ARM_INS_LDRB,
+	ARM_INS_LDRBT,
+	ARM_INS_LDRD,
+	ARM_INS_LDREX,
+	ARM_INS_LDREXB,
+	ARM_INS_LDREXD,
+	ARM_INS_LDREXH,
+	ARM_INS_LDRH,
+	ARM_INS_LDRHT,
+	ARM_INS_LDRSB,
+	ARM_INS_LDRSBT,
+	ARM_INS_LDRSH,
+	ARM_INS_LDRSHT,
+	ARM_INS_LDRT,
+	ARM_INS_LSL,
+	ARM_INS_LSR,
+	ARM_INS_MCR,
+	ARM_INS_MCR2,
+	ARM_INS_MCRR,
+	ARM_INS_MCRR2,
+	ARM_INS_MLA,
+	ARM_INS_MLS,
+	ARM_INS_MOV,
+	ARM_INS_MOVS,
+	ARM_INS_MOVT,
+	ARM_INS_MOVW,
+	ARM_INS_MRC,
+	ARM_INS_MRC2,
+	ARM_INS_MRRC,
+	ARM_INS_MRRC2,
+	ARM_INS_MRS,
+	ARM_INS_MSR,
+	ARM_INS_MUL,
+	ARM_INS_MVN,
+	ARM_INS_NEG,
+	ARM_INS_NOP,
+	ARM_INS_ORN,
+	ARM_INS_ORR,
+	ARM_INS_PKHBT,
+	ARM_INS_PKHTB,
+	ARM_INS_PLD,
+	ARM_INS_PLDW,
+	ARM_INS_PLI,
+	ARM_INS_POP,
+	ARM_INS_PUSH,
+	ARM_INS_QADD,
+	ARM_INS_QADD16,
+	ARM_INS_QADD8,
+	ARM_INS_QASX,
+	ARM_INS_QDADD,
+	ARM_INS_QDSUB,
+	ARM_INS_QSAX,
+	ARM_INS_QSUB,
+	ARM_INS_QSUB16,
+	ARM_INS_QSUB8,
+	ARM_INS_RBIT,
+	ARM_INS_REV,
+	ARM_INS_REV16,
+	ARM_INS_REVSH,
+	ARM_INS_RFEDA,
+	ARM_INS_RFEDB,
+	ARM_INS_RFEIA,
+	ARM_INS_RFEIB,
+	ARM_INS_ROR,
+	ARM_INS_RRX,
+	ARM_INS_RSB,
+	ARM_INS_RSC,
+	ARM_INS_SADD16,
+	ARM_INS_SADD8,
+	ARM_INS_SASX,
+	ARM_INS_SBC,
+	ARM_INS_SBFX,
+	ARM_INS_SDIV,
+	ARM_INS_SEL,
+	ARM_INS_SETEND,
+	ARM_INS_SETPAN,
+	ARM_INS_SEV,
+	ARM_INS_SEVL,
+	ARM_INS_SG,
+	ARM_INS_SHA1C,
+	ARM_INS_SHA1H,
+	ARM_INS_SHA1M,
+	ARM_INS_SHA1P,
+	ARM_INS_SHA1SU0,
+	ARM_INS_SHA1SU1,
+	ARM_INS_SHA256H,
+	ARM_INS_SHA256H2,
+	ARM_INS_SHA256SU0,
+	ARM_INS_SHA256SU1,
+	ARM_INS_SHADD16,
+	ARM_INS_SHADD8,
+	ARM_INS_SHASX,
+	ARM_INS_SHSAX,
+	ARM_INS_SHSUB16,
+	ARM_INS_SHSUB8,
+	ARM_INS_SMC,
+	ARM_INS_SMLABB,
+	ARM_INS_SMLABT,
+	ARM_INS_SMLAD,
+	ARM_INS_SMLADX,
+	ARM_INS_SMLAL,
+	ARM_INS_SMLALBB,
+	ARM_INS_SMLALBT,
+	ARM_INS_SMLALD,
+	ARM_INS_SMLALDX,
+	ARM_INS_SMLALTB,
+	ARM_INS_SMLALTT,
+	ARM_INS_SMLATB,
+	ARM_INS_SMLATT,
+	ARM_INS_SMLAWB,
+	ARM_INS_SMLAWT,
+	ARM_INS_SMLSD,
+	ARM_INS_SMLSDX,
+	ARM_INS_SMLSLD,
+	ARM_INS_SMLSLDX,
+	ARM_INS_SMMLA,
+	ARM_INS_SMMLAR,
+	ARM_INS_SMMLS,
+	ARM_INS_SMMLSR,
+	ARM_INS_SMMUL,
+	ARM_INS_SMMULR,
+	ARM_INS_SMUAD,
+	ARM_INS_SMUADX,
+	ARM_INS_SMULBB,
+	ARM_INS_SMULBT,
+	ARM_INS_SMULL,
+	ARM_INS_SMULTB,
+	ARM_INS_SMULTT,
+	ARM_INS_SMULWB,
+	ARM_INS_SMULWT,
+	ARM_INS_SMUSD,
+	ARM_INS_SMUSDX,
+	ARM_INS_SRSDA,
+	ARM_INS_SRSDB,
+	ARM_INS_SRSIA,
+	ARM_INS_SRSIB,
+	ARM_INS_SSAT,
+	ARM_INS_SSAT16,
+	ARM_INS_SSAX,
+	ARM_INS_SSUB16,
+	ARM_INS_SSUB8,
+	ARM_INS_STC,
+	ARM_INS_STC2,
+	ARM_INS_STC2L,
+	ARM_INS_STCL,
+	ARM_INS_STL,
+	ARM_INS_STLB,
+	ARM_INS_STLEX,
+	ARM_INS_STLEXB,
+	ARM_INS_STLEXD,
+	ARM_INS_STLEXH,
+	ARM_INS_STLH,
+	ARM_INS_STM,
+	ARM_INS_STMDA,
+	ARM_INS_STMDB,
+	ARM_INS_STMIB,
+	ARM_INS_STR,
+	ARM_INS_STRB,
+	ARM_INS_STRBT,
+	ARM_INS_STRD,
+	ARM_INS_STREX,
+	ARM_INS_STREXB,
+	ARM_INS_STREXD,
+	ARM_INS_STREXH,
+	ARM_INS_STRH,
+	ARM_INS_STRHT,
+	ARM_INS_STRT,
+	ARM_INS_SUB,
+	ARM_INS_SUBS,
+	ARM_INS_SUBW,
+	ARM_INS_SVC,
+	ARM_INS_SWP,
+	ARM_INS_SWPB,
+	ARM_INS_SXTAB,
+	ARM_INS_SXTAB16,
+	ARM_INS_SXTAH,
+	ARM_INS_SXTB,
+	ARM_INS_SXTB16,
+	ARM_INS_SXTH,
+	ARM_INS_TBB,
+	ARM_INS_TBH,
+	ARM_INS_TEQ,
+	ARM_INS_TRAP,
+	ARM_INS_TSB,
+	ARM_INS_TST,
+	ARM_INS_TT,
+	ARM_INS_TTA,
+	ARM_INS_TTAT,
+	ARM_INS_TTT,
+	ARM_INS_UADD16,
+	ARM_INS_UADD8,
+	ARM_INS_UASX,
+	ARM_INS_UBFX,
+	ARM_INS_UDF,
+	ARM_INS_UDIV,
+	ARM_INS_UHADD16,
+	ARM_INS_UHADD8,
+	ARM_INS_UHASX,
+	ARM_INS_UHSAX,
+	ARM_INS_UHSUB16,
+	ARM_INS_UHSUB8,
+	ARM_INS_UMAAL,
+	ARM_INS_UMLAL,
+	ARM_INS_UMULL,
+	ARM_INS_UQADD16,
+	ARM_INS_UQADD8,
+	ARM_INS_UQASX,
+	ARM_INS_UQSAX,
+	ARM_INS_UQSUB16,
+	ARM_INS_UQSUB8,
+	ARM_INS_USAD8,
+	ARM_INS_USADA8,
+	ARM_INS_USAT,
+	ARM_INS_USAT16,
+	ARM_INS_USAX,
+	ARM_INS_USUB16,
+	ARM_INS_USUB8,
+	ARM_INS_UXTAB,
+	ARM_INS_UXTAB16,
+	ARM_INS_UXTAH,
+	ARM_INS_UXTB,
+	ARM_INS_UXTB16,
+	ARM_INS_UXTH,
+	ARM_INS_VABA,
+	ARM_INS_VABAL,
+	ARM_INS_VABD,
+	ARM_INS_VABDL,
+	ARM_INS_VABS,
+	ARM_INS_VACGE,
+	ARM_INS_VACGT,
+	ARM_INS_VACLE,
+	ARM_INS_VACLT,
+	ARM_INS_VADD,
+	ARM_INS_VADDHN,
+	ARM_INS_VADDL,
+	ARM_INS_VADDW,
+	ARM_INS_VAND,
+	ARM_INS_VBIC,
+	ARM_INS_VBIF,
+	ARM_INS_VBIT,
+	ARM_INS_VBSL,
+	ARM_INS_VCADD,
+	ARM_INS_VCEQ,
+	ARM_INS_VCGE,
+	ARM_INS_VCGT,
+	ARM_INS_VCLE,
+	ARM_INS_VCLS,
+	ARM_INS_VCLT,
+	ARM_INS_VCLZ,
+	ARM_INS_VCMLA,
+	ARM_INS_VCMP,
+	ARM_INS_VCMPE,
+	ARM_INS_VCNT,
+	ARM_INS_VCVT,
+	ARM_INS_VCVTA,
+	ARM_INS_VCVTB,
+	ARM_INS_VCVTM,
+	ARM_INS_VCVTN,
+	ARM_INS_VCVTP,
+	ARM_INS_VCVTR,
+	ARM_INS_VCVTT,
+	ARM_INS_VDIV,
+	ARM_INS_VDUP,
+	ARM_INS_VEOR,
+	ARM_INS_VEXT,
+	ARM_INS_VFMA,
+	ARM_INS_VFMS,
+	ARM_INS_VFNMA,
+	ARM_INS_VFNMS,
+	ARM_INS_VHADD,
+	ARM_INS_VHSUB,
+	ARM_INS_VINS,
+	ARM_INS_VJCVT,
+	ARM_INS_VLD1,
+	ARM_INS_VLD2,
+	ARM_INS_VLD3,
+	ARM_INS_VLD4,
+	ARM_INS_VLDMDB,
+	ARM_INS_VLDMIA,
+	ARM_INS_VLDR,
+	ARM_INS_VLLDM,
+	ARM_INS_VLSTM,
+	ARM_INS_VMAX,
+	ARM_INS_VMAXNM,
+	ARM_INS_VMIN,
+	ARM_INS_VMINNM,
+	ARM_INS_VMLA,
+	ARM_INS_VMLAL,
+	ARM_INS_VMLS,
+	ARM_INS_VMLSL,
+	ARM_INS_VMOV,
+	ARM_INS_VMOVL,
+	ARM_INS_VMOVN,
+	ARM_INS_VMOVX,
+	ARM_INS_VMRS,
+	ARM_INS_VMSR,
+	ARM_INS_VMUL,
+	ARM_INS_VMULL,
+	ARM_INS_VMVN,
+	ARM_INS_VNEG,
+	ARM_INS_VNMLA,
+	ARM_INS_VNMLS,
+	ARM_INS_VNMUL,
+	ARM_INS_VORN,
+	ARM_INS_VORR,
+	ARM_INS_VPADAL,
+	ARM_INS_VPADD,
+	ARM_INS_VPADDL,
+	ARM_INS_VPMAX,
+	ARM_INS_VPMIN,
+	ARM_INS_VPOP,
+	ARM_INS_VPUSH,
+	ARM_INS_VQABS,
+	ARM_INS_VQADD,
+	ARM_INS_VQDMLAL,
+	ARM_INS_VQDMLSL,
+	ARM_INS_VQDMULH,
+	ARM_INS_VQDMULL,
+	ARM_INS_VQMOVN,
+	ARM_INS_VQMOVUN,
+	ARM_INS_VQNEG,
+	ARM_INS_VQRDMLAH,
+	ARM_INS_VQRDMLSH,
+	ARM_INS_VQRDMULH,
+	ARM_INS_VQRSHL,
+	ARM_INS_VQRSHRN,
+	ARM_INS_VQRSHRUN,
+	ARM_INS_VQSHL,
+	ARM_INS_VQSHLU,
+	ARM_INS_VQSHRN,
+	ARM_INS_VQSHRUN,
+	ARM_INS_VQSUB,
+	ARM_INS_VRADDHN,
+	ARM_INS_VRECPE,
+	ARM_INS_VRECPS,
+	ARM_INS_VREV16,
+	ARM_INS_VREV32,
+	ARM_INS_VREV64,
+	ARM_INS_VRHADD,
+	ARM_INS_VRINTA,
+	ARM_INS_VRINTM,
+	ARM_INS_VRINTN,
+	ARM_INS_VRINTP,
+	ARM_INS_VRINTR,
+	ARM_INS_VRINTX,
+	ARM_INS_VRINTZ,
+	ARM_INS_VRSHL,
+	ARM_INS_VRSHR,
+	ARM_INS_VRSHRN,
+	ARM_INS_VRSQRTE,
+	ARM_INS_VRSQRTS,
+	ARM_INS_VRSRA,
+	ARM_INS_VRSUBHN,
+	ARM_INS_VSDOT,
+	ARM_INS_VSELEQ,
+	ARM_INS_VSELGE,
+	ARM_INS_VSELGT,
+	ARM_INS_VSELVS,
+	ARM_INS_VSHL,
+	ARM_INS_VSHLL,
+	ARM_INS_VSHR,
+	ARM_INS_VSHRN,
+	ARM_INS_VSLI,
+	ARM_INS_VSQRT,
+	ARM_INS_VSRA,
+	ARM_INS_VSRI,
+	ARM_INS_VST1,
+	ARM_INS_VST2,
+	ARM_INS_VST3,
+	ARM_INS_VST4,
+	ARM_INS_VSTMDB,
+	ARM_INS_VSTMIA,
+	ARM_INS_VSTR,
+	ARM_INS_VSUB,
+	ARM_INS_VSUBHN,
+	ARM_INS_VSUBL,
+	ARM_INS_VSUBW,
+	ARM_INS_VSWP,
+	ARM_INS_VTBL,
+	ARM_INS_VTBX,
+	ARM_INS_VTRN,
+	ARM_INS_VTST,
+	ARM_INS_VUDOT,
+	ARM_INS_VUZP,
+	ARM_INS_VZIP,
+	ARM_INS_WFE,
+	ARM_INS_WFI,
+	ARM_INS_YIELD,
+
+	ARM_INS_ENDING,	// <-- mark the end of the list of instructions
+} arm_insn;
+
+/// Group of ARM instructions
+typedef enum arm_insn_group {
+	ARM_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+	// Generic groups
+	// all jump instructions (conditional+direct+indirect jumps)
+	ARM_GRP_JUMP,	///< = CS_GRP_JUMP
+	ARM_GRP_CALL,	///< = CS_GRP_CALL
+	ARM_GRP_INT = 4, ///< = CS_GRP_INT
+	ARM_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE
+	ARM_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
+
+	// Architecture-specific groups
+	ARM_GRP_CRYPTO = 128,
+	ARM_GRP_DATABARRIER,
+	ARM_GRP_DIVIDE,
+	ARM_GRP_FPARMV8,
+	ARM_GRP_MULTPRO,
+	ARM_GRP_NEON,
+	ARM_GRP_T2EXTRACTPACK,
+	ARM_GRP_THUMB2DSP,
+	ARM_GRP_TRUSTZONE,
+	ARM_GRP_V4T,
+	ARM_GRP_V5T,
+	ARM_GRP_V5TE,
+	ARM_GRP_V6,
+	ARM_GRP_V6T2,
+	ARM_GRP_V7,
+	ARM_GRP_V8,
+	ARM_GRP_VFP2,
+	ARM_GRP_VFP3,
+	ARM_GRP_VFP4,
+	ARM_GRP_ARM,
+	ARM_GRP_MCLASS,
+	ARM_GRP_NOTMCLASS,
+	ARM_GRP_THUMB,
+	ARM_GRP_THUMB1ONLY,
+	ARM_GRP_THUMB2,
+	ARM_GRP_PREV8,
+	ARM_GRP_FPVMLX,
+	ARM_GRP_MULOPS,
+	ARM_GRP_CRC,
+	ARM_GRP_DPVFP,
+	ARM_GRP_V6M,
+	ARM_GRP_VIRTUALIZATION,
+
+	ARM_GRP_ENDING,
+} arm_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

.tools/python-revlibs/capstone/include/capstone/bpf.h

@@ -0,0 +1,209 @@
+/* Capstone Disassembly Engine */
+/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
+
+#ifndef CAPSTONE_BPF_H
+#define CAPSTONE_BPF_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// Operand type for instruction's operands
+typedef enum bpf_op_type {
+	BPF_OP_INVALID = 0,
+
+	BPF_OP_REG,
+	BPF_OP_IMM,
+	BPF_OP_OFF,
+	BPF_OP_MEM,
+	BPF_OP_MMEM,	///< M[k] in cBPF
+	BPF_OP_MSH,	///< corresponds to cBPF's BPF_MSH mode
+	BPF_OP_EXT,	///< cBPF's extension (not eBPF)
+} bpf_op_type;
+
+/// BPF registers
+typedef enum bpf_reg {
+	BPF_REG_INVALID = 0,
+
+	///< cBPF
+	BPF_REG_A,
+	BPF_REG_X,
+
+	///< eBPF
+	BPF_REG_R0,
+	BPF_REG_R1,
+	BPF_REG_R2,
+	BPF_REG_R3,
+	BPF_REG_R4,
+	BPF_REG_R5,
+	BPF_REG_R6,
+	BPF_REG_R7,
+	BPF_REG_R8,
+	BPF_REG_R9,
+	BPF_REG_R10,
+
+	BPF_REG_ENDING,
+} bpf_reg;
+
+/// Instruction's operand referring to memory
+/// This is associated with BPF_OP_MEM operand type above
+typedef struct bpf_op_mem {
+	bpf_reg base;	///< base register
+	uint32_t disp;	///< offset value
+} bpf_op_mem;
+
+typedef enum bpf_ext_type {
+	BPF_EXT_INVALID = 0,
+
+	BPF_EXT_LEN,
+} bpf_ext_type;
+
+/// Instruction operand
+typedef struct cs_bpf_op {
+	bpf_op_type type;
+	union {
+		uint8_t reg;	///< register value for REG operand
+		uint64_t imm;	///< immediate value IMM operand
+		uint32_t off;	///< offset value, used in jump & call
+		bpf_op_mem mem;	///< base/disp value for MEM operand
+		/* cBPF only */
+		uint32_t mmem;	///< M[k] in cBPF
+		uint32_t msh;	///< corresponds to cBPF's BPF_MSH mode
+		uint32_t ext;	///< cBPF's extension (not eBPF)
+	};
+
+	/// How is this operand accessed? (READ, WRITE or READ|WRITE)
+	/// This field is combined of cs_ac_type.
+	/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
+	uint8_t access;
+} cs_bpf_op;
+
+/// Instruction structure
+typedef struct cs_bpf {
+	uint8_t op_count;
+	cs_bpf_op operands[4];
+} cs_bpf;
+
+/// BPF instruction
+typedef enum bpf_insn {
+	BPF_INS_INVALID = 0,
+
+	///< ALU
+	BPF_INS_ADD,
+	BPF_INS_SUB,
+	BPF_INS_MUL,
+	BPF_INS_DIV,
+	BPF_INS_OR,
+	BPF_INS_AND,
+	BPF_INS_LSH,
+	BPF_INS_RSH,
+	BPF_INS_NEG,
+	BPF_INS_MOD,
+	BPF_INS_XOR,
+	BPF_INS_MOV,	///< eBPF only
+	BPF_INS_ARSH,	///< eBPF only
+
+	///< ALU64, eBPF only
+	BPF_INS_ADD64,
+	BPF_INS_SUB64,
+	BPF_INS_MUL64,
+	BPF_INS_DIV64,
+	BPF_INS_OR64,
+	BPF_INS_AND64,
+	BPF_INS_LSH64,
+	BPF_INS_RSH64,
+	BPF_INS_NEG64,
+	BPF_INS_MOD64,
+	BPF_INS_XOR64,
+	BPF_INS_MOV64,
+	BPF_INS_ARSH64,
+
+	///< Byteswap, eBPF only
+	BPF_INS_LE16,
+	BPF_INS_LE32,
+	BPF_INS_LE64,
+	BPF_INS_BE16,
+	BPF_INS_BE32,
+	BPF_INS_BE64,
+
+	///< Load
+	BPF_INS_LDW,	///< eBPF only
+	BPF_INS_LDH,
+	BPF_INS_LDB,
+	BPF_INS_LDDW,	///< eBPF only: load 64-bit imm
+	BPF_INS_LDXW,	///< eBPF only
+	BPF_INS_LDXH,	///< eBPF only
+	BPF_INS_LDXB,	///< eBPF only
+	BPF_INS_LDXDW,	///< eBPF only
+
+	///< Store
+	BPF_INS_STW,	///< eBPF only
+	BPF_INS_STH,	///< eBPF only
+	BPF_INS_STB,	///< eBPF only
+	BPF_INS_STDW,	///< eBPF only
+	BPF_INS_STXW,	///< eBPF only
+	BPF_INS_STXH,	///< eBPF only
+	BPF_INS_STXB,	///< eBPF only
+	BPF_INS_STXDW,	///< eBPF only
+	BPF_INS_XADDW,	///< eBPF only
+	BPF_INS_XADDDW,	///< eBPF only
+
+	///< Jump
+	BPF_INS_JMP,
+	BPF_INS_JEQ,
+	BPF_INS_JGT,
+	BPF_INS_JGE,
+	BPF_INS_JSET,
+	BPF_INS_JNE,	///< eBPF only
+	BPF_INS_JSGT,	///< eBPF only
+	BPF_INS_JSGE,	///< eBPF only
+	BPF_INS_CALL,	///< eBPF only
+	BPF_INS_CALLX,	///< eBPF only
+	BPF_INS_EXIT,	///< eBPF only
+	BPF_INS_JLT,	///< eBPF only
+	BPF_INS_JLE,	///< eBPF only
+	BPF_INS_JSLT,	///< eBPF only
+	BPF_INS_JSLE,	///< eBPF only
+
+	///< Return, cBPF only
+	BPF_INS_RET,
+
+	///< Misc, cBPF only
+	BPF_INS_TAX,
+	BPF_INS_TXA,
+
+	BPF_INS_ENDING,
+
+	// alias instructions
+	BPF_INS_LD = BPF_INS_LDW,	///< cBPF only
+	BPF_INS_LDX = BPF_INS_LDXW,	///< cBPF only
+	BPF_INS_ST = BPF_INS_STW,	///< cBPF only
+	BPF_INS_STX = BPF_INS_STXW,	///< cBPF only
+} bpf_insn;
+
+/// Group of BPF instructions
+typedef enum bpf_insn_group {
+	BPF_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+	BPF_GRP_LOAD,
+	BPF_GRP_STORE,
+	BPF_GRP_ALU,
+	BPF_GRP_JUMP,
+	BPF_GRP_CALL, ///< eBPF only
+	BPF_GRP_RETURN,
+	BPF_GRP_MISC, ///< cBPF only
+
+	BPF_GRP_ENDING,
+} bpf_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

.tools/python-revlibs/capstone/include/capstone/capstone.h

@@ -0,0 +1,890 @@
+#ifndef CAPSTONE_ENGINE_H
+#define CAPSTONE_ENGINE_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2016 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdarg.h>
+
+#if defined(CAPSTONE_HAS_OSXKERNEL)
+#include <libkern/libkern.h>
+#else
+#include <stdlib.h>
+#include <stdio.h>
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#pragma warning(disable:4100)
+#define CAPSTONE_API __cdecl
+#ifdef CAPSTONE_SHARED
+#define CAPSTONE_EXPORT __declspec(dllexport)
+#else    // defined(CAPSTONE_STATIC)
+#define CAPSTONE_EXPORT
+#endif
+#else
+#define CAPSTONE_API
+#if (defined(__GNUC__) || defined(__IBMC__)) && !defined(CAPSTONE_STATIC)
+#define CAPSTONE_EXPORT __attribute__((visibility("default")))
+#else    // defined(CAPSTONE_STATIC)
+#define CAPSTONE_EXPORT
+#endif
+#endif
+
+#if (defined(__GNUC__) || defined(__IBMC__))
+#define CAPSTONE_DEPRECATED __attribute__((deprecated))
+#elif defined(_MSC_VER)
+#define CAPSTONE_DEPRECATED __declspec(deprecated)
+#else
+#pragma message("WARNING: You need to implement CAPSTONE_DEPRECATED for this compiler")
+#define CAPSTONE_DEPRECATED
+#endif
+
+// Capstone API version
+#define CS_API_MAJOR 5
+#define CS_API_MINOR 0
+
+// Version for bleeding edge code of the Github's "next" branch.
+// Use this if you want the absolutely latest development code.
+// This version number will be bumped up whenever we have a new major change.
+#define CS_NEXT_VERSION 5
+
+// Capstone package version
+#define CS_VERSION_MAJOR CS_API_MAJOR
+#define CS_VERSION_MINOR CS_API_MINOR
+#define CS_VERSION_EXTRA 9
+
+// Pre-release identifier.
+// A stable release.
+#define CS_VERSION_STABLE 0xffff
+
+// The postfix version: Alpha1, Alpha2, ..., Beta1, ...
+#define CS_VERSION_ALPHA 0xa000
+#define CS_VERSION_ALPHA9 (CS_VERSION_ALPHA | 9)
+
+#define CS_VERSION_BETA 0xb000
+#define CS_VERSION_BETA1 (CS_VERSION_BETA | 1)
+
+// The identifier of a pre-release (Alpha, Beta, ...).
+// It is set to CS_VERSION_STABLE, if this code is part of a stable release.
+#define CS_VERSION_PRE_RELEASE CS_VERSION_STABLE
+
+/// Macro for meta programming.
+/// Meant for projects using Capstone and need to support multiple
+/// versions of it.
+/// These macros replace several instances of the old "ARM64" with
+/// the new "AArch64" name depending on the CS version.
+#if CS_NEXT_VERSION < 6
+#define CS_AARCH64(x) ARM64##x
+#else
+#define CS_AARCH64(x) AArch64##x
+#endif
+
+#if CS_NEXT_VERSION < 6
+#define CS_AARCH64pre(x) x##ARM64
+#else
+#define CS_AARCH64pre(x) x##AARCH64
+#endif
+
+#if CS_NEXT_VERSION < 6
+#define CS_AARCH64CC(x) ARM64_CC##x
+#else
+#define CS_AARCH64CC(x) AArch64CC##x
+#endif
+
+#if CS_NEXT_VERSION < 6
+#define CS_AARCH64_VL_(x) ARM64_VAS_##x
+#else
+#define CS_AARCH64_VL_(x) AArch64Layout_VL_##x
+#endif
+
+#if CS_NEXT_VERSION < 6
+#define CS_aarch64_ arm64
+#else
+#define CS_aarch64_ aarch64
+#endif
+
+#if CS_NEXT_VERSION < 6
+#define CS_aarch64(x) arm64##x
+#else
+#define CS_aarch64(x) aarch64##x
+#endif
+
+#if CS_NEXT_VERSION < 6
+#define CS_aarch64_op() cs_arm64_op
+#define CS_aarch64_reg() arm64_reg
+#define CS_aarch64_cc() arm64_cc
+#define CS_cs_aarch64() cs_arm64
+#define CS_aarch64_extender() arm64_extender
+#define CS_aarch64_shifter() arm64_shifter
+#define CS_aarch64_vas() arm64_vas
+#else
+#define CS_aarch64_op() cs_aarch64_op
+#define CS_aarch64_reg() aarch64_reg
+#define CS_aarch64_cc() AArch64CC_CondCode
+#define CS_cs_aarch64() cs_aarch64
+#define CS_aarch64_extender() aarch64_extender
+#define CS_aarch64_shifter() aarch64_shifter
+#define CS_aarch64_vas() AArch64Layout_VectorLayout
+#endif
+
+/// Macro to create combined version which can be compared to
+/// result of cs_version() API.
+#define CS_MAKE_VERSION(major, minor) ((major << 8) + minor)
+
+/// Maximum size of an instruction mnemonic string.
+#define CS_MNEMONIC_SIZE 32
+
+// Handle using with all API
+typedef size_t csh;
+
+/// Architecture type
+typedef enum cs_arch {
+	CS_ARCH_ARM = 0,	///< ARM architecture (including Thumb, Thumb-2)
+	CS_ARCH_ARM64,		///< ARM-64, also called AArch64
+	CS_ARCH_MIPS,		///< Mips architecture
+	CS_ARCH_X86,		///< X86 architecture (including x86 & x86-64)
+	CS_ARCH_PPC,		///< PowerPC architecture
+	CS_ARCH_SPARC,		///< Sparc architecture
+	CS_ARCH_SYSZ,		///< SystemZ architecture
+	CS_ARCH_XCORE,		///< XCore architecture
+	CS_ARCH_M68K,		///< 68K architecture
+	CS_ARCH_TMS320C64X,	///< TMS320C64x architecture
+	CS_ARCH_M680X,		///< 680X architecture
+	CS_ARCH_EVM,		///< Ethereum architecture
+	CS_ARCH_MOS65XX,	///< MOS65XX architecture (including MOS6502)
+	CS_ARCH_WASM,		///< WebAssembly architecture
+	CS_ARCH_BPF,		///< Berkeley Packet Filter architecture (including eBPF)
+	CS_ARCH_RISCV,          ///< RISCV architecture
+	CS_ARCH_SH,             ///< SH architecture
+	CS_ARCH_TRICORE,	///< TriCore architecture
+	CS_ARCH_MAX,
+	CS_ARCH_ALL = 0xFFFF, // All architectures - for cs_support()
+} cs_arch;
+
+// Support value to verify diet mode of the engine.
+// If cs_support(CS_SUPPORT_DIET) return True, the engine was compiled
+// in diet mode.
+#define CS_SUPPORT_DIET (CS_ARCH_ALL + 1)
+
+// Support value to verify X86 reduce mode of the engine.
+// If cs_support(CS_SUPPORT_X86_REDUCE) return True, the engine was compiled
+// in X86 reduce mode.
+#define CS_SUPPORT_X86_REDUCE (CS_ARCH_ALL + 2)
+
+/// Mode type
+typedef enum cs_mode {
+	CS_MODE_LITTLE_ENDIAN = 0,	///< little-endian mode (default mode)
+	CS_MODE_ARM = 0,	///< 32-bit ARM
+	CS_MODE_16 = 1 << 1,	///< 16-bit mode (X86)
+	CS_MODE_32 = 1 << 2,	///< 32-bit mode (X86)
+	CS_MODE_64 = 1 << 3,	///< 64-bit mode (X86, PPC)
+	CS_MODE_THUMB = 1 << 4,	///< ARM's Thumb mode, including Thumb-2
+	CS_MODE_MCLASS = 1 << 5,	///< ARM's Cortex-M series
+	CS_MODE_V8 = 1 << 6,	///< ARMv8 A32 encodings for ARM
+	CS_MODE_MICRO = 1 << 4, ///< MicroMips mode (MIPS)
+	CS_MODE_MIPS3 = 1 << 5, ///< Mips III ISA
+	CS_MODE_MIPS32R6 = 1 << 6, ///< Mips32r6 ISA
+	CS_MODE_MIPS2 = 1 << 7, ///< Mips II ISA
+	CS_MODE_V9 = 1 << 4, ///< SparcV9 mode (Sparc)
+	CS_MODE_QPX = 1 << 4, ///< Quad Processing eXtensions mode (PPC)
+	CS_MODE_SPE = 1 << 5, ///< Signal Processing Engine mode (PPC)
+	CS_MODE_BOOKE = 1 << 6, ///< Book-E mode (PPC)
+	CS_MODE_PS = 1 << 7, ///< Paired-singles mode (PPC)
+	CS_MODE_M68K_000 = 1 << 1, ///< M68K 68000 mode
+	CS_MODE_M68K_010 = 1 << 2, ///< M68K 68010 mode
+	CS_MODE_M68K_020 = 1 << 3, ///< M68K 68020 mode
+	CS_MODE_M68K_030 = 1 << 4, ///< M68K 68030 mode
+	CS_MODE_M68K_040 = 1 << 5, ///< M68K 68040 mode
+	CS_MODE_M68K_060 = 1 << 6, ///< M68K 68060 mode
+	CS_MODE_BIG_ENDIAN = 1U << 31,	///< big-endian mode
+	CS_MODE_MIPS32 = CS_MODE_32,	///< Mips32 ISA (Mips)
+	CS_MODE_MIPS64 = CS_MODE_64,	///< Mips64 ISA (Mips)
+	CS_MODE_M680X_6301 = 1 << 1, ///< M680X Hitachi 6301,6303 mode
+	CS_MODE_M680X_6309 = 1 << 2, ///< M680X Hitachi 6309 mode
+	CS_MODE_M680X_6800 = 1 << 3, ///< M680X Motorola 6800,6802 mode
+	CS_MODE_M680X_6801 = 1 << 4, ///< M680X Motorola 6801,6803 mode
+	CS_MODE_M680X_6805 = 1 << 5, ///< M680X Motorola/Freescale 6805 mode
+	CS_MODE_M680X_6808 = 1 << 6, ///< M680X Motorola/Freescale/NXP 68HC08 mode
+	CS_MODE_M680X_6809 = 1 << 7, ///< M680X Motorola 6809 mode
+	CS_MODE_M680X_6811 = 1 << 8, ///< M680X Motorola/Freescale/NXP 68HC11 mode
+	CS_MODE_M680X_CPU12 = 1 << 9, ///< M680X Motorola/Freescale/NXP CPU12
+					///< used on M68HC12/HCS12
+	CS_MODE_M680X_HCS08 = 1 << 10, ///< M680X Freescale/NXP HCS08 mode
+	CS_MODE_BPF_CLASSIC = 0,	///< Classic BPF mode (default)
+	CS_MODE_BPF_EXTENDED = 1 << 0,	///< Extended BPF mode
+	CS_MODE_RISCV32  = 1 << 0,        ///< RISCV RV32G
+	CS_MODE_RISCV64  = 1 << 1,        ///< RISCV RV64G
+	CS_MODE_RISCVC   = 1 << 2,        ///< RISCV compressed instructure mode
+	CS_MODE_MOS65XX_6502 = 1 << 1, ///< MOS65XXX MOS 6502
+	CS_MODE_MOS65XX_65C02 = 1 << 2, ///< MOS65XXX WDC 65c02
+	CS_MODE_MOS65XX_W65C02 = 1 << 3, ///< MOS65XXX WDC W65c02
+	CS_MODE_MOS65XX_65816 = 1 << 4, ///< MOS65XXX WDC 65816, 8-bit m/x
+	CS_MODE_MOS65XX_65816_LONG_M = (1 << 5), ///< MOS65XXX WDC 65816, 16-bit m, 8-bit x
+	CS_MODE_MOS65XX_65816_LONG_X = (1 << 6), ///< MOS65XXX WDC 65816, 8-bit m, 16-bit x
+	CS_MODE_MOS65XX_65816_LONG_MX = CS_MODE_MOS65XX_65816_LONG_M | CS_MODE_MOS65XX_65816_LONG_X,
+	CS_MODE_SH2 = 1 << 1,    ///< SH2
+	CS_MODE_SH2A = 1 << 2,   ///< SH2A
+	CS_MODE_SH3 = 1 << 3,    ///< SH3
+	CS_MODE_SH4 = 1 << 4,    ///< SH4
+	CS_MODE_SH4A = 1 << 5,   ///< SH4A
+	CS_MODE_SHFPU = 1 << 6,  ///< w/ FPU
+	CS_MODE_SHDSP = 1 << 7,  ///< w/ DSP
+	CS_MODE_TRICORE_110 = 1 << 1, ///< Tricore 1.1
+	CS_MODE_TRICORE_120 = 1 << 2, ///< Tricore 1.2
+	CS_MODE_TRICORE_130 = 1 << 3, ///< Tricore 1.3
+	CS_MODE_TRICORE_131 = 1 << 4, ///< Tricore 1.3.1
+	CS_MODE_TRICORE_160 = 1 << 5, ///< Tricore 1.6
+	CS_MODE_TRICORE_161 = 1 << 6, ///< Tricore 1.6.1
+	CS_MODE_TRICORE_162 = 1 << 7, ///< Tricore 1.6.2
+} cs_mode;
+
+typedef void* (CAPSTONE_API *cs_malloc_t)(size_t size);
+typedef void* (CAPSTONE_API *cs_calloc_t)(size_t nmemb, size_t size);
+typedef void* (CAPSTONE_API *cs_realloc_t)(void *ptr, size_t size);
+typedef void (CAPSTONE_API *cs_free_t)(void *ptr);
+typedef int (CAPSTONE_API *cs_vsnprintf_t)(char *str, size_t size, const char *format, va_list ap);
+
+
+/// User-defined dynamic memory related functions: malloc/calloc/realloc/free/vsnprintf()
+/// By default, Capstone uses system's malloc(), calloc(), realloc(), free() & vsnprintf().
+typedef struct cs_opt_mem {
+	cs_malloc_t malloc;
+	cs_calloc_t calloc;
+	cs_realloc_t realloc;
+	cs_free_t free;
+	cs_vsnprintf_t vsnprintf;
+} cs_opt_mem;
+
+/// Customize mnemonic for instructions with alternative name.
+/// To reset existing customized instruction to its default mnemonic,
+/// call cs_option(CS_OPT_MNEMONIC) again with the same @id and NULL value
+/// for @mnemonic.
+typedef struct cs_opt_mnem {
+	/// ID of instruction to be customized.
+	unsigned int id;
+	/// Customized instruction mnemonic.
+	const char *mnemonic;
+} cs_opt_mnem;
+
+/// Runtime option for the disassembled engine
+typedef enum cs_opt_type {
+	CS_OPT_INVALID = 0, ///< No option specified
+	CS_OPT_SYNTAX,	    ///< Assembly output syntax
+	CS_OPT_DETAIL,	    ///< Break down instruction structure into details
+	CS_OPT_MODE,	    ///< Change engine's mode at run-time
+	CS_OPT_MEM,	    ///< User-defined dynamic memory related functions
+	CS_OPT_SKIPDATA, ///< Skip data when disassembling. Then engine is in SKIPDATA mode.
+	CS_OPT_SKIPDATA_SETUP, ///< Setup user-defined function for SKIPDATA option
+	CS_OPT_MNEMONIC,       ///< Customize instruction mnemonic
+	CS_OPT_UNSIGNED,       ///< print immediate operands in unsigned form
+	CS_OPT_NO_BRANCH_OFFSET, ///< ARM, prints branch immediates without offset.
+} cs_opt_type;
+
+/// Runtime option value (associated with option type above)
+typedef enum cs_opt_value {
+	CS_OPT_OFF = 0,  ///< Turn OFF an option - default for CS_OPT_DETAIL, CS_OPT_SKIPDATA, CS_OPT_UNSIGNED.
+	CS_OPT_ON = 3, ///< Turn ON an option (CS_OPT_DETAIL, CS_OPT_SKIPDATA).
+	CS_OPT_SYNTAX_DEFAULT = 0, ///< Default asm syntax (CS_OPT_SYNTAX).
+	CS_OPT_SYNTAX_INTEL, ///< X86 Intel asm syntax - default on X86 (CS_OPT_SYNTAX).
+	CS_OPT_SYNTAX_ATT,   ///< X86 ATT asm syntax (CS_OPT_SYNTAX).
+	CS_OPT_SYNTAX_NOREGNAME, ///< Prints register name with only number (CS_OPT_SYNTAX)
+	CS_OPT_SYNTAX_MASM, ///< X86 Intel Masm syntax (CS_OPT_SYNTAX).
+	CS_OPT_SYNTAX_MOTOROLA, ///< MOS65XX use $ as hex prefix
+} cs_opt_value;
+
+/// Common instruction operand types - to be consistent across all architectures.
+typedef enum cs_op_type {
+	CS_OP_INVALID = 0, ///< uninitialized/invalid operand.
+	CS_OP_REG,	   ///< Register operand.
+	CS_OP_IMM,	   ///< Immediate operand.
+	CS_OP_MEM,	   ///< Memory operand. Can be ORed with another operand type.
+	CS_OP_FP,	   ///< Floating-Point operand.
+} cs_op_type;
+
+/// Common instruction operand access types - to be consistent across all architectures.
+/// It is possible to combine access types, for example: CS_AC_READ | CS_AC_WRITE
+typedef enum cs_ac_type {
+	CS_AC_INVALID = 0,        ///< Uninitialized/invalid access type.
+	CS_AC_READ    = 1 << 0,   ///< Operand read from memory or register.
+	CS_AC_WRITE   = 1 << 1,   ///< Operand write to memory or register.
+} cs_ac_type;
+
+/// Common instruction groups - to be consistent across all architectures.
+typedef enum cs_group_type {
+	CS_GRP_INVALID = 0,  ///< uninitialized/invalid group.
+	CS_GRP_JUMP,    ///< all jump instructions (conditional+direct+indirect jumps)
+	CS_GRP_CALL,    ///< all call instructions
+	CS_GRP_RET,     ///< all return instructions
+	CS_GRP_INT,     ///< all interrupt instructions (int+syscall)
+	CS_GRP_IRET,    ///< all interrupt return instructions
+	CS_GRP_PRIVILEGE,    ///< all privileged instructions
+	CS_GRP_BRANCH_RELATIVE, ///< all relative branching instructions
+} cs_group_type;
+
+/**
+ User-defined callback function for SKIPDATA option.
+ See tests/test_skipdata.c for sample code demonstrating this API.
+
+ @code: the input buffer containing code to be disassembled.
+        This is the same buffer passed to cs_disasm().
+ @code_size: size (in bytes) of the above @code buffer.
+ @offset: the position of the currently-examining byte in the input
+      buffer @code mentioned above.
+ @user_data: user-data passed to cs_option() via @user_data field in
+      cs_opt_skipdata struct below.
+
+ @return: return number of bytes to skip, or 0 to immediately stop disassembling.
+*/
+typedef size_t (CAPSTONE_API *cs_skipdata_cb_t)(const uint8_t *code, size_t code_size, size_t offset, void *user_data);
+
+/// User-customized setup for SKIPDATA option
+typedef struct cs_opt_skipdata {
+	/// Capstone considers data to skip as special "instructions".
+	/// User can specify the string for this instruction's "mnemonic" here.
+	/// By default (if @mnemonic is NULL), Capstone use ".byte".
+	const char *mnemonic;
+
+	/// User-defined callback function to be called when Capstone hits data.
+	/// If the returned value from this callback is positive (>0), Capstone
+	/// will skip exactly that number of bytes & continue. Otherwise, if
+	/// the callback returns 0, Capstone stops disassembling and returns
+	/// immediately from cs_disasm()
+	/// NOTE: if this callback pointer is NULL, Capstone would skip a number
+	/// of bytes depending on architectures, as following:
+	/// Arm:     2 bytes (Thumb mode) or 4 bytes.
+	/// Arm64:   4 bytes.
+	/// Mips:    4 bytes.
+	/// M680x:   1 byte.
+	/// PowerPC: 4 bytes.
+	/// Sparc:   4 bytes.
+	/// SystemZ: 2 bytes.
+	/// X86:     1 bytes.
+	/// XCore:   2 bytes.
+	/// EVM:     1 bytes.
+	/// RISCV:   4 bytes.
+	/// WASM:    1 bytes.
+	/// MOS65XX: 1 bytes.
+	/// BPF:     8 bytes.
+	/// TriCore: 2 bytes.
+	cs_skipdata_cb_t callback; 	// default value is NULL
+
+	/// User-defined data to be passed to @callback function pointer.
+	void *user_data;
+} cs_opt_skipdata;
+
+
+#include "arm.h"
+#include "arm64.h"
+#include "m68k.h"
+#include "mips.h"
+#include "ppc.h"
+#include "sparc.h"
+#include "systemz.h"
+#include "x86.h"
+#include "xcore.h"
+#include "tms320c64x.h"
+#include "m680x.h"
+#include "evm.h"
+#include "riscv.h"
+#include "wasm.h"
+#include "mos65xx.h"
+#include "bpf.h"
+#include "sh.h"
+#include "tricore.h"
+
+#define MAX_IMPL_W_REGS 20
+#define MAX_IMPL_R_REGS 20
+#define MAX_NUM_GROUPS 8
+
+/// NOTE: All information in cs_detail is only available when CS_OPT_DETAIL = CS_OPT_ON
+/// Initialized as memset(., 0, offsetof(cs_detail, ARCH)+sizeof(cs_ARCH))
+/// by ARCH_getInstruction in arch/ARCH/ARCHDisassembler.c
+/// if cs_detail changes, in particular if a field is added after the union,
+/// then update arch/ARCH/ARCHDisassembler.c accordingly
+typedef struct cs_detail {
+	uint16_t regs_read
+		[MAX_IMPL_R_REGS]; ///< list of implicit registers read by this insn
+	uint8_t regs_read_count; ///< number of implicit registers read by this insn
+
+	uint16_t regs_write
+		[MAX_IMPL_W_REGS]; ///< list of implicit registers modified by this insn
+	uint8_t regs_write_count; ///< number of implicit registers modified by this insn
+
+	uint8_t groups[MAX_NUM_GROUPS]; ///< list of group this instruction belong to
+	uint8_t groups_count; ///< number of groups this insn belongs to
+
+	bool writeback;	      ///< Instruction has writeback operands.
+
+	/// Architecture-specific instruction info
+	union {
+		cs_x86 x86;     ///< X86 architecture, including 16-bit, 32-bit & 64-bit mode
+		cs_arm64 arm64; ///< ARM64 architecture (aka AArch64)
+		cs_arm arm;     ///< ARM architecture (including Thumb/Thumb2)
+		cs_m68k m68k;   ///< M68K architecture
+		cs_mips mips;   ///< MIPS architecture
+		cs_ppc ppc;	    ///< PowerPC architecture
+		cs_sparc sparc; ///< Sparc architecture
+		cs_sysz sysz;   ///< SystemZ architecture
+		cs_xcore xcore; ///< XCore architecture
+		cs_tms320c64x tms320c64x;  ///< TMS320C64x architecture
+		cs_m680x m680x; ///< M680X architecture
+		cs_evm evm;	    ///< Ethereum architecture
+		cs_mos65xx mos65xx;	///< MOS65XX architecture (including MOS6502)
+		cs_wasm wasm;	///< Web Assembly architecture
+		cs_bpf bpf;	///< Berkeley Packet Filter architecture (including eBPF)
+		cs_riscv riscv; ///< RISCV architecture
+		cs_sh sh;        ///< SH architecture
+		cs_tricore tricore; ///< TriCore architecture
+	};
+} cs_detail;
+
+/// Detail information of disassembled instruction
+typedef struct cs_insn {
+	/// Instruction ID (basically a numeric ID for the instruction mnemonic)
+	/// Find the instruction id in the '[ARCH]_insn' enum in the header file
+	/// of corresponding architecture, such as 'arm_insn' in arm.h for ARM,
+	/// 'x86_insn' in x86.h for X86, etc...
+	/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+	/// NOTE: in Skipdata mode, "data" instruction has 0 for this id field.
+	unsigned int id;
+
+	/// Address (EIP) of this instruction
+	/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+	uint64_t address;
+
+	/// Size of this instruction
+	/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+	uint16_t size;
+
+	/// Machine bytes of this instruction, with number of bytes indicated by @size above
+	/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+	uint8_t bytes[24];
+
+	/// Ascii text of instruction mnemonic
+	/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+	char mnemonic[CS_MNEMONIC_SIZE];
+
+	/// Ascii text of instruction operands
+	/// This information is available even when CS_OPT_DETAIL = CS_OPT_OFF
+	char op_str[160];
+
+	/// Pointer to cs_detail.
+	/// NOTE: detail pointer is only valid when both requirements below are met:
+	/// (1) CS_OP_DETAIL = CS_OPT_ON
+	/// (2) Engine is not in Skipdata mode (CS_OP_SKIPDATA option set to CS_OPT_ON)
+	///
+	/// NOTE 2: when in Skipdata mode, or when detail mode is OFF, even if this pointer
+	///     is not NULL, its content is still irrelevant.
+	cs_detail *detail;
+} cs_insn;
+
+
+/// Calculate the offset of a disassembled instruction in its buffer, given its position
+/// in its array of disassembled insn
+/// NOTE: this macro works with position (>=1), not index
+#define CS_INSN_OFFSET(insns, post) (insns[post - 1].address - insns[0].address)
+
+
+/// All type of errors encountered by Capstone API.
+/// These are values returned by cs_errno()
+typedef enum cs_err {
+	CS_ERR_OK = 0,   ///< No error: everything was fine
+	CS_ERR_MEM,      ///< Out-Of-Memory error: cs_open(), cs_disasm(), cs_disasm_iter()
+	CS_ERR_ARCH,     ///< Unsupported architecture: cs_open()
+	CS_ERR_HANDLE,   ///< Invalid handle: cs_op_count(), cs_op_index()
+	CS_ERR_CSH,      ///< Invalid csh argument: cs_close(), cs_errno(), cs_option()
+	CS_ERR_MODE,     ///< Invalid/unsupported mode: cs_open()
+	CS_ERR_OPTION,   ///< Invalid/unsupported option: cs_option()
+	CS_ERR_DETAIL,   ///< Information is unavailable because detail option is OFF
+	CS_ERR_MEMSETUP, ///< Dynamic memory management uninitialized (see CS_OPT_MEM)
+	CS_ERR_VERSION,  ///< Unsupported version (bindings)
+	CS_ERR_DIET,     ///< Access irrelevant data in "diet" engine
+	CS_ERR_SKIPDATA, ///< Access irrelevant data for "data" instruction in SKIPDATA mode
+	CS_ERR_X86_ATT,  ///< X86 AT&T syntax is unsupported (opt-out at compile time)
+	CS_ERR_X86_INTEL, ///< X86 Intel syntax is unsupported (opt-out at compile time)
+	CS_ERR_X86_MASM, ///< X86 Masm syntax is unsupported (opt-out at compile time)
+} cs_err;
+
+/**
+ Return combined API version & major and minor version numbers.
+
+ @major: major number of API version
+ @minor: minor number of API version
+
+ @return hexical number as (major << 8 | minor), which encodes both
+	 major & minor versions.
+	 NOTE: This returned value can be compared with version number made
+	 with macro CS_MAKE_VERSION
+
+ For example, second API version would return 1 in @major, and 1 in @minor
+ The return value would be 0x0101
+
+ NOTE: if you only care about returned value, but not major and minor values,
+ set both @major & @minor arguments to NULL.
+*/
+CAPSTONE_EXPORT
+unsigned int CAPSTONE_API cs_version(int *major, int *minor);
+
+
+/**
+ This API can be used to either ask for archs supported by this library,
+ or check to see if the library was compile with 'diet' option (or called
+ in 'diet' mode).
+
+ To check if a particular arch is supported by this library, set @query to
+ arch mode (CS_ARCH_* value).
+ To verify if this library supports all the archs, use CS_ARCH_ALL.
+
+ To check if this library is in 'diet' mode, set @query to CS_SUPPORT_DIET.
+
+ @return True if this library supports the given arch, or in 'diet' mode.
+*/
+CAPSTONE_EXPORT
+bool CAPSTONE_API cs_support(int query);
+
+/**
+ Initialize CS handle: this must be done before any usage of CS.
+
+ @arch: architecture type (CS_ARCH_*)
+ @mode: hardware mode. This is combined of CS_MODE_*
+ @handle: pointer to handle, which will be updated at return time
+
+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
+ for detailed error).
+*/
+CAPSTONE_EXPORT
+cs_err CAPSTONE_API cs_open(cs_arch arch, cs_mode mode, csh *handle);
+
+/**
+ Close CS handle: MUST do to release the handle when it is not used anymore.
+ NOTE: this must be only called when there is no longer usage of Capstone,
+ not even access to cs_insn array. The reason is the this API releases some
+ cached memory, thus access to any Capstone API after cs_close() might crash
+ your application.
+
+ In fact,this API invalidate @handle by ZERO out its value (i.e *handle = 0).
+
+ @handle: pointer to a handle returned by cs_open()
+
+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
+ for detailed error).
+*/
+CAPSTONE_EXPORT
+cs_err CAPSTONE_API cs_close(csh *handle);
+
+/**
+ Set option for disassembling engine at runtime
+
+ @handle: handle returned by cs_open()
+ @type: type of option to be set
+ @value: option value corresponding with @type
+
+ @return: CS_ERR_OK on success, or other value on failure.
+ Refer to cs_err enum for detailed error.
+
+ NOTE: in the case of CS_OPT_MEM, handle's value can be anything,
+ so that cs_option(handle, CS_OPT_MEM, value) can (i.e must) be called
+ even before cs_open()
+*/
+CAPSTONE_EXPORT
+cs_err CAPSTONE_API cs_option(csh handle, cs_opt_type type, size_t value);
+
+/**
+ Report the last error number when some API function fail.
+ Like glibc's errno, cs_errno might not retain its old value once accessed.
+
+ @handle: handle returned by cs_open()
+
+ @return: error code of cs_err enum type (CS_ERR_*, see above)
+*/
+CAPSTONE_EXPORT
+cs_err CAPSTONE_API cs_errno(csh handle);
+
+
+/**
+ Return a string describing given error code.
+
+ @code: error code (see CS_ERR_* above)
+
+ @return: returns a pointer to a string that describes the error code
+	passed in the argument @code
+*/
+CAPSTONE_EXPORT
+const char * CAPSTONE_API cs_strerror(cs_err code);
+
+/**
+ Disassemble binary code, given the code buffer, size, address and number
+ of instructions to be decoded.
+ This API dynamically allocate memory to contain disassembled instruction.
+ Resulting instructions will be put into @*insn
+
+ NOTE 1: this API will automatically determine memory needed to contain
+ output disassembled instructions in @insn.
+
+ NOTE 2: caller must free the allocated memory itself to avoid memory leaking.
+
+ NOTE 3: for system with scarce memory to be dynamically allocated such as
+ OS kernel or firmware, the API cs_disasm_iter() might be a better choice than
+ cs_disasm(). The reason is that with cs_disasm(), based on limited available
+ memory, we have to calculate in advance how many instructions to be disassembled,
+ which complicates things. This is especially troublesome for the case @count=0,
+ when cs_disasm() runs uncontrollably (until either end of input buffer, or
+ when it encounters an invalid instruction).
+ 
+ @handle: handle returned by cs_open()
+ @code: buffer containing raw binary code to be disassembled.
+ @code_size: size of the above code buffer.
+ @address: address of the first instruction in given raw code buffer.
+ @insn: array of instructions filled in by this API.
+	   NOTE: @insn will be allocated by this function, and should be freed
+	   with cs_free() API.
+ @count: number of instructions to be disassembled, or 0 to get all of them
+
+ @return: the number of successfully disassembled instructions,
+ or 0 if this function failed to disassemble the given code
+
+ On failure, call cs_errno() for error code.
+*/
+CAPSTONE_EXPORT
+size_t CAPSTONE_API cs_disasm(csh handle,
+		const uint8_t *code, size_t code_size,
+		uint64_t address,
+		size_t count,
+		cs_insn **insn);
+
+/**
+ Free memory allocated by cs_malloc() or cs_disasm() (argument @insn)
+
+ @insn: pointer returned by @insn argument in cs_disasm() or cs_malloc()
+ @count: number of cs_insn structures returned by cs_disasm(), or 1
+     to free memory allocated by cs_malloc().
+*/
+CAPSTONE_EXPORT
+void CAPSTONE_API cs_free(cs_insn *insn, size_t count);
+
+
+/**
+ Allocate memory for 1 instruction to be used by cs_disasm_iter().
+
+ @handle: handle returned by cs_open()
+
+ NOTE: when no longer in use, you can reclaim the memory allocated for
+ this instruction with cs_free(insn, 1)
+*/
+CAPSTONE_EXPORT
+cs_insn * CAPSTONE_API cs_malloc(csh handle);
+
+/**
+ Fast API to disassemble binary code, given the code buffer, size, address
+ and number of instructions to be decoded.
+ This API puts the resulting instruction into a given cache in @insn.
+ See tests/test_iter.c for sample code demonstrating this API.
+
+ NOTE 1: this API will update @code, @size & @address to point to the next
+ instruction in the input buffer. Therefore, it is convenient to use
+ cs_disasm_iter() inside a loop to quickly iterate all the instructions.
+ While decoding one instruction at a time can also be achieved with
+ cs_disasm(count=1), some benchmarks shown that cs_disasm_iter() can be 30%
+ faster on random input.
+
+ NOTE 2: the cache in @insn can be created with cs_malloc() API.
+
+ NOTE 3: for system with scarce memory to be dynamically allocated such as
+ OS kernel or firmware, this API is recommended over cs_disasm(), which
+ allocates memory based on the number of instructions to be disassembled.
+ The reason is that with cs_disasm(), based on limited available memory,
+ we have to calculate in advance how many instructions to be disassembled,
+ which complicates things. This is especially troublesome for the case
+ @count=0, when cs_disasm() runs uncontrollably (until either end of input
+ buffer, or when it encounters an invalid instruction).
+ 
+ @handle: handle returned by cs_open()
+ @code: buffer containing raw binary code to be disassembled
+ @size: size of above code
+ @address: address of the first insn in given raw code buffer
+ @insn: pointer to instruction to be filled in by this API.
+
+ @return: true if this API successfully decode 1 instruction,
+ or false otherwise.
+
+ On failure, call cs_errno() for error code.
+*/
+CAPSTONE_EXPORT
+bool CAPSTONE_API cs_disasm_iter(csh handle,
+	const uint8_t **code, size_t *size,
+	uint64_t *address, cs_insn *insn);
+
+/**
+ Return friendly name of register in a string.
+ Find the instruction id from header file of corresponding architecture (arm.h for ARM,
+ x86.h for X86, ...)
+
+ WARN: when in 'diet' mode, this API is irrelevant because engine does not
+ store register name.
+
+ @handle: handle returned by cs_open()
+ @reg_id: register id
+
+ @return: string name of the register, or NULL if @reg_id is invalid.
+*/
+CAPSTONE_EXPORT
+const char * CAPSTONE_API cs_reg_name(csh handle, unsigned int reg_id);
+
+/**
+ Return friendly name of an instruction in a string.
+ Find the instruction id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ store instruction name.
+
+ @handle: handle returned by cs_open()
+ @insn_id: instruction id
+
+ @return: string name of the instruction, or NULL if @insn_id is invalid.
+*/
+CAPSTONE_EXPORT
+const char * CAPSTONE_API cs_insn_name(csh handle, unsigned int insn_id);
+
+/**
+ Return friendly name of a group id (that an instruction can belong to)
+ Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ store group name.
+
+ @handle: handle returned by cs_open()
+ @group_id: group id
+
+ @return: string name of the group, or NULL if @group_id is invalid.
+*/
+CAPSTONE_EXPORT
+const char * CAPSTONE_API cs_group_name(csh handle, unsigned int group_id);
+
+/**
+ Check if a disassembled instruction belong to a particular group.
+ Find the group id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+ Internally, this simply verifies if @group_id matches any member of insn->groups array.
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default).
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ update @groups array.
+
+ @handle: handle returned by cs_open()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @group_id: group that you want to check if this instruction belong to.
+
+ @return: true if this instruction indeed belongs to the given group, or false otherwise.
+*/
+CAPSTONE_EXPORT
+bool CAPSTONE_API cs_insn_group(csh handle, const cs_insn *insn, unsigned int group_id);
+
+/**
+ Check if a disassembled instruction IMPLICITLY used a particular register.
+ Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+ Internally, this simply verifies if @reg_id matches any member of insn->regs_read array.
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ update @regs_read array.
+
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @reg_id: register that you want to check if this instruction used it.
+
+ @return: true if this instruction indeed implicitly used the given register, or false otherwise.
+*/
+CAPSTONE_EXPORT
+bool CAPSTONE_API cs_reg_read(csh handle, const cs_insn *insn, unsigned int reg_id);
+
+/**
+ Check if a disassembled instruction IMPLICITLY modified a particular register.
+ Find the register id from header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+ Internally, this simply verifies if @reg_id matches any member of insn->regs_write array.
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default)
+
+ WARN: when in 'diet' mode, this API is irrelevant because the engine does not
+ update @regs_write array.
+
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @reg_id: register that you want to check if this instruction modified it.
+
+ @return: true if this instruction indeed implicitly modified the given register, or false otherwise.
+*/
+CAPSTONE_EXPORT
+bool CAPSTONE_API cs_reg_write(csh handle, const cs_insn *insn, unsigned int reg_id);
+
+/**
+ Count the number of operands of a given type.
+ Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default)
+
+ @handle: handle returned by cs_open()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @op_type: Operand type to be found.
+
+ @return: number of operands of given type @op_type in instruction @insn,
+ or -1 on failure.
+*/
+CAPSTONE_EXPORT
+int CAPSTONE_API cs_op_count(csh handle, const cs_insn *insn, unsigned int op_type);
+
+/**
+ Retrieve the position of operand of given type in <arch>.operands[] array.
+ Later, the operand can be accessed using the returned position.
+ Find the operand type in header file of corresponding architecture (arm.h for ARM, x86.h for X86, ...)
+
+ NOTE: this API is only valid when detail option is ON (which is OFF by default)
+
+ @handle: handle returned by cs_open()
+ @insn: disassembled instruction structure received from cs_disasm() or cs_disasm_iter()
+ @op_type: Operand type to be found.
+ @position: position of the operand to be found. This must be in the range
+			[1, cs_op_count(handle, insn, op_type)]
+
+ @return: index of operand of given type @op_type in <arch>.operands[] array
+ in instruction @insn, or -1 on failure.
+*/
+CAPSTONE_EXPORT
+int CAPSTONE_API cs_op_index(csh handle, const cs_insn *insn, unsigned int op_type,
+		unsigned int position);
+
+/// Type of array to keep the list of registers
+typedef uint16_t cs_regs[64];
+
+/**
+ Retrieve all the registers accessed by an instruction, either explicitly or
+ implicitly.
+
+ WARN: when in 'diet' mode, this API is irrelevant because engine does not
+ store registers.
+
+ @handle: handle returned by cs_open()
+ @insn: disassembled instruction structure returned from cs_disasm() or cs_disasm_iter()
+ @regs_read: on return, this array contains all registers read by instruction.
+ @regs_read_count: number of registers kept inside @regs_read array.
+ @regs_write: on return, this array contains all registers written by instruction.
+ @regs_write_count: number of registers kept inside @regs_write array.
+
+ @return CS_ERR_OK on success, or other value on failure (refer to cs_err enum
+ for detailed error).
+*/
+CAPSTONE_EXPORT
+cs_err CAPSTONE_API cs_regs_access(csh handle, const cs_insn *insn,
+		cs_regs regs_read, uint8_t *regs_read_count,
+		cs_regs regs_write, uint8_t *regs_write_count);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

.tools/python-revlibs/capstone/include/capstone/evm.h

@@ -0,0 +1,188 @@
+#ifndef CAPSTONE_EVM_H
+#define CAPSTONE_EVM_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2018 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// Instruction structure
+typedef struct cs_evm {
+    unsigned char pop;    ///< number of items popped from the stack
+    unsigned char push;   ///< number of items pushed into the stack
+    unsigned int  fee;    ///< gas fee for the instruction
+} cs_evm;
+
+/// EVM instruction
+typedef enum evm_insn {
+	EVM_INS_STOP = 0,
+	EVM_INS_ADD = 1,
+	EVM_INS_MUL = 2,
+	EVM_INS_SUB = 3,
+	EVM_INS_DIV = 4,
+	EVM_INS_SDIV = 5,
+	EVM_INS_MOD = 6,
+	EVM_INS_SMOD = 7,
+	EVM_INS_ADDMOD = 8,
+	EVM_INS_MULMOD = 9,
+	EVM_INS_EXP = 10,
+	EVM_INS_SIGNEXTEND = 11,
+	EVM_INS_LT = 16,
+	EVM_INS_GT = 17,
+	EVM_INS_SLT = 18,
+	EVM_INS_SGT = 19,
+	EVM_INS_EQ = 20,
+	EVM_INS_ISZERO = 21,
+	EVM_INS_AND = 22,
+	EVM_INS_OR = 23,
+	EVM_INS_XOR = 24,
+	EVM_INS_NOT = 25,
+	EVM_INS_BYTE = 26,
+	EVM_INS_SHA3 = 32,
+	EVM_INS_ADDRESS = 48,
+	EVM_INS_BALANCE = 49,
+	EVM_INS_ORIGIN = 50,
+	EVM_INS_CALLER = 51,
+	EVM_INS_CALLVALUE = 52,
+	EVM_INS_CALLDATALOAD = 53,
+	EVM_INS_CALLDATASIZE = 54,
+	EVM_INS_CALLDATACOPY = 55,
+	EVM_INS_CODESIZE = 56,
+	EVM_INS_CODECOPY = 57,
+	EVM_INS_GASPRICE = 58,
+	EVM_INS_EXTCODESIZE = 59,
+	EVM_INS_EXTCODECOPY = 60,
+	EVM_INS_RETURNDATASIZE = 61,
+	EVM_INS_RETURNDATACOPY = 62,
+	EVM_INS_BLOCKHASH = 64,
+	EVM_INS_COINBASE = 65,
+	EVM_INS_TIMESTAMP = 66,
+	EVM_INS_NUMBER = 67,
+	EVM_INS_DIFFICULTY = 68,
+	EVM_INS_GASLIMIT = 69,
+	EVM_INS_POP = 80,
+	EVM_INS_MLOAD = 81,
+	EVM_INS_MSTORE = 82,
+	EVM_INS_MSTORE8 = 83,
+	EVM_INS_SLOAD = 84,
+	EVM_INS_SSTORE = 85,
+	EVM_INS_JUMP = 86,
+	EVM_INS_JUMPI = 87,
+	EVM_INS_PC = 88,
+	EVM_INS_MSIZE = 89,
+	EVM_INS_GAS = 90,
+	EVM_INS_JUMPDEST = 91,
+	EVM_INS_PUSH1 = 96,
+	EVM_INS_PUSH2 = 97,
+	EVM_INS_PUSH3 = 98,
+	EVM_INS_PUSH4 = 99,
+	EVM_INS_PUSH5 = 100,
+	EVM_INS_PUSH6 = 101,
+	EVM_INS_PUSH7 = 102,
+	EVM_INS_PUSH8 = 103,
+	EVM_INS_PUSH9 = 104,
+	EVM_INS_PUSH10 = 105,
+	EVM_INS_PUSH11 = 106,
+	EVM_INS_PUSH12 = 107,
+	EVM_INS_PUSH13 = 108,
+	EVM_INS_PUSH14 = 109,
+	EVM_INS_PUSH15 = 110,
+	EVM_INS_PUSH16 = 111,
+	EVM_INS_PUSH17 = 112,
+	EVM_INS_PUSH18 = 113,
+	EVM_INS_PUSH19 = 114,
+	EVM_INS_PUSH20 = 115,
+	EVM_INS_PUSH21 = 116,
+	EVM_INS_PUSH22 = 117,
+	EVM_INS_PUSH23 = 118,
+	EVM_INS_PUSH24 = 119,
+	EVM_INS_PUSH25 = 120,
+	EVM_INS_PUSH26 = 121,
+	EVM_INS_PUSH27 = 122,
+	EVM_INS_PUSH28 = 123,
+	EVM_INS_PUSH29 = 124,
+	EVM_INS_PUSH30 = 125,
+	EVM_INS_PUSH31 = 126,
+	EVM_INS_PUSH32 = 127,
+	EVM_INS_DUP1 = 128,
+	EVM_INS_DUP2 = 129,
+	EVM_INS_DUP3 = 130,
+	EVM_INS_DUP4 = 131,
+	EVM_INS_DUP5 = 132,
+	EVM_INS_DUP6 = 133,
+	EVM_INS_DUP7 = 134,
+	EVM_INS_DUP8 = 135,
+	EVM_INS_DUP9 = 136,
+	EVM_INS_DUP10 = 137,
+	EVM_INS_DUP11 = 138,
+	EVM_INS_DUP12 = 139,
+	EVM_INS_DUP13 = 140,
+	EVM_INS_DUP14 = 141,
+	EVM_INS_DUP15 = 142,
+	EVM_INS_DUP16 = 143,
+	EVM_INS_SWAP1 = 144,
+	EVM_INS_SWAP2 = 145,
+	EVM_INS_SWAP3 = 146,
+	EVM_INS_SWAP4 = 147,
+	EVM_INS_SWAP5 = 148,
+	EVM_INS_SWAP6 = 149,
+	EVM_INS_SWAP7 = 150,
+	EVM_INS_SWAP8 = 151,
+	EVM_INS_SWAP9 = 152,
+	EVM_INS_SWAP10 = 153,
+	EVM_INS_SWAP11 = 154,
+	EVM_INS_SWAP12 = 155,
+	EVM_INS_SWAP13 = 156,
+	EVM_INS_SWAP14 = 157,
+	EVM_INS_SWAP15 = 158,
+	EVM_INS_SWAP16 = 159,
+	EVM_INS_LOG0 = 160,
+	EVM_INS_LOG1 = 161,
+	EVM_INS_LOG2 = 162,
+	EVM_INS_LOG3 = 163,
+	EVM_INS_LOG4 = 164,
+	EVM_INS_CREATE = 240,
+	EVM_INS_CALL = 241,
+	EVM_INS_CALLCODE = 242,
+	EVM_INS_RETURN = 243,
+	EVM_INS_DELEGATECALL = 244,
+	EVM_INS_CALLBLACKBOX = 245,
+	EVM_INS_STATICCALL = 250,
+	EVM_INS_REVERT = 253,
+	EVM_INS_SUICIDE = 255,
+
+	EVM_INS_INVALID = 512,
+	EVM_INS_ENDING,   // <-- mark the end of the list of instructions
+} evm_insn;
+
+/// Group of EVM instructions
+typedef enum evm_insn_group {
+	EVM_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+	EVM_GRP_JUMP,          ///< all jump instructions
+
+	EVM_GRP_MATH = 8,      ///< math instructions
+	EVM_GRP_STACK_WRITE,   ///< instructions write to stack
+	EVM_GRP_STACK_READ,    ///< instructions read from stack
+	EVM_GRP_MEM_WRITE,     ///< instructions write to memory
+	EVM_GRP_MEM_READ,      ///< instructions read from memory
+	EVM_GRP_STORE_WRITE,   ///< instructions write to storage
+	EVM_GRP_STORE_READ,    ///< instructions read from storage
+	EVM_GRP_HALT,    ///< instructions halt execution
+
+	EVM_GRP_ENDING,   ///< <-- mark the end of the list of groups
+} evm_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

.tools/python-revlibs/capstone/include/capstone/m680x.h

@@ -0,0 +1,537 @@
+#ifndef CAPSTONE_M680X_H
+#define CAPSTONE_M680X_H
+
+/* Capstone Disassembly Engine */
+/* M680X Backend by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net> 2017 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+#define M680X_OPERAND_COUNT 9
+
+/// M680X registers and special registers
+typedef enum m680x_reg {
+	M680X_REG_INVALID = 0,
+
+	M680X_REG_A, ///< M6800/1/2/3/9, HD6301/9
+	M680X_REG_B, ///< M6800/1/2/3/9, HD6301/9
+	M680X_REG_E, ///< HD6309
+	M680X_REG_F, ///< HD6309
+	M680X_REG_0, ///< HD6309
+
+	M680X_REG_D, ///< M6801/3/9, HD6301/9
+	M680X_REG_W, ///< HD6309
+
+	M680X_REG_CC, ///< M6800/1/2/3/9, M6301/9
+	M680X_REG_DP, ///< M6809/M6309
+	M680X_REG_MD, ///< M6309
+
+	M680X_REG_HX, ///< M6808
+	M680X_REG_H, ///< M6808
+	M680X_REG_X, ///< M6800/1/2/3/9, M6301/9
+	M680X_REG_Y, ///< M6809/M6309
+	M680X_REG_S, ///< M6809/M6309
+	M680X_REG_U, ///< M6809/M6309
+	M680X_REG_V, ///< M6309
+
+	M680X_REG_Q, ///< M6309
+
+	M680X_REG_PC, ///< M6800/1/2/3/9, M6301/9
+
+	M680X_REG_TMP2, ///< CPU12
+	M680X_REG_TMP3, ///< CPU12
+
+	M680X_REG_ENDING,   ///< <-- mark the end of the list of registers
+} m680x_reg;
+
+/// Operand type for instruction's operands
+typedef enum m680x_op_type {
+	M680X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+	M680X_OP_REGISTER,    ///< = Register operand.
+	M680X_OP_IMMEDIATE,   ///< = Immediate operand.
+	M680X_OP_INDEXED,     ///< = Indexed addressing operand.
+	M680X_OP_EXTENDED,    ///< = Extended addressing operand.
+	M680X_OP_DIRECT,      ///< = Direct addressing operand.
+	M680X_OP_RELATIVE,    ///< = Relative addressing operand.
+	M680X_OP_CONSTANT,    ///< = constant operand (Displayed as number only).
+				///< Used e.g. for a bit index or page number.
+} m680x_op_type;
+
+// Supported bit values for mem.idx.offset_bits
+#define M680X_OFFSET_NONE      0
+#define M680X_OFFSET_BITS_5    5
+#define M680X_OFFSET_BITS_8    8
+#define M680X_OFFSET_BITS_9    9
+#define M680X_OFFSET_BITS_16  16
+
+// Supported bit flags for mem.idx.flags
+// These flags can be combined
+#define M680X_IDX_INDIRECT     1
+#define M680X_IDX_NO_COMMA     2
+#define M680X_IDX_POST_INC_DEC 4
+
+/// Instruction's operand referring to indexed addressing
+typedef struct m680x_op_idx {
+	m680x_reg base_reg;	///< base register (or M680X_REG_INVALID if
+				///< irrelevant)
+	m680x_reg offset_reg;	///< offset register (or M680X_REG_INVALID if
+				///< irrelevant)
+	int16_t offset;		///< 5-,8- or 16-bit offset. See also offset_bits.
+	uint16_t offset_addr;	///< = offset addr. if base_reg == M680X_REG_PC.
+				///< calculated as offset + PC
+	uint8_t offset_bits;	///< offset width in bits for indexed addressing
+	int8_t inc_dec;		///< inc. or dec. value:
+				///<    0: no inc-/decrement
+				///<    1 .. 8: increment by 1 .. 8
+				///<    -1 .. -8: decrement by 1 .. 8
+				///< if flag M680X_IDX_POST_INC_DEC set it is post
+				///< inc-/decrement otherwise pre inc-/decrement
+	uint8_t flags;		///< 8-bit flags (see above)
+} m680x_op_idx;
+
+/// Instruction's memory operand referring to relative addressing (Bcc/LBcc)
+typedef struct m680x_op_rel {
+	uint16_t address;	///< The absolute address.
+				///< calculated as PC + offset. PC is the first
+				///< address after the instruction.
+	int16_t offset;		///< the offset/displacement value
+} m680x_op_rel;
+
+/// Instruction's operand referring to extended addressing
+typedef struct m680x_op_ext {
+	uint16_t address;      ///< The absolute address
+	bool indirect;         ///< true if extended indirect addressing
+} m680x_op_ext;
+
+/// Instruction operand
+typedef struct cs_m680x_op {
+	m680x_op_type type;
+	union {
+		int32_t imm;		///< immediate value for IMM operand
+		m680x_reg reg;		///< register value for REG operand
+		m680x_op_idx idx;	///< Indexed addressing operand
+		m680x_op_rel rel;	///< Relative address. operand (Bcc/LBcc)
+		m680x_op_ext ext;	///< Extended address
+		uint8_t direct_addr;	///<</ Direct address (lower 8-bit)
+		uint8_t const_val;	///< constant value (bit index, page nr.)
+	};
+	uint8_t size;			///< size of this operand (in bytes)
+	/// How is this operand accessed? (READ, WRITE or READ|WRITE)
+	/// This field is combined of cs_ac_type.
+	/// NOTE: this field is irrelevant if engine is compiled in DIET 
+	uint8_t access;
+} cs_m680x_op;
+
+/// Group of M680X instructions
+typedef enum m680x_group_type {
+	M680X_GRP_INVALID = 0,	/// = CS_GRP_INVALID
+	// Generic groups
+	// all jump instructions (conditional+direct+indirect jumps)
+	M680X_GRP_JUMP,		///< = CS_GRP_JUMP
+	// all call instructions
+	M680X_GRP_CALL,		///< = CS_GRP_CALL
+	// all return instructions
+	M680X_GRP_RET,		///< = CS_GRP_RET
+	// all interrupt instructions (int+syscall)
+	M680X_GRP_INT,		///< = CS_GRP_INT
+	// all interrupt return instructions
+	M680X_GRP_IRET,		///< = CS_GRP_IRET
+	// all privileged instructions
+	M680X_GRP_PRIV,		///< = CS_GRP_PRIVILEDGE; not used
+	// all relative branching instructions
+	M680X_GRP_BRAREL,	///< = CS_GRP_BRANCH_RELATIVE
+
+	// Architecture-specific groups
+	M680X_GRP_ENDING,	// <-- mark the end of the list of groups
+} m680x_group_type;
+
+// M680X instruction flags:
+
+/// The first (register) operand is part of the
+/// instruction mnemonic
+#define M680X_FIRST_OP_IN_MNEM    1
+/// The second (register) operand is part of the
+/// instruction mnemonic
+#define M680X_SECOND_OP_IN_MNEM   2
+
+/// The M680X instruction and it's operands
+typedef struct cs_m680x {
+	uint8_t flags;		///< See: M680X instruction flags
+	uint8_t op_count;	///< number of operands for the instruction or 0
+	cs_m680x_op operands[M680X_OPERAND_COUNT]; ///< operands for this insn.
+} cs_m680x;
+
+/// M680X instruction IDs
+typedef enum m680x_insn {
+	M680X_INS_INVLD = 0,
+	M680X_INS_ABA, ///< M6800/1/2/3
+	M680X_INS_ABX,
+	M680X_INS_ABY,
+	M680X_INS_ADC,
+	M680X_INS_ADCA,
+	M680X_INS_ADCB,
+	M680X_INS_ADCD,
+	M680X_INS_ADCR,
+	M680X_INS_ADD,
+	M680X_INS_ADDA,
+	M680X_INS_ADDB,
+	M680X_INS_ADDD,
+	M680X_INS_ADDE,
+	M680X_INS_ADDF,
+	M680X_INS_ADDR,
+	M680X_INS_ADDW,
+	M680X_INS_AIM,
+	M680X_INS_AIS,
+	M680X_INS_AIX,
+	M680X_INS_AND,
+	M680X_INS_ANDA,
+	M680X_INS_ANDB,
+	M680X_INS_ANDCC,
+	M680X_INS_ANDD,
+	M680X_INS_ANDR,
+	M680X_INS_ASL,
+	M680X_INS_ASLA,
+	M680X_INS_ASLB,
+	M680X_INS_ASLD, ///< or LSLD
+	M680X_INS_ASR,
+	M680X_INS_ASRA,
+	M680X_INS_ASRB,
+	M680X_INS_ASRD,
+	M680X_INS_ASRX,
+	M680X_INS_BAND,
+	M680X_INS_BCC, ///< or BHS
+	M680X_INS_BCLR,
+	M680X_INS_BCS, ///< or BLO
+	M680X_INS_BEOR,
+	M680X_INS_BEQ,
+	M680X_INS_BGE,
+	M680X_INS_BGND,
+	M680X_INS_BGT,
+	M680X_INS_BHCC,
+	M680X_INS_BHCS,
+	M680X_INS_BHI,
+	M680X_INS_BIAND,
+	M680X_INS_BIEOR,
+	M680X_INS_BIH,
+	M680X_INS_BIL,
+	M680X_INS_BIOR,
+	M680X_INS_BIT,
+	M680X_INS_BITA,
+	M680X_INS_BITB,
+	M680X_INS_BITD,
+	M680X_INS_BITMD,
+	M680X_INS_BLE,
+	M680X_INS_BLS,
+	M680X_INS_BLT,
+	M680X_INS_BMC,
+	M680X_INS_BMI,
+	M680X_INS_BMS,
+	M680X_INS_BNE,
+	M680X_INS_BOR,
+	M680X_INS_BPL,
+	M680X_INS_BRCLR,
+	M680X_INS_BRSET,
+	M680X_INS_BRA,
+	M680X_INS_BRN,
+	M680X_INS_BSET,
+	M680X_INS_BSR,
+	M680X_INS_BVC,
+	M680X_INS_BVS,
+	M680X_INS_CALL,
+	M680X_INS_CBA, ///< M6800/1/2/3
+	M680X_INS_CBEQ,
+	M680X_INS_CBEQA,
+	M680X_INS_CBEQX,
+	M680X_INS_CLC, ///< M6800/1/2/3
+	M680X_INS_CLI, ///< M6800/1/2/3
+	M680X_INS_CLR,
+	M680X_INS_CLRA,
+	M680X_INS_CLRB,
+	M680X_INS_CLRD,
+	M680X_INS_CLRE,
+	M680X_INS_CLRF,
+	M680X_INS_CLRH,
+	M680X_INS_CLRW,
+	M680X_INS_CLRX,
+	M680X_INS_CLV, ///< M6800/1/2/3
+	M680X_INS_CMP,
+	M680X_INS_CMPA,
+	M680X_INS_CMPB,
+	M680X_INS_CMPD,
+	M680X_INS_CMPE,
+	M680X_INS_CMPF,
+	M680X_INS_CMPR,
+	M680X_INS_CMPS,
+	M680X_INS_CMPU,
+	M680X_INS_CMPW,
+	M680X_INS_CMPX,
+	M680X_INS_CMPY,
+	M680X_INS_COM,
+	M680X_INS_COMA,
+	M680X_INS_COMB,
+	M680X_INS_COMD,
+	M680X_INS_COME,
+	M680X_INS_COMF,
+	M680X_INS_COMW,
+	M680X_INS_COMX,
+	M680X_INS_CPD,
+	M680X_INS_CPHX,
+	M680X_INS_CPS,
+	M680X_INS_CPX, ///< M6800/1/2/3
+	M680X_INS_CPY,
+	M680X_INS_CWAI,
+	M680X_INS_DAA,
+	M680X_INS_DBEQ,
+	M680X_INS_DBNE,
+	M680X_INS_DBNZ,
+	M680X_INS_DBNZA,
+	M680X_INS_DBNZX,
+	M680X_INS_DEC,
+	M680X_INS_DECA,
+	M680X_INS_DECB,
+	M680X_INS_DECD,
+	M680X_INS_DECE,
+	M680X_INS_DECF,
+	M680X_INS_DECW,
+	M680X_INS_DECX,
+	M680X_INS_DES, ///< M6800/1/2/3
+	M680X_INS_DEX, ///< M6800/1/2/3
+	M680X_INS_DEY,
+	M680X_INS_DIV,
+	M680X_INS_DIVD,
+	M680X_INS_DIVQ,
+	M680X_INS_EDIV,
+	M680X_INS_EDIVS,
+	M680X_INS_EIM,
+	M680X_INS_EMACS,
+	M680X_INS_EMAXD,
+	M680X_INS_EMAXM,
+	M680X_INS_EMIND,
+	M680X_INS_EMINM,
+	M680X_INS_EMUL,
+	M680X_INS_EMULS,
+	M680X_INS_EOR,
+	M680X_INS_EORA,
+	M680X_INS_EORB,
+	M680X_INS_EORD,
+	M680X_INS_EORR,
+	M680X_INS_ETBL,
+	M680X_INS_EXG,
+	M680X_INS_FDIV,
+	M680X_INS_IBEQ,
+	M680X_INS_IBNE,
+	M680X_INS_IDIV,
+	M680X_INS_IDIVS,
+	M680X_INS_ILLGL,
+	M680X_INS_INC,
+	M680X_INS_INCA,
+	M680X_INS_INCB,
+	M680X_INS_INCD,
+	M680X_INS_INCE,
+	M680X_INS_INCF,
+	M680X_INS_INCW,
+	M680X_INS_INCX,
+	M680X_INS_INS, ///< M6800/1/2/3
+	M680X_INS_INX, ///< M6800/1/2/3
+	M680X_INS_INY,
+	M680X_INS_JMP,
+	M680X_INS_JSR,
+	M680X_INS_LBCC, ///< or LBHS
+	M680X_INS_LBCS, ///< or LBLO
+	M680X_INS_LBEQ,
+	M680X_INS_LBGE,
+	M680X_INS_LBGT,
+	M680X_INS_LBHI,
+	M680X_INS_LBLE,
+	M680X_INS_LBLS,
+	M680X_INS_LBLT,
+	M680X_INS_LBMI,
+	M680X_INS_LBNE,
+	M680X_INS_LBPL,
+	M680X_INS_LBRA,
+	M680X_INS_LBRN,
+	M680X_INS_LBSR,
+	M680X_INS_LBVC,
+	M680X_INS_LBVS,
+	M680X_INS_LDA,
+	M680X_INS_LDAA, ///< M6800/1/2/3
+	M680X_INS_LDAB, ///< M6800/1/2/3
+	M680X_INS_LDB,
+	M680X_INS_LDBT,
+	M680X_INS_LDD,
+	M680X_INS_LDE,
+	M680X_INS_LDF,
+	M680X_INS_LDHX,
+	M680X_INS_LDMD,
+	M680X_INS_LDQ,
+	M680X_INS_LDS,
+	M680X_INS_LDU,
+	M680X_INS_LDW,
+	M680X_INS_LDX,
+	M680X_INS_LDY,
+	M680X_INS_LEAS,
+	M680X_INS_LEAU,
+	M680X_INS_LEAX,
+	M680X_INS_LEAY,
+	M680X_INS_LSL,
+	M680X_INS_LSLA,
+	M680X_INS_LSLB,
+	M680X_INS_LSLD,
+	M680X_INS_LSLX,
+	M680X_INS_LSR,
+	M680X_INS_LSRA,
+	M680X_INS_LSRB,
+	M680X_INS_LSRD, ///< or ASRD
+	M680X_INS_LSRW,
+	M680X_INS_LSRX,
+	M680X_INS_MAXA,
+	M680X_INS_MAXM,
+	M680X_INS_MEM,
+	M680X_INS_MINA,
+	M680X_INS_MINM,
+	M680X_INS_MOV,
+	M680X_INS_MOVB,
+	M680X_INS_MOVW,
+	M680X_INS_MUL,
+	M680X_INS_MULD,
+	M680X_INS_NEG,
+	M680X_INS_NEGA,
+	M680X_INS_NEGB,
+	M680X_INS_NEGD,
+	M680X_INS_NEGX,
+	M680X_INS_NOP,
+	M680X_INS_NSA,
+	M680X_INS_OIM,
+	M680X_INS_ORA,
+	M680X_INS_ORAA, ///< M6800/1/2/3
+	M680X_INS_ORAB, ///< M6800/1/2/3
+	M680X_INS_ORB,
+	M680X_INS_ORCC,
+	M680X_INS_ORD,
+	M680X_INS_ORR,
+	M680X_INS_PSHA, ///< M6800/1/2/3
+	M680X_INS_PSHB, ///< M6800/1/2/3
+	M680X_INS_PSHC,
+	M680X_INS_PSHD,
+	M680X_INS_PSHH,
+	M680X_INS_PSHS,
+	M680X_INS_PSHSW,
+	M680X_INS_PSHU,
+	M680X_INS_PSHUW,
+	M680X_INS_PSHX, ///< M6800/1/2/3
+	M680X_INS_PSHY,
+	M680X_INS_PULA, ///< M6800/1/2/3
+	M680X_INS_PULB, ///< M6800/1/2/3
+	M680X_INS_PULC,
+	M680X_INS_PULD,
+	M680X_INS_PULH,
+	M680X_INS_PULS,
+	M680X_INS_PULSW,
+	M680X_INS_PULU,
+	M680X_INS_PULUW,
+	M680X_INS_PULX, ///< M6800/1/2/3
+	M680X_INS_PULY,
+	M680X_INS_REV,
+	M680X_INS_REVW,
+	M680X_INS_ROL,
+	M680X_INS_ROLA,
+	M680X_INS_ROLB,
+	M680X_INS_ROLD,
+	M680X_INS_ROLW,
+	M680X_INS_ROLX,
+	M680X_INS_ROR,
+	M680X_INS_RORA,
+	M680X_INS_RORB,
+	M680X_INS_RORD,
+	M680X_INS_RORW,
+	M680X_INS_RORX,
+	M680X_INS_RSP,
+	M680X_INS_RTC,
+	M680X_INS_RTI,
+	M680X_INS_RTS,
+	M680X_INS_SBA, ///< M6800/1/2/3
+	M680X_INS_SBC,
+	M680X_INS_SBCA,
+	M680X_INS_SBCB,
+	M680X_INS_SBCD,
+	M680X_INS_SBCR,
+	M680X_INS_SEC,
+	M680X_INS_SEI,
+	M680X_INS_SEV,
+	M680X_INS_SEX,
+	M680X_INS_SEXW,
+	M680X_INS_SLP,
+	M680X_INS_STA,
+	M680X_INS_STAA, ///< M6800/1/2/3
+	M680X_INS_STAB, ///< M6800/1/2/3
+	M680X_INS_STB,
+	M680X_INS_STBT,
+	M680X_INS_STD,
+	M680X_INS_STE,
+	M680X_INS_STF,
+	M680X_INS_STOP,
+	M680X_INS_STHX,
+	M680X_INS_STQ,
+	M680X_INS_STS,
+	M680X_INS_STU,
+	M680X_INS_STW,
+	M680X_INS_STX,
+	M680X_INS_STY,
+	M680X_INS_SUB,
+	M680X_INS_SUBA,
+	M680X_INS_SUBB,
+	M680X_INS_SUBD,
+	M680X_INS_SUBE,
+	M680X_INS_SUBF,
+	M680X_INS_SUBR,
+	M680X_INS_SUBW,
+	M680X_INS_SWI,
+	M680X_INS_SWI2,
+	M680X_INS_SWI3,
+	M680X_INS_SYNC,
+	M680X_INS_TAB, ///< M6800/1/2/3
+	M680X_INS_TAP, ///< M6800/1/2/3
+	M680X_INS_TAX,
+	M680X_INS_TBA, ///< M6800/1/2/3
+	M680X_INS_TBEQ,
+	M680X_INS_TBL,
+	M680X_INS_TBNE,
+	M680X_INS_TEST,
+	M680X_INS_TFM,
+	M680X_INS_TFR,
+	M680X_INS_TIM,
+	M680X_INS_TPA, ///< M6800/1/2/3
+	M680X_INS_TST,
+	M680X_INS_TSTA,
+	M680X_INS_TSTB,
+	M680X_INS_TSTD,
+	M680X_INS_TSTE,
+	M680X_INS_TSTF,
+	M680X_INS_TSTW,
+	M680X_INS_TSTX,
+	M680X_INS_TSX, ///< M6800/1/2/3
+	M680X_INS_TSY,
+	M680X_INS_TXA,
+	M680X_INS_TXS, ///< M6800/1/2/3
+	M680X_INS_TYS,
+	M680X_INS_WAI, ///< M6800/1/2/3
+	M680X_INS_WAIT,
+	M680X_INS_WAV,
+	M680X_INS_WAVR,
+	M680X_INS_XGDX, ///< HD6301
+	M680X_INS_XGDY,
+	M680X_INS_ENDING,   // <-- mark the end of the list of instructions
+} m680x_insn;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

.tools/python-revlibs/capstone/include/capstone/m68k.h

@@ -0,0 +1,613 @@
+#ifndef CAPSTONE_M68K_H
+#define CAPSTONE_M68K_H
+
+/* Capstone Disassembly Engine */
+/* By Daniel Collin <daniel@collin.com>, 2015-2016 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+#define M68K_OPERAND_COUNT 4
+
+/// M68K registers and special registers
+typedef enum m68k_reg {
+	M68K_REG_INVALID = 0,
+
+	M68K_REG_D0,
+	M68K_REG_D1,
+	M68K_REG_D2,
+	M68K_REG_D3,
+	M68K_REG_D4,
+	M68K_REG_D5,
+	M68K_REG_D6,
+	M68K_REG_D7,
+
+	M68K_REG_A0,
+	M68K_REG_A1,
+	M68K_REG_A2,
+	M68K_REG_A3,
+	M68K_REG_A4,
+	M68K_REG_A5,
+	M68K_REG_A6,
+	M68K_REG_A7,
+
+	M68K_REG_FP0,
+	M68K_REG_FP1,
+	M68K_REG_FP2,
+	M68K_REG_FP3,
+	M68K_REG_FP4,
+	M68K_REG_FP5,
+	M68K_REG_FP6,
+	M68K_REG_FP7,
+
+	M68K_REG_PC,
+
+	M68K_REG_SR,
+	M68K_REG_CCR,
+	M68K_REG_SFC,
+	M68K_REG_DFC,
+	M68K_REG_USP,
+	M68K_REG_VBR,
+	M68K_REG_CACR,
+	M68K_REG_CAAR,
+	M68K_REG_MSP,
+	M68K_REG_ISP,
+	M68K_REG_TC,
+	M68K_REG_ITT0,
+	M68K_REG_ITT1,
+	M68K_REG_DTT0,
+	M68K_REG_DTT1,
+	M68K_REG_MMUSR,
+	M68K_REG_URP,
+	M68K_REG_SRP,
+
+	M68K_REG_FPCR,
+	M68K_REG_FPSR,
+	M68K_REG_FPIAR,
+
+	M68K_REG_ENDING,   // <-- mark the end of the list of registers
+} m68k_reg;
+
+/// M68K Addressing Modes
+typedef enum m68k_address_mode {
+	M68K_AM_NONE = 0,			///< No address mode.
+
+	M68K_AM_REG_DIRECT_DATA,		///< Register Direct - Data
+	M68K_AM_REG_DIRECT_ADDR,		///< Register Direct - Address
+
+	M68K_AM_REGI_ADDR,				///< Register Indirect - Address
+	M68K_AM_REGI_ADDR_POST_INC,		///< Register Indirect - Address with Postincrement
+	M68K_AM_REGI_ADDR_PRE_DEC,		///< Register Indirect - Address with Predecrement
+	M68K_AM_REGI_ADDR_DISP,			///< Register Indirect - Address with Displacement
+
+	M68K_AM_AREGI_INDEX_8_BIT_DISP,	///< Address Register Indirect With Index- 8-bit displacement
+	M68K_AM_AREGI_INDEX_BASE_DISP,	///< Address Register Indirect With Index- Base displacement
+
+	M68K_AM_MEMI_POST_INDEX,		///< Memory indirect - Postindex
+	M68K_AM_MEMI_PRE_INDEX,			///< Memory indirect - Preindex
+
+	M68K_AM_PCI_DISP,				///< Program Counter Indirect - with Displacement
+
+	M68K_AM_PCI_INDEX_8_BIT_DISP,	///< Program Counter Indirect with Index - with 8-Bit Displacement
+	M68K_AM_PCI_INDEX_BASE_DISP,	///< Program Counter Indirect with Index - with Base Displacement
+
+	M68K_AM_PC_MEMI_POST_INDEX,		///< Program Counter Memory Indirect - Postindexed
+	M68K_AM_PC_MEMI_PRE_INDEX,		///< Program Counter Memory Indirect - Preindexed
+
+	M68K_AM_ABSOLUTE_DATA_SHORT,	///< Absolute Data Addressing  - Short
+	M68K_AM_ABSOLUTE_DATA_LONG,		///< Absolute Data Addressing  - Long
+	M68K_AM_IMMEDIATE,              ///< Immediate value
+
+	M68K_AM_BRANCH_DISPLACEMENT,    ///< Address as displacement from (PC+2) used by branches
+} m68k_address_mode;
+
+/// Operand type for instruction's operands
+typedef enum m68k_op_type {
+	M68K_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+	M68K_OP_REG,         ///< = CS_OP_REG (Register operand).
+	M68K_OP_IMM,         ///< = CS_OP_IMM (Immediate operand).
+	M68K_OP_MEM,         ///< = CS_OP_MEM (Memory operand).
+	M68K_OP_FP_SINGLE,   ///< single precision Floating-Point operand
+	M68K_OP_FP_DOUBLE,   ///< double precision Floating-Point operand
+	M68K_OP_REG_BITS,    ///< Register bits move
+	M68K_OP_REG_PAIR,    ///< Register pair in the same op (upper 4 bits for first reg, lower for second)
+	M68K_OP_BR_DISP,     ///< Branch displacement
+} m68k_op_type;
+
+/// Instruction's operand referring to memory
+/// This is associated with M68K_OP_MEM operand type above
+typedef struct m68k_op_mem {
+	m68k_reg base_reg;      ///< base register (or M68K_REG_INVALID if irrelevant)
+	m68k_reg index_reg;     ///< index register (or M68K_REG_INVALID if irrelevant)
+	m68k_reg in_base_reg;   ///< indirect base register (or M68K_REG_INVALID if irrelevant)
+	uint32_t in_disp; 	    ///< indirect displacement
+	uint32_t out_disp;      ///< other displacement
+	int16_t disp;	        ///< displacement value
+	uint8_t scale;	        ///< scale for index register
+	uint8_t bitfield;       ///< set to true if the two values below should be used
+	uint8_t width;	        ///< used for bf* instructions
+	uint8_t offset;	        ///< used for bf* instructions
+	uint8_t index_size;     ///< 0 = w, 1 = l
+} m68k_op_mem;
+
+/// Operand type for instruction's operands
+typedef enum m68k_op_br_disp_size {
+	M68K_OP_BR_DISP_SIZE_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+	M68K_OP_BR_DISP_SIZE_BYTE = 1,    ///< signed 8-bit displacement
+	M68K_OP_BR_DISP_SIZE_WORD = 2,    ///< signed 16-bit displacement
+	M68K_OP_BR_DISP_SIZE_LONG = 4,    ///< signed 32-bit displacement
+} m68k_op_br_disp_size;
+
+typedef struct m68k_op_br_disp {
+	int32_t disp;	        ///< displacement value
+	uint8_t disp_size;		///< Size from m68k_op_br_disp_size type above
+} m68k_op_br_disp;
+
+/// Register pair in one operand.
+typedef struct cs_m68k_op_reg_pair {
+	m68k_reg reg_0;
+	m68k_reg reg_1;
+} cs_m68k_op_reg_pair;
+
+/// Instruction operand
+typedef struct cs_m68k_op {
+	union {
+		uint64_t imm;               ///< immediate value for IMM operand
+		double dimm; 		    ///< double imm
+		float simm; 		    ///< float imm
+		m68k_reg reg;		    ///< register value for REG operand
+		cs_m68k_op_reg_pair reg_pair; ///< register pair in one operand
+	};
+
+	m68k_op_mem mem; 	    ///< data when operand is targeting memory
+	m68k_op_br_disp br_disp; ///< data when operand is a branch displacement
+	uint32_t register_bits; ///< register bits for movem etc. (always in d0-d7, a0-a7, fp0 - fp7 order)
+	m68k_op_type type;
+	m68k_address_mode address_mode;	///< M68K addressing mode for this op
+} cs_m68k_op;
+
+/// Operation size of the CPU instructions
+typedef enum m68k_cpu_size {
+	M68K_CPU_SIZE_NONE = 0,		///< unsized or unspecified
+	M68K_CPU_SIZE_BYTE = 1,		///< 1 byte in size
+	M68K_CPU_SIZE_WORD = 2,		///< 2 bytes in size
+	M68K_CPU_SIZE_LONG = 4,		///< 4 bytes in size
+} m68k_cpu_size;
+
+/// Operation size of the FPU instructions (Notice that FPU instruction can also use CPU sizes if needed)
+typedef enum m68k_fpu_size {
+	M68K_FPU_SIZE_NONE = 0,		///< unsized like fsave/frestore
+	M68K_FPU_SIZE_SINGLE = 4,		///< 4 byte in size (single float)
+	M68K_FPU_SIZE_DOUBLE = 8,		///< 8 byte in size (double)
+	M68K_FPU_SIZE_EXTENDED = 12,	///< 12 byte in size (extended real format)
+} m68k_fpu_size;
+
+/// Type of size that is being used for the current instruction
+typedef enum m68k_size_type {
+	M68K_SIZE_TYPE_INVALID = 0,
+
+	M68K_SIZE_TYPE_CPU,
+	M68K_SIZE_TYPE_FPU,
+} m68k_size_type;
+
+/// Operation size of the current instruction (NOT the actually size of instruction)
+typedef struct m68k_op_size {
+	m68k_size_type type;
+	union {
+		m68k_cpu_size cpu_size;
+		m68k_fpu_size fpu_size;
+	};
+} m68k_op_size;
+
+/// The M68K instruction and it's operands
+typedef struct cs_m68k {
+	// Number of operands of this instruction or 0 when instruction has no operand.
+	cs_m68k_op operands[M68K_OPERAND_COUNT]; ///< operands for this instruction.
+	m68k_op_size op_size;	///< size of data operand works on in bytes (.b, .w, .l, etc)
+	uint8_t op_count; ///< number of operands for the instruction
+} cs_m68k;
+
+/// M68K instruction
+typedef enum m68k_insn {
+	M68K_INS_INVALID = 0,
+
+	M68K_INS_ABCD,
+	M68K_INS_ADD,
+	M68K_INS_ADDA,
+	M68K_INS_ADDI,
+	M68K_INS_ADDQ,
+	M68K_INS_ADDX,
+	M68K_INS_AND,
+	M68K_INS_ANDI,
+	M68K_INS_ASL,
+	M68K_INS_ASR,
+	M68K_INS_BHS,
+	M68K_INS_BLO,
+	M68K_INS_BHI,
+	M68K_INS_BLS,
+	M68K_INS_BCC,
+	M68K_INS_BCS,
+	M68K_INS_BNE,
+	M68K_INS_BEQ,
+	M68K_INS_BVC,
+	M68K_INS_BVS,
+	M68K_INS_BPL,
+	M68K_INS_BMI,
+	M68K_INS_BGE,
+	M68K_INS_BLT,
+	M68K_INS_BGT,
+	M68K_INS_BLE,
+	M68K_INS_BRA,
+	M68K_INS_BSR,
+	M68K_INS_BCHG,
+	M68K_INS_BCLR,
+	M68K_INS_BSET,
+	M68K_INS_BTST,
+	M68K_INS_BFCHG,
+	M68K_INS_BFCLR,
+	M68K_INS_BFEXTS,
+	M68K_INS_BFEXTU,
+	M68K_INS_BFFFO,
+	M68K_INS_BFINS,
+	M68K_INS_BFSET,
+	M68K_INS_BFTST,
+	M68K_INS_BKPT,
+	M68K_INS_CALLM,
+	M68K_INS_CAS,
+	M68K_INS_CAS2,
+	M68K_INS_CHK,
+	M68K_INS_CHK2,
+	M68K_INS_CLR,
+	M68K_INS_CMP,
+	M68K_INS_CMPA,
+	M68K_INS_CMPI,
+	M68K_INS_CMPM,
+	M68K_INS_CMP2,
+	M68K_INS_CINVL,
+	M68K_INS_CINVP,
+	M68K_INS_CINVA,
+	M68K_INS_CPUSHL,
+	M68K_INS_CPUSHP,
+	M68K_INS_CPUSHA,
+	M68K_INS_DBT,
+	M68K_INS_DBF,
+	M68K_INS_DBHI,
+	M68K_INS_DBLS,
+	M68K_INS_DBCC,
+	M68K_INS_DBCS,
+	M68K_INS_DBNE,
+	M68K_INS_DBEQ,
+	M68K_INS_DBVC,
+	M68K_INS_DBVS,
+	M68K_INS_DBPL,
+	M68K_INS_DBMI,
+	M68K_INS_DBGE,
+	M68K_INS_DBLT,
+	M68K_INS_DBGT,
+	M68K_INS_DBLE,
+	M68K_INS_DBRA,
+	M68K_INS_DIVS,
+	M68K_INS_DIVSL,
+	M68K_INS_DIVU,
+	M68K_INS_DIVUL,
+	M68K_INS_EOR,
+	M68K_INS_EORI,
+	M68K_INS_EXG,
+	M68K_INS_EXT,
+	M68K_INS_EXTB,
+	M68K_INS_FABS,
+	M68K_INS_FSABS,
+	M68K_INS_FDABS,
+	M68K_INS_FACOS,
+	M68K_INS_FADD,
+	M68K_INS_FSADD,
+	M68K_INS_FDADD,
+	M68K_INS_FASIN,
+	M68K_INS_FATAN,
+	M68K_INS_FATANH,
+	M68K_INS_FBF,
+	M68K_INS_FBEQ,
+	M68K_INS_FBOGT,
+	M68K_INS_FBOGE,
+	M68K_INS_FBOLT,
+	M68K_INS_FBOLE,
+	M68K_INS_FBOGL,
+	M68K_INS_FBOR,
+	M68K_INS_FBUN,
+	M68K_INS_FBUEQ,
+	M68K_INS_FBUGT,
+	M68K_INS_FBUGE,
+	M68K_INS_FBULT,
+	M68K_INS_FBULE,
+	M68K_INS_FBNE,
+	M68K_INS_FBT,
+	M68K_INS_FBSF,
+	M68K_INS_FBSEQ,
+	M68K_INS_FBGT,
+	M68K_INS_FBGE,
+	M68K_INS_FBLT,
+	M68K_INS_FBLE,
+	M68K_INS_FBGL,
+	M68K_INS_FBGLE,
+	M68K_INS_FBNGLE,
+	M68K_INS_FBNGL,
+	M68K_INS_FBNLE,
+	M68K_INS_FBNLT,
+	M68K_INS_FBNGE,
+	M68K_INS_FBNGT,
+	M68K_INS_FBSNE,
+	M68K_INS_FBST,
+	M68K_INS_FCMP,
+	M68K_INS_FCOS,
+	M68K_INS_FCOSH,
+	M68K_INS_FDBF,
+	M68K_INS_FDBEQ,
+	M68K_INS_FDBOGT,
+	M68K_INS_FDBOGE,
+	M68K_INS_FDBOLT,
+	M68K_INS_FDBOLE,
+	M68K_INS_FDBOGL,
+	M68K_INS_FDBOR,
+	M68K_INS_FDBUN,
+	M68K_INS_FDBUEQ,
+	M68K_INS_FDBUGT,
+	M68K_INS_FDBUGE,
+	M68K_INS_FDBULT,
+	M68K_INS_FDBULE,
+	M68K_INS_FDBNE,
+	M68K_INS_FDBT,
+	M68K_INS_FDBSF,
+	M68K_INS_FDBSEQ,
+	M68K_INS_FDBGT,
+	M68K_INS_FDBGE,
+	M68K_INS_FDBLT,
+	M68K_INS_FDBLE,
+	M68K_INS_FDBGL,
+	M68K_INS_FDBGLE,
+	M68K_INS_FDBNGLE,
+	M68K_INS_FDBNGL,
+	M68K_INS_FDBNLE,
+	M68K_INS_FDBNLT,
+	M68K_INS_FDBNGE,
+	M68K_INS_FDBNGT,
+	M68K_INS_FDBSNE,
+	M68K_INS_FDBST,
+	M68K_INS_FDIV,
+	M68K_INS_FSDIV,
+	M68K_INS_FDDIV,
+	M68K_INS_FETOX,
+	M68K_INS_FETOXM1,
+	M68K_INS_FGETEXP,
+	M68K_INS_FGETMAN,
+	M68K_INS_FINT,
+	M68K_INS_FINTRZ,
+	M68K_INS_FLOG10,
+	M68K_INS_FLOG2,
+	M68K_INS_FLOGN,
+	M68K_INS_FLOGNP1,
+	M68K_INS_FMOD,
+	M68K_INS_FMOVE,
+	M68K_INS_FSMOVE,
+	M68K_INS_FDMOVE,
+	M68K_INS_FMOVECR,
+	M68K_INS_FMOVEM,
+	M68K_INS_FMUL,
+	M68K_INS_FSMUL,
+	M68K_INS_FDMUL,
+	M68K_INS_FNEG,
+	M68K_INS_FSNEG,
+	M68K_INS_FDNEG,
+	M68K_INS_FNOP,
+	M68K_INS_FREM,
+	M68K_INS_FRESTORE,
+	M68K_INS_FSAVE,
+	M68K_INS_FSCALE,
+	M68K_INS_FSGLDIV,
+	M68K_INS_FSGLMUL,
+	M68K_INS_FSIN,
+	M68K_INS_FSINCOS,
+	M68K_INS_FSINH,
+	M68K_INS_FSQRT,
+	M68K_INS_FSSQRT,
+	M68K_INS_FDSQRT,
+	M68K_INS_FSF,
+	M68K_INS_FSBEQ,
+	M68K_INS_FSOGT,
+	M68K_INS_FSOGE,
+	M68K_INS_FSOLT,
+	M68K_INS_FSOLE,
+	M68K_INS_FSOGL,
+	M68K_INS_FSOR,
+	M68K_INS_FSUN,
+	M68K_INS_FSUEQ,
+	M68K_INS_FSUGT,
+	M68K_INS_FSUGE,
+	M68K_INS_FSULT,
+	M68K_INS_FSULE,
+	M68K_INS_FSNE,
+	M68K_INS_FST,
+	M68K_INS_FSSF,
+	M68K_INS_FSSEQ,
+	M68K_INS_FSGT,
+	M68K_INS_FSGE,
+	M68K_INS_FSLT,
+	M68K_INS_FSLE,
+	M68K_INS_FSGL,
+	M68K_INS_FSGLE,
+	M68K_INS_FSNGLE,
+	M68K_INS_FSNGL,
+	M68K_INS_FSNLE,
+	M68K_INS_FSNLT,
+	M68K_INS_FSNGE,
+	M68K_INS_FSNGT,
+	M68K_INS_FSSNE,
+	M68K_INS_FSST,
+	M68K_INS_FSUB,
+	M68K_INS_FSSUB,
+	M68K_INS_FDSUB,
+	M68K_INS_FTAN,
+	M68K_INS_FTANH,
+	M68K_INS_FTENTOX,
+	M68K_INS_FTRAPF,
+	M68K_INS_FTRAPEQ,
+	M68K_INS_FTRAPOGT,
+	M68K_INS_FTRAPOGE,
+	M68K_INS_FTRAPOLT,
+	M68K_INS_FTRAPOLE,
+	M68K_INS_FTRAPOGL,
+	M68K_INS_FTRAPOR,
+	M68K_INS_FTRAPUN,
+	M68K_INS_FTRAPUEQ,
+	M68K_INS_FTRAPUGT,
+	M68K_INS_FTRAPUGE,
+	M68K_INS_FTRAPULT,
+	M68K_INS_FTRAPULE,
+	M68K_INS_FTRAPNE,
+	M68K_INS_FTRAPT,
+	M68K_INS_FTRAPSF,
+	M68K_INS_FTRAPSEQ,
+	M68K_INS_FTRAPGT,
+	M68K_INS_FTRAPGE,
+	M68K_INS_FTRAPLT,
+	M68K_INS_FTRAPLE,
+	M68K_INS_FTRAPGL,
+	M68K_INS_FTRAPGLE,
+	M68K_INS_FTRAPNGLE,
+	M68K_INS_FTRAPNGL,
+	M68K_INS_FTRAPNLE,
+	M68K_INS_FTRAPNLT,
+	M68K_INS_FTRAPNGE,
+	M68K_INS_FTRAPNGT,
+	M68K_INS_FTRAPSNE,
+	M68K_INS_FTRAPST,
+	M68K_INS_FTST,
+	M68K_INS_FTWOTOX,
+	M68K_INS_HALT,
+	M68K_INS_ILLEGAL,
+	M68K_INS_JMP,
+	M68K_INS_JSR,
+	M68K_INS_LEA,
+	M68K_INS_LINK,
+	M68K_INS_LPSTOP,
+	M68K_INS_LSL,
+	M68K_INS_LSR,
+	M68K_INS_MOVE,
+	M68K_INS_MOVEA,
+	M68K_INS_MOVEC,
+	M68K_INS_MOVEM,
+	M68K_INS_MOVEP,
+	M68K_INS_MOVEQ,
+	M68K_INS_MOVES,
+	M68K_INS_MOVE16,
+	M68K_INS_MULS,
+	M68K_INS_MULU,
+	M68K_INS_NBCD,
+	M68K_INS_NEG,
+	M68K_INS_NEGX,
+	M68K_INS_NOP,
+	M68K_INS_NOT,
+	M68K_INS_OR,
+	M68K_INS_ORI,
+	M68K_INS_PACK,
+	M68K_INS_PEA,
+	M68K_INS_PFLUSH,
+	M68K_INS_PFLUSHA,
+	M68K_INS_PFLUSHAN,
+	M68K_INS_PFLUSHN,
+	M68K_INS_PLOADR,
+	M68K_INS_PLOADW,
+	M68K_INS_PLPAR,
+	M68K_INS_PLPAW,
+	M68K_INS_PMOVE,
+	M68K_INS_PMOVEFD,
+	M68K_INS_PTESTR,
+	M68K_INS_PTESTW,
+	M68K_INS_PULSE,
+	M68K_INS_REMS,
+	M68K_INS_REMU,
+	M68K_INS_RESET,
+	M68K_INS_ROL,
+	M68K_INS_ROR,
+	M68K_INS_ROXL,
+	M68K_INS_ROXR,
+	M68K_INS_RTD,
+	M68K_INS_RTE,
+	M68K_INS_RTM,
+	M68K_INS_RTR,
+	M68K_INS_RTS,
+	M68K_INS_SBCD,
+	M68K_INS_ST,
+	M68K_INS_SF,
+	M68K_INS_SHI,
+	M68K_INS_SLS,
+	M68K_INS_SCC,
+	M68K_INS_SHS,
+	M68K_INS_SCS,
+	M68K_INS_SLO,
+	M68K_INS_SNE,
+	M68K_INS_SEQ,
+	M68K_INS_SVC,
+	M68K_INS_SVS,
+	M68K_INS_SPL,
+	M68K_INS_SMI,
+	M68K_INS_SGE,
+	M68K_INS_SLT,
+	M68K_INS_SGT,
+	M68K_INS_SLE,
+	M68K_INS_STOP,
+	M68K_INS_SUB,
+	M68K_INS_SUBA,
+	M68K_INS_SUBI,
+	M68K_INS_SUBQ,
+	M68K_INS_SUBX,
+	M68K_INS_SWAP,
+	M68K_INS_TAS,
+	M68K_INS_TRAP,
+	M68K_INS_TRAPV,
+	M68K_INS_TRAPT,
+	M68K_INS_TRAPF,
+	M68K_INS_TRAPHI,
+	M68K_INS_TRAPLS,
+	M68K_INS_TRAPCC,
+	M68K_INS_TRAPHS,
+	M68K_INS_TRAPCS,
+	M68K_INS_TRAPLO,
+	M68K_INS_TRAPNE,
+	M68K_INS_TRAPEQ,
+	M68K_INS_TRAPVC,
+	M68K_INS_TRAPVS,
+	M68K_INS_TRAPPL,
+	M68K_INS_TRAPMI,
+	M68K_INS_TRAPGE,
+	M68K_INS_TRAPLT,
+	M68K_INS_TRAPGT,
+	M68K_INS_TRAPLE,
+	M68K_INS_TST,
+	M68K_INS_UNLK,
+	M68K_INS_UNPK,
+	M68K_INS_ENDING,   // <-- mark the end of the list of instructions
+} m68k_insn;
+
+/// Group of M68K instructions
+typedef enum m68k_group_type {
+	M68K_GRP_INVALID = 0,  ///< CS_GRUP_INVALID
+	M68K_GRP_JUMP,  ///< = CS_GRP_JUMP
+	M68K_GRP_RET = 3,  ///< = CS_GRP_RET
+	M68K_GRP_IRET = 5, ///< = CS_GRP_IRET
+	M68K_GRP_BRANCH_RELATIVE = 7, ///< = CS_GRP_BRANCH_RELATIVE
+
+	M68K_GRP_ENDING,// <-- mark the end of the list of groups
+} m68k_group_type;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

.tools/python-revlibs/capstone/include/capstone/mips.h

@@ -0,0 +1,956 @@
+#ifndef CAPSTONE_MIPS_H
+#define CAPSTONE_MIPS_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+// GCC MIPS toolchain has a default macro called "mips" which breaks
+// compilation
+#undef mips
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// Operand type for instruction's operands
+typedef enum mips_op_type {
+	MIPS_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+	MIPS_OP_REG, ///< = CS_OP_REG (Register operand).
+	MIPS_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	MIPS_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+} mips_op_type;
+
+/// MIPS registers
+typedef enum mips_reg {
+	MIPS_REG_INVALID = 0,
+	// General purpose registers
+	MIPS_REG_PC,
+
+	MIPS_REG_0,
+	MIPS_REG_1,
+	MIPS_REG_2,
+	MIPS_REG_3,
+	MIPS_REG_4,
+	MIPS_REG_5,
+	MIPS_REG_6,
+	MIPS_REG_7,
+	MIPS_REG_8,
+	MIPS_REG_9,
+	MIPS_REG_10,
+	MIPS_REG_11,
+	MIPS_REG_12,
+	MIPS_REG_13,
+	MIPS_REG_14,
+	MIPS_REG_15,
+	MIPS_REG_16,
+	MIPS_REG_17,
+	MIPS_REG_18,
+	MIPS_REG_19,
+	MIPS_REG_20,
+	MIPS_REG_21,
+	MIPS_REG_22,
+	MIPS_REG_23,
+	MIPS_REG_24,
+	MIPS_REG_25,
+	MIPS_REG_26,
+	MIPS_REG_27,
+	MIPS_REG_28,
+	MIPS_REG_29,
+	MIPS_REG_30,
+	MIPS_REG_31,
+
+	// DSP registers
+	MIPS_REG_DSPCCOND,
+	MIPS_REG_DSPCARRY,
+	MIPS_REG_DSPEFI,
+	MIPS_REG_DSPOUTFLAG,
+	MIPS_REG_DSPOUTFLAG16_19,
+	MIPS_REG_DSPOUTFLAG20,
+	MIPS_REG_DSPOUTFLAG21,
+	MIPS_REG_DSPOUTFLAG22,
+	MIPS_REG_DSPOUTFLAG23,
+	MIPS_REG_DSPPOS,
+	MIPS_REG_DSPSCOUNT,
+
+	// ACC registers
+	MIPS_REG_AC0,
+	MIPS_REG_AC1,
+	MIPS_REG_AC2,
+	MIPS_REG_AC3,
+
+	// COP registers
+	MIPS_REG_CC0,
+	MIPS_REG_CC1,
+	MIPS_REG_CC2,
+	MIPS_REG_CC3,
+	MIPS_REG_CC4,
+	MIPS_REG_CC5,
+	MIPS_REG_CC6,
+	MIPS_REG_CC7,
+
+	// FPU registers
+	MIPS_REG_F0,
+	MIPS_REG_F1,
+	MIPS_REG_F2,
+	MIPS_REG_F3,
+	MIPS_REG_F4,
+	MIPS_REG_F5,
+	MIPS_REG_F6,
+	MIPS_REG_F7,
+	MIPS_REG_F8,
+	MIPS_REG_F9,
+	MIPS_REG_F10,
+	MIPS_REG_F11,
+	MIPS_REG_F12,
+	MIPS_REG_F13,
+	MIPS_REG_F14,
+	MIPS_REG_F15,
+	MIPS_REG_F16,
+	MIPS_REG_F17,
+	MIPS_REG_F18,
+	MIPS_REG_F19,
+	MIPS_REG_F20,
+	MIPS_REG_F21,
+	MIPS_REG_F22,
+	MIPS_REG_F23,
+	MIPS_REG_F24,
+	MIPS_REG_F25,
+	MIPS_REG_F26,
+	MIPS_REG_F27,
+	MIPS_REG_F28,
+	MIPS_REG_F29,
+	MIPS_REG_F30,
+	MIPS_REG_F31,
+
+	MIPS_REG_FCC0,
+	MIPS_REG_FCC1,
+	MIPS_REG_FCC2,
+	MIPS_REG_FCC3,
+	MIPS_REG_FCC4,
+	MIPS_REG_FCC5,
+	MIPS_REG_FCC6,
+	MIPS_REG_FCC7,
+
+	// AFPR128
+	MIPS_REG_W0,
+	MIPS_REG_W1,
+	MIPS_REG_W2,
+	MIPS_REG_W3,
+	MIPS_REG_W4,
+	MIPS_REG_W5,
+	MIPS_REG_W6,
+	MIPS_REG_W7,
+	MIPS_REG_W8,
+	MIPS_REG_W9,
+	MIPS_REG_W10,
+	MIPS_REG_W11,
+	MIPS_REG_W12,
+	MIPS_REG_W13,
+	MIPS_REG_W14,
+	MIPS_REG_W15,
+	MIPS_REG_W16,
+	MIPS_REG_W17,
+	MIPS_REG_W18,
+	MIPS_REG_W19,
+	MIPS_REG_W20,
+	MIPS_REG_W21,
+	MIPS_REG_W22,
+	MIPS_REG_W23,
+	MIPS_REG_W24,
+	MIPS_REG_W25,
+	MIPS_REG_W26,
+	MIPS_REG_W27,
+	MIPS_REG_W28,
+	MIPS_REG_W29,
+	MIPS_REG_W30,
+	MIPS_REG_W31,
+
+	MIPS_REG_HI,
+	MIPS_REG_LO,
+
+	MIPS_REG_P0,
+	MIPS_REG_P1,
+	MIPS_REG_P2,
+
+	MIPS_REG_MPL0,
+	MIPS_REG_MPL1,
+	MIPS_REG_MPL2,
+
+	MIPS_REG_ENDING,	// <-- mark the end of the list or registers
+
+	// alias registers
+	MIPS_REG_ZERO = MIPS_REG_0,
+	MIPS_REG_AT = MIPS_REG_1,
+	MIPS_REG_V0 = MIPS_REG_2,
+	MIPS_REG_V1 = MIPS_REG_3,
+	MIPS_REG_A0 = MIPS_REG_4,
+	MIPS_REG_A1 = MIPS_REG_5,
+	MIPS_REG_A2 = MIPS_REG_6,
+	MIPS_REG_A3 = MIPS_REG_7,
+	MIPS_REG_T0 = MIPS_REG_8,
+	MIPS_REG_T1 = MIPS_REG_9,
+	MIPS_REG_T2 = MIPS_REG_10,
+	MIPS_REG_T3 = MIPS_REG_11,
+	MIPS_REG_T4 = MIPS_REG_12,
+	MIPS_REG_T5 = MIPS_REG_13,
+	MIPS_REG_T6 = MIPS_REG_14,
+	MIPS_REG_T7 = MIPS_REG_15,
+	MIPS_REG_S0 = MIPS_REG_16,
+	MIPS_REG_S1 = MIPS_REG_17,
+	MIPS_REG_S2 = MIPS_REG_18,
+	MIPS_REG_S3 = MIPS_REG_19,
+	MIPS_REG_S4 = MIPS_REG_20,
+	MIPS_REG_S5 = MIPS_REG_21,
+	MIPS_REG_S6 = MIPS_REG_22,
+	MIPS_REG_S7 = MIPS_REG_23,
+	MIPS_REG_T8 = MIPS_REG_24,
+	MIPS_REG_T9 = MIPS_REG_25,
+	MIPS_REG_K0 = MIPS_REG_26,
+	MIPS_REG_K1 = MIPS_REG_27,
+	MIPS_REG_GP = MIPS_REG_28,
+	MIPS_REG_SP = MIPS_REG_29,
+	MIPS_REG_FP = MIPS_REG_30, MIPS_REG_S8 = MIPS_REG_30,
+	MIPS_REG_RA = MIPS_REG_31,
+
+	MIPS_REG_HI0 = MIPS_REG_AC0,
+	MIPS_REG_HI1 = MIPS_REG_AC1,
+	MIPS_REG_HI2 = MIPS_REG_AC2,
+	MIPS_REG_HI3 = MIPS_REG_AC3,
+
+	MIPS_REG_LO0 = MIPS_REG_HI0,
+	MIPS_REG_LO1 = MIPS_REG_HI1,
+	MIPS_REG_LO2 = MIPS_REG_HI2,
+	MIPS_REG_LO3 = MIPS_REG_HI3,
+} mips_reg;
+
+/// Instruction's operand referring to memory
+/// This is associated with MIPS_OP_MEM operand type above
+typedef struct mips_op_mem {
+	mips_reg base;	///< base register
+	int64_t disp;	///< displacement/offset value
+} mips_op_mem;
+
+/// Instruction operand
+typedef struct cs_mips_op {
+	mips_op_type type;	///< operand type
+	union {
+		mips_reg reg;		///< register id for REG operand
+		int64_t imm;		///< immediate value for IMM operand
+		mips_op_mem mem;	///< base/index/scale/disp value for MEM operand
+	};
+} cs_mips_op;
+
+/// Instruction structure
+typedef struct cs_mips {
+	/// Number of operands of this instruction,
+	/// or 0 when instruction has no operand.
+	uint8_t op_count;
+	cs_mips_op operands[10]; ///< operands for this instruction.
+} cs_mips;
+
+/// MIPS instruction
+typedef enum mips_insn {
+	MIPS_INS_INVALID = 0,
+
+	MIPS_INS_ABSQ_S,
+	MIPS_INS_ADD,
+	MIPS_INS_ADDIUPC,
+	MIPS_INS_ADDIUR1SP,
+	MIPS_INS_ADDIUR2,
+	MIPS_INS_ADDIUS5,
+	MIPS_INS_ADDIUSP,
+	MIPS_INS_ADDQH,
+	MIPS_INS_ADDQH_R,
+	MIPS_INS_ADDQ,
+	MIPS_INS_ADDQ_S,
+	MIPS_INS_ADDSC,
+	MIPS_INS_ADDS_A,
+	MIPS_INS_ADDS_S,
+	MIPS_INS_ADDS_U,
+	MIPS_INS_ADDU16,
+	MIPS_INS_ADDUH,
+	MIPS_INS_ADDUH_R,
+	MIPS_INS_ADDU,
+	MIPS_INS_ADDU_S,
+	MIPS_INS_ADDVI,
+	MIPS_INS_ADDV,
+	MIPS_INS_ADDWC,
+	MIPS_INS_ADD_A,
+	MIPS_INS_ADDI,
+	MIPS_INS_ADDIU,
+	MIPS_INS_ALIGN,
+	MIPS_INS_ALUIPC,
+	MIPS_INS_AND,
+	MIPS_INS_AND16,
+	MIPS_INS_ANDI16,
+	MIPS_INS_ANDI,
+	MIPS_INS_APPEND,
+	MIPS_INS_ASUB_S,
+	MIPS_INS_ASUB_U,
+	MIPS_INS_AUI,
+	MIPS_INS_AUIPC,
+	MIPS_INS_AVER_S,
+	MIPS_INS_AVER_U,
+	MIPS_INS_AVE_S,
+	MIPS_INS_AVE_U,
+	MIPS_INS_B16,
+	MIPS_INS_BADDU,
+	MIPS_INS_BAL,
+	MIPS_INS_BALC,
+	MIPS_INS_BALIGN,
+	MIPS_INS_BBIT0,
+	MIPS_INS_BBIT032,
+	MIPS_INS_BBIT1,
+	MIPS_INS_BBIT132,
+	MIPS_INS_BC,
+	MIPS_INS_BC0F,
+	MIPS_INS_BC0FL,
+	MIPS_INS_BC0T,
+	MIPS_INS_BC0TL,
+	MIPS_INS_BC1EQZ,
+	MIPS_INS_BC1F,
+	MIPS_INS_BC1FL,
+	MIPS_INS_BC1NEZ,
+	MIPS_INS_BC1T,
+	MIPS_INS_BC1TL,
+	MIPS_INS_BC2EQZ,
+	MIPS_INS_BC2F,
+	MIPS_INS_BC2FL,
+	MIPS_INS_BC2NEZ,
+	MIPS_INS_BC2T,
+	MIPS_INS_BC2TL,
+	MIPS_INS_BC3F,
+	MIPS_INS_BC3FL,
+	MIPS_INS_BC3T,
+	MIPS_INS_BC3TL,
+	MIPS_INS_BCLRI,
+	MIPS_INS_BCLR,
+	MIPS_INS_BEQ,
+	MIPS_INS_BEQC,
+	MIPS_INS_BEQL,
+	MIPS_INS_BEQZ16,
+	MIPS_INS_BEQZALC,
+	MIPS_INS_BEQZC,
+	MIPS_INS_BGEC,
+	MIPS_INS_BGEUC,
+	MIPS_INS_BGEZ,
+	MIPS_INS_BGEZAL,
+	MIPS_INS_BGEZALC,
+	MIPS_INS_BGEZALL,
+	MIPS_INS_BGEZALS,
+	MIPS_INS_BGEZC,
+	MIPS_INS_BGEZL,
+	MIPS_INS_BGTZ,
+	MIPS_INS_BGTZALC,
+	MIPS_INS_BGTZC,
+	MIPS_INS_BGTZL,
+	MIPS_INS_BINSLI,
+	MIPS_INS_BINSL,
+	MIPS_INS_BINSRI,
+	MIPS_INS_BINSR,
+	MIPS_INS_BITREV,
+	MIPS_INS_BITSWAP,
+	MIPS_INS_BLEZ,
+	MIPS_INS_BLEZALC,
+	MIPS_INS_BLEZC,
+	MIPS_INS_BLEZL,
+	MIPS_INS_BLTC,
+	MIPS_INS_BLTUC,
+	MIPS_INS_BLTZ,
+	MIPS_INS_BLTZAL,
+	MIPS_INS_BLTZALC,
+	MIPS_INS_BLTZALL,
+	MIPS_INS_BLTZALS,
+	MIPS_INS_BLTZC,
+	MIPS_INS_BLTZL,
+	MIPS_INS_BMNZI,
+	MIPS_INS_BMNZ,
+	MIPS_INS_BMZI,
+	MIPS_INS_BMZ,
+	MIPS_INS_BNE,
+	MIPS_INS_BNEC,
+	MIPS_INS_BNEGI,
+	MIPS_INS_BNEG,
+	MIPS_INS_BNEL,
+	MIPS_INS_BNEZ16,
+	MIPS_INS_BNEZALC,
+	MIPS_INS_BNEZC,
+	MIPS_INS_BNVC,
+	MIPS_INS_BNZ,
+	MIPS_INS_BOVC,
+	MIPS_INS_BPOSGE32,
+	MIPS_INS_BREAK,
+	MIPS_INS_BREAK16,
+	MIPS_INS_BSELI,
+	MIPS_INS_BSEL,
+	MIPS_INS_BSETI,
+	MIPS_INS_BSET,
+	MIPS_INS_BZ,
+	MIPS_INS_BEQZ,
+	MIPS_INS_B,
+	MIPS_INS_BNEZ,
+	MIPS_INS_BTEQZ,
+	MIPS_INS_BTNEZ,
+	MIPS_INS_CACHE,
+	MIPS_INS_CEIL,
+	MIPS_INS_CEQI,
+	MIPS_INS_CEQ,
+	MIPS_INS_CFC1,
+	MIPS_INS_CFCMSA,
+	MIPS_INS_CINS,
+	MIPS_INS_CINS32,
+	MIPS_INS_CLASS,
+	MIPS_INS_CLEI_S,
+	MIPS_INS_CLEI_U,
+	MIPS_INS_CLE_S,
+	MIPS_INS_CLE_U,
+	MIPS_INS_CLO,
+	MIPS_INS_CLTI_S,
+	MIPS_INS_CLTI_U,
+	MIPS_INS_CLT_S,
+	MIPS_INS_CLT_U,
+	MIPS_INS_CLZ,
+	MIPS_INS_CMPGDU,
+	MIPS_INS_CMPGU,
+	MIPS_INS_CMPU,
+	MIPS_INS_CMP,
+	MIPS_INS_COPY_S,
+	MIPS_INS_COPY_U,
+	MIPS_INS_CTC1,
+	MIPS_INS_CTCMSA,
+	MIPS_INS_CVT,
+	MIPS_INS_C,
+	MIPS_INS_CMPI,
+	MIPS_INS_DADD,
+	MIPS_INS_DADDI,
+	MIPS_INS_DADDIU,
+	MIPS_INS_DADDU,
+	MIPS_INS_DAHI,
+	MIPS_INS_DALIGN,
+	MIPS_INS_DATI,
+	MIPS_INS_DAUI,
+	MIPS_INS_DBITSWAP,
+	MIPS_INS_DCLO,
+	MIPS_INS_DCLZ,
+	MIPS_INS_DDIV,
+	MIPS_INS_DDIVU,
+	MIPS_INS_DERET,
+	MIPS_INS_DEXT,
+	MIPS_INS_DEXTM,
+	MIPS_INS_DEXTU,
+	MIPS_INS_DI,
+	MIPS_INS_DINS,
+	MIPS_INS_DINSM,
+	MIPS_INS_DINSU,
+	MIPS_INS_DIV,
+	MIPS_INS_DIVU,
+	MIPS_INS_DIV_S,
+	MIPS_INS_DIV_U,
+	MIPS_INS_DLSA,
+	MIPS_INS_DMFC0,
+	MIPS_INS_DMFC1,
+	MIPS_INS_DMFC2,
+	MIPS_INS_DMOD,
+	MIPS_INS_DMODU,
+	MIPS_INS_DMTC0,
+	MIPS_INS_DMTC1,
+	MIPS_INS_DMTC2,
+	MIPS_INS_DMUH,
+	MIPS_INS_DMUHU,
+	MIPS_INS_DMUL,
+	MIPS_INS_DMULT,
+	MIPS_INS_DMULTU,
+	MIPS_INS_DMULU,
+	MIPS_INS_DOTP_S,
+	MIPS_INS_DOTP_U,
+	MIPS_INS_DPADD_S,
+	MIPS_INS_DPADD_U,
+	MIPS_INS_DPAQX_SA,
+	MIPS_INS_DPAQX_S,
+	MIPS_INS_DPAQ_SA,
+	MIPS_INS_DPAQ_S,
+	MIPS_INS_DPAU,
+	MIPS_INS_DPAX,
+	MIPS_INS_DPA,
+	MIPS_INS_DPOP,
+	MIPS_INS_DPSQX_SA,
+	MIPS_INS_DPSQX_S,
+	MIPS_INS_DPSQ_SA,
+	MIPS_INS_DPSQ_S,
+	MIPS_INS_DPSUB_S,
+	MIPS_INS_DPSUB_U,
+	MIPS_INS_DPSU,
+	MIPS_INS_DPSX,
+	MIPS_INS_DPS,
+	MIPS_INS_DROTR,
+	MIPS_INS_DROTR32,
+	MIPS_INS_DROTRV,
+	MIPS_INS_DSBH,
+	MIPS_INS_DSHD,
+	MIPS_INS_DSLL,
+	MIPS_INS_DSLL32,
+	MIPS_INS_DSLLV,
+	MIPS_INS_DSRA,
+	MIPS_INS_DSRA32,
+	MIPS_INS_DSRAV,
+	MIPS_INS_DSRL,
+	MIPS_INS_DSRL32,
+	MIPS_INS_DSRLV,
+	MIPS_INS_DSUB,
+	MIPS_INS_DSUBU,
+	MIPS_INS_EHB,
+	MIPS_INS_EI,
+	MIPS_INS_ERET,
+	MIPS_INS_EXT,
+	MIPS_INS_EXTP,
+	MIPS_INS_EXTPDP,
+	MIPS_INS_EXTPDPV,
+	MIPS_INS_EXTPV,
+	MIPS_INS_EXTRV_RS,
+	MIPS_INS_EXTRV_R,
+	MIPS_INS_EXTRV_S,
+	MIPS_INS_EXTRV,
+	MIPS_INS_EXTR_RS,
+	MIPS_INS_EXTR_R,
+	MIPS_INS_EXTR_S,
+	MIPS_INS_EXTR,
+	MIPS_INS_EXTS,
+	MIPS_INS_EXTS32,
+	MIPS_INS_ABS,
+	MIPS_INS_FADD,
+	MIPS_INS_FCAF,
+	MIPS_INS_FCEQ,
+	MIPS_INS_FCLASS,
+	MIPS_INS_FCLE,
+	MIPS_INS_FCLT,
+	MIPS_INS_FCNE,
+	MIPS_INS_FCOR,
+	MIPS_INS_FCUEQ,
+	MIPS_INS_FCULE,
+	MIPS_INS_FCULT,
+	MIPS_INS_FCUNE,
+	MIPS_INS_FCUN,
+	MIPS_INS_FDIV,
+	MIPS_INS_FEXDO,
+	MIPS_INS_FEXP2,
+	MIPS_INS_FEXUPL,
+	MIPS_INS_FEXUPR,
+	MIPS_INS_FFINT_S,
+	MIPS_INS_FFINT_U,
+	MIPS_INS_FFQL,
+	MIPS_INS_FFQR,
+	MIPS_INS_FILL,
+	MIPS_INS_FLOG2,
+	MIPS_INS_FLOOR,
+	MIPS_INS_FMADD,
+	MIPS_INS_FMAX_A,
+	MIPS_INS_FMAX,
+	MIPS_INS_FMIN_A,
+	MIPS_INS_FMIN,
+	MIPS_INS_MOV,
+	MIPS_INS_FMSUB,
+	MIPS_INS_FMUL,
+	MIPS_INS_MUL,
+	MIPS_INS_NEG,
+	MIPS_INS_FRCP,
+	MIPS_INS_FRINT,
+	MIPS_INS_FRSQRT,
+	MIPS_INS_FSAF,
+	MIPS_INS_FSEQ,
+	MIPS_INS_FSLE,
+	MIPS_INS_FSLT,
+	MIPS_INS_FSNE,
+	MIPS_INS_FSOR,
+	MIPS_INS_FSQRT,
+	MIPS_INS_SQRT,
+	MIPS_INS_FSUB,
+	MIPS_INS_SUB,
+	MIPS_INS_FSUEQ,
+	MIPS_INS_FSULE,
+	MIPS_INS_FSULT,
+	MIPS_INS_FSUNE,
+	MIPS_INS_FSUN,
+	MIPS_INS_FTINT_S,
+	MIPS_INS_FTINT_U,
+	MIPS_INS_FTQ,
+	MIPS_INS_FTRUNC_S,
+	MIPS_INS_FTRUNC_U,
+	MIPS_INS_HADD_S,
+	MIPS_INS_HADD_U,
+	MIPS_INS_HSUB_S,
+	MIPS_INS_HSUB_U,
+	MIPS_INS_ILVEV,
+	MIPS_INS_ILVL,
+	MIPS_INS_ILVOD,
+	MIPS_INS_ILVR,
+	MIPS_INS_INS,
+	MIPS_INS_INSERT,
+	MIPS_INS_INSV,
+	MIPS_INS_INSVE,
+	MIPS_INS_J,
+	MIPS_INS_JAL,
+	MIPS_INS_JALR,
+	MIPS_INS_JALRS16,
+	MIPS_INS_JALRS,
+	MIPS_INS_JALS,
+	MIPS_INS_JALX,
+	MIPS_INS_JIALC,
+	MIPS_INS_JIC,
+	MIPS_INS_JR,
+	MIPS_INS_JR16,
+	MIPS_INS_JRADDIUSP,
+	MIPS_INS_JRC,
+	MIPS_INS_JALRC,
+	MIPS_INS_LB,
+	MIPS_INS_LBU16,
+	MIPS_INS_LBUX,
+	MIPS_INS_LBU,
+	MIPS_INS_LD,
+	MIPS_INS_LDC1,
+	MIPS_INS_LDC2,
+	MIPS_INS_LDC3,
+	MIPS_INS_LDI,
+	MIPS_INS_LDL,
+	MIPS_INS_LDPC,
+	MIPS_INS_LDR,
+	MIPS_INS_LDXC1,
+	MIPS_INS_LH,
+	MIPS_INS_LHU16,
+	MIPS_INS_LHX,
+	MIPS_INS_LHU,
+	MIPS_INS_LI16,
+	MIPS_INS_LL,
+	MIPS_INS_LLD,
+	MIPS_INS_LSA,
+	MIPS_INS_LUXC1,
+	MIPS_INS_LUI,
+	MIPS_INS_LW,
+	MIPS_INS_LW16,
+	MIPS_INS_LWC1,
+	MIPS_INS_LWC2,
+	MIPS_INS_LWC3,
+	MIPS_INS_LWL,
+	MIPS_INS_LWM16,
+	MIPS_INS_LWM32,
+	MIPS_INS_LWPC,
+	MIPS_INS_LWP,
+	MIPS_INS_LWR,
+	MIPS_INS_LWUPC,
+	MIPS_INS_LWU,
+	MIPS_INS_LWX,
+	MIPS_INS_LWXC1,
+	MIPS_INS_LWXS,
+	MIPS_INS_LI,
+	MIPS_INS_MADD,
+	MIPS_INS_MADDF,
+	MIPS_INS_MADDR_Q,
+	MIPS_INS_MADDU,
+	MIPS_INS_MADDV,
+	MIPS_INS_MADD_Q,
+	MIPS_INS_MAQ_SA,
+	MIPS_INS_MAQ_S,
+	MIPS_INS_MAXA,
+	MIPS_INS_MAXI_S,
+	MIPS_INS_MAXI_U,
+	MIPS_INS_MAX_A,
+	MIPS_INS_MAX,
+	MIPS_INS_MAX_S,
+	MIPS_INS_MAX_U,
+	MIPS_INS_MFC0,
+	MIPS_INS_MFC1,
+	MIPS_INS_MFC2,
+	MIPS_INS_MFHC1,
+	MIPS_INS_MFHI,
+	MIPS_INS_MFLO,
+	MIPS_INS_MINA,
+	MIPS_INS_MINI_S,
+	MIPS_INS_MINI_U,
+	MIPS_INS_MIN_A,
+	MIPS_INS_MIN,
+	MIPS_INS_MIN_S,
+	MIPS_INS_MIN_U,
+	MIPS_INS_MOD,
+	MIPS_INS_MODSUB,
+	MIPS_INS_MODU,
+	MIPS_INS_MOD_S,
+	MIPS_INS_MOD_U,
+	MIPS_INS_MOVE,
+	MIPS_INS_MOVEP,
+	MIPS_INS_MOVF,
+	MIPS_INS_MOVN,
+	MIPS_INS_MOVT,
+	MIPS_INS_MOVZ,
+	MIPS_INS_MSUB,
+	MIPS_INS_MSUBF,
+	MIPS_INS_MSUBR_Q,
+	MIPS_INS_MSUBU,
+	MIPS_INS_MSUBV,
+	MIPS_INS_MSUB_Q,
+	MIPS_INS_MTC0,
+	MIPS_INS_MTC1,
+	MIPS_INS_MTC2,
+	MIPS_INS_MTHC1,
+	MIPS_INS_MTHI,
+	MIPS_INS_MTHLIP,
+	MIPS_INS_MTLO,
+	MIPS_INS_MTM0,
+	MIPS_INS_MTM1,
+	MIPS_INS_MTM2,
+	MIPS_INS_MTP0,
+	MIPS_INS_MTP1,
+	MIPS_INS_MTP2,
+	MIPS_INS_MUH,
+	MIPS_INS_MUHU,
+	MIPS_INS_MULEQ_S,
+	MIPS_INS_MULEU_S,
+	MIPS_INS_MULQ_RS,
+	MIPS_INS_MULQ_S,
+	MIPS_INS_MULR_Q,
+	MIPS_INS_MULSAQ_S,
+	MIPS_INS_MULSA,
+	MIPS_INS_MULT,
+	MIPS_INS_MULTU,
+	MIPS_INS_MULU,
+	MIPS_INS_MULV,
+	MIPS_INS_MUL_Q,
+	MIPS_INS_MUL_S,
+	MIPS_INS_NLOC,
+	MIPS_INS_NLZC,
+	MIPS_INS_NMADD,
+	MIPS_INS_NMSUB,
+	MIPS_INS_NOR,
+	MIPS_INS_NORI,
+	MIPS_INS_NOT16,
+	MIPS_INS_NOT,
+	MIPS_INS_OR,
+	MIPS_INS_OR16,
+	MIPS_INS_ORI,
+	MIPS_INS_PACKRL,
+	MIPS_INS_PAUSE,
+	MIPS_INS_PCKEV,
+	MIPS_INS_PCKOD,
+	MIPS_INS_PCNT,
+	MIPS_INS_PICK,
+	MIPS_INS_POP,
+	MIPS_INS_PRECEQU,
+	MIPS_INS_PRECEQ,
+	MIPS_INS_PRECEU,
+	MIPS_INS_PRECRQU_S,
+	MIPS_INS_PRECRQ,
+	MIPS_INS_PRECRQ_RS,
+	MIPS_INS_PRECR,
+	MIPS_INS_PRECR_SRA,
+	MIPS_INS_PRECR_SRA_R,
+	MIPS_INS_PREF,
+	MIPS_INS_PREPEND,
+	MIPS_INS_RADDU,
+	MIPS_INS_RDDSP,
+	MIPS_INS_RDHWR,
+	MIPS_INS_REPLV,
+	MIPS_INS_REPL,
+	MIPS_INS_RINT,
+	MIPS_INS_ROTR,
+	MIPS_INS_ROTRV,
+	MIPS_INS_ROUND,
+	MIPS_INS_SAT_S,
+	MIPS_INS_SAT_U,
+	MIPS_INS_SB,
+	MIPS_INS_SB16,
+	MIPS_INS_SC,
+	MIPS_INS_SCD,
+	MIPS_INS_SD,
+	MIPS_INS_SDBBP,
+	MIPS_INS_SDBBP16,
+	MIPS_INS_SDC1,
+	MIPS_INS_SDC2,
+	MIPS_INS_SDC3,
+	MIPS_INS_SDL,
+	MIPS_INS_SDR,
+	MIPS_INS_SDXC1,
+	MIPS_INS_SEB,
+	MIPS_INS_SEH,
+	MIPS_INS_SELEQZ,
+	MIPS_INS_SELNEZ,
+	MIPS_INS_SEL,
+	MIPS_INS_SEQ,
+	MIPS_INS_SEQI,
+	MIPS_INS_SH,
+	MIPS_INS_SH16,
+	MIPS_INS_SHF,
+	MIPS_INS_SHILO,
+	MIPS_INS_SHILOV,
+	MIPS_INS_SHLLV,
+	MIPS_INS_SHLLV_S,
+	MIPS_INS_SHLL,
+	MIPS_INS_SHLL_S,
+	MIPS_INS_SHRAV,
+	MIPS_INS_SHRAV_R,
+	MIPS_INS_SHRA,
+	MIPS_INS_SHRA_R,
+	MIPS_INS_SHRLV,
+	MIPS_INS_SHRL,
+	MIPS_INS_SLDI,
+	MIPS_INS_SLD,
+	MIPS_INS_SLL,
+	MIPS_INS_SLL16,
+	MIPS_INS_SLLI,
+	MIPS_INS_SLLV,
+	MIPS_INS_SLT,
+	MIPS_INS_SLTI,
+	MIPS_INS_SLTIU,
+	MIPS_INS_SLTU,
+	MIPS_INS_SNE,
+	MIPS_INS_SNEI,
+	MIPS_INS_SPLATI,
+	MIPS_INS_SPLAT,
+	MIPS_INS_SRA,
+	MIPS_INS_SRAI,
+	MIPS_INS_SRARI,
+	MIPS_INS_SRAR,
+	MIPS_INS_SRAV,
+	MIPS_INS_SRL,
+	MIPS_INS_SRL16,
+	MIPS_INS_SRLI,
+	MIPS_INS_SRLRI,
+	MIPS_INS_SRLR,
+	MIPS_INS_SRLV,
+	MIPS_INS_SSNOP,
+	MIPS_INS_ST,
+	MIPS_INS_SUBQH,
+	MIPS_INS_SUBQH_R,
+	MIPS_INS_SUBQ,
+	MIPS_INS_SUBQ_S,
+	MIPS_INS_SUBSUS_U,
+	MIPS_INS_SUBSUU_S,
+	MIPS_INS_SUBS_S,
+	MIPS_INS_SUBS_U,
+	MIPS_INS_SUBU16,
+	MIPS_INS_SUBUH,
+	MIPS_INS_SUBUH_R,
+	MIPS_INS_SUBU,
+	MIPS_INS_SUBU_S,
+	MIPS_INS_SUBVI,
+	MIPS_INS_SUBV,
+	MIPS_INS_SUXC1,
+	MIPS_INS_SW,
+	MIPS_INS_SW16,
+	MIPS_INS_SWC1,
+	MIPS_INS_SWC2,
+	MIPS_INS_SWC3,
+	MIPS_INS_SWL,
+	MIPS_INS_SWM16,
+	MIPS_INS_SWM32,
+	MIPS_INS_SWP,
+	MIPS_INS_SWR,
+	MIPS_INS_SWXC1,
+	MIPS_INS_SYNC,
+	MIPS_INS_SYNCI,
+	MIPS_INS_SYSCALL,
+	MIPS_INS_TEQ,
+	MIPS_INS_TEQI,
+	MIPS_INS_TGE,
+	MIPS_INS_TGEI,
+	MIPS_INS_TGEIU,
+	MIPS_INS_TGEU,
+	MIPS_INS_TLBP,
+	MIPS_INS_TLBR,
+	MIPS_INS_TLBWI,
+	MIPS_INS_TLBWR,
+	MIPS_INS_TLT,
+	MIPS_INS_TLTI,
+	MIPS_INS_TLTIU,
+	MIPS_INS_TLTU,
+	MIPS_INS_TNE,
+	MIPS_INS_TNEI,
+	MIPS_INS_TRUNC,
+	MIPS_INS_V3MULU,
+	MIPS_INS_VMM0,
+	MIPS_INS_VMULU,
+	MIPS_INS_VSHF,
+	MIPS_INS_WAIT,
+	MIPS_INS_WRDSP,
+	MIPS_INS_WSBH,
+	MIPS_INS_XOR,
+	MIPS_INS_XOR16,
+	MIPS_INS_XORI,
+
+	//> some alias instructions
+	MIPS_INS_NOP,
+	MIPS_INS_NEGU,
+
+	//> special instructions
+	MIPS_INS_JALR_HB,	// jump and link with Hazard Barrier
+	MIPS_INS_JR_HB,		// jump register with Hazard Barrier
+
+	MIPS_INS_ENDING,
+} mips_insn;
+
+/// Group of MIPS instructions
+typedef enum mips_insn_group {
+	MIPS_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+	// Generic groups
+	// all jump instructions (conditional+direct+indirect jumps)
+	MIPS_GRP_JUMP,	///< = CS_GRP_JUMP
+	// all call instructions
+	MIPS_GRP_CALL,	///< = CS_GRP_CALL
+	// all return instructions
+	MIPS_GRP_RET,	///< = CS_GRP_RET
+	// all interrupt instructions (int+syscall)
+	MIPS_GRP_INT,	///< = CS_GRP_INT
+	// all interrupt return instructions
+	MIPS_GRP_IRET,	///< = CS_GRP_IRET
+	// all privileged instructions
+	MIPS_GRP_PRIVILEGE,	///< = CS_GRP_PRIVILEGE
+	// all relative branching instructions
+	MIPS_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
+
+	// Architecture-specific groups
+	MIPS_GRP_BITCOUNT = 128,
+	MIPS_GRP_DSP,
+	MIPS_GRP_DSPR2,
+	MIPS_GRP_FPIDX,
+	MIPS_GRP_MSA,
+	MIPS_GRP_MIPS32R2,
+	MIPS_GRP_MIPS64,
+	MIPS_GRP_MIPS64R2,
+	MIPS_GRP_SEINREG,
+	MIPS_GRP_STDENC,
+	MIPS_GRP_SWAP,
+	MIPS_GRP_MICROMIPS,
+	MIPS_GRP_MIPS16MODE,
+	MIPS_GRP_FP64BIT,
+	MIPS_GRP_NONANSFPMATH,
+	MIPS_GRP_NOTFP64BIT,
+	MIPS_GRP_NOTINMICROMIPS,
+	MIPS_GRP_NOTNACL,
+	MIPS_GRP_NOTMIPS32R6,
+	MIPS_GRP_NOTMIPS64R6,
+	MIPS_GRP_CNMIPS,
+	MIPS_GRP_MIPS32,
+	MIPS_GRP_MIPS32R6,
+	MIPS_GRP_MIPS64R6,
+	MIPS_GRP_MIPS2,
+	MIPS_GRP_MIPS3,
+	MIPS_GRP_MIPS3_32,
+	MIPS_GRP_MIPS3_32R2,
+	MIPS_GRP_MIPS4_32,
+	MIPS_GRP_MIPS4_32R2,
+	MIPS_GRP_MIPS5_32R2,
+	MIPS_GRP_GP32BIT,
+	MIPS_GRP_GP64BIT,
+
+	MIPS_GRP_ENDING,
+} mips_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

.tools/python-revlibs/capstone/include/capstone/mos65xx.h

@@ -0,0 +1,204 @@
+#ifndef CAPSTONE_MOS65XX_H
+#define CAPSTONE_MOS65XX_H
+
+/* Capstone Disassembly Engine */
+/* By Sebastian Macke <sebastian@macke.de, 2018 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+/// MOS65XX registers and special registers
+typedef enum mos65xx_reg {
+	MOS65XX_REG_INVALID = 0,
+	MOS65XX_REG_ACC, ///< accumulator
+	MOS65XX_REG_X, ///< X index register
+	MOS65XX_REG_Y, ///< Y index register
+	MOS65XX_REG_P, ///< status register
+	MOS65XX_REG_SP, ///< stack pointer register
+	MOS65XX_REG_DP, ///< direct page register
+	MOS65XX_REG_B, ///< data bank register
+	MOS65XX_REG_K, ///< program bank register
+	MOS65XX_REG_ENDING,   // <-- mark the end of the list of registers
+} mos65xx_reg;
+
+/// MOS65XX Addressing Modes
+typedef enum mos65xx_address_mode {
+	MOS65XX_AM_NONE = 0, ///< No address mode.
+	MOS65XX_AM_IMP, ///< implied addressing (no addressing mode)
+	MOS65XX_AM_ACC, ///< accumulator addressing
+	MOS65XX_AM_IMM, ///< 8/16 Bit immediate value
+	MOS65XX_AM_REL, ///< relative addressing used by branches
+	MOS65XX_AM_INT, ///< interrupt addressing
+	MOS65XX_AM_BLOCK, ///< memory block addressing
+	MOS65XX_AM_ZP,  ///< zeropage addressing
+	MOS65XX_AM_ZP_X, ///< indexed zeropage addressing by the X index register
+	MOS65XX_AM_ZP_Y, ///< indexed zeropage addressing by the Y index register
+	MOS65XX_AM_ZP_REL, ///< zero page address, branch relative address
+	MOS65XX_AM_ZP_IND, ///< indirect zeropage addressing
+	MOS65XX_AM_ZP_X_IND, ///< indexed zeropage indirect addressing by the X index register
+	MOS65XX_AM_ZP_IND_Y, ///< indirect zeropage indexed addressing by the Y index register
+	MOS65XX_AM_ZP_IND_LONG, ///< zeropage indirect long addressing
+	MOS65XX_AM_ZP_IND_LONG_Y, ///< zeropage indirect long addressing indexed by Y register
+	MOS65XX_AM_ABS, ///< absolute addressing
+	MOS65XX_AM_ABS_X, ///< indexed absolute addressing by the X index register
+	MOS65XX_AM_ABS_Y, ///< indexed absolute addressing by the Y index register
+	MOS65XX_AM_ABS_IND, ///< absolute indirect addressing
+	MOS65XX_AM_ABS_X_IND, ///< indexed absolute indirect addressing by the X index register
+	MOS65XX_AM_ABS_IND_LONG, ///< absolute indirect long addressing
+	MOS65XX_AM_ABS_LONG, ///< absolute long address mode
+	MOS65XX_AM_ABS_LONG_X, ///< absolute long address mode, indexed by X register
+	MOS65XX_AM_SR, ///< stack relative addressing
+	MOS65XX_AM_SR_IND_Y, ///< indirect stack relative addressing indexed by the Y index register
+} mos65xx_address_mode;
+
+/// MOS65XX instruction
+typedef enum mos65xx_insn {
+	MOS65XX_INS_INVALID = 0,
+	MOS65XX_INS_ADC,
+	MOS65XX_INS_AND,
+	MOS65XX_INS_ASL,
+	MOS65XX_INS_BBR,
+	MOS65XX_INS_BBS,
+	MOS65XX_INS_BCC,
+	MOS65XX_INS_BCS,
+	MOS65XX_INS_BEQ,
+	MOS65XX_INS_BIT,
+	MOS65XX_INS_BMI,
+	MOS65XX_INS_BNE,
+	MOS65XX_INS_BPL,
+	MOS65XX_INS_BRA,
+	MOS65XX_INS_BRK,
+	MOS65XX_INS_BRL,
+	MOS65XX_INS_BVC,
+	MOS65XX_INS_BVS,
+	MOS65XX_INS_CLC,
+	MOS65XX_INS_CLD,
+	MOS65XX_INS_CLI,
+	MOS65XX_INS_CLV,
+	MOS65XX_INS_CMP,
+	MOS65XX_INS_COP,
+	MOS65XX_INS_CPX,
+	MOS65XX_INS_CPY,
+	MOS65XX_INS_DEC,
+	MOS65XX_INS_DEX,
+	MOS65XX_INS_DEY,
+	MOS65XX_INS_EOR,
+	MOS65XX_INS_INC,
+	MOS65XX_INS_INX,
+	MOS65XX_INS_INY,
+	MOS65XX_INS_JML,
+	MOS65XX_INS_JMP,
+	MOS65XX_INS_JSL,
+	MOS65XX_INS_JSR,
+	MOS65XX_INS_LDA,
+	MOS65XX_INS_LDX,
+	MOS65XX_INS_LDY,
+	MOS65XX_INS_LSR,
+	MOS65XX_INS_MVN,
+	MOS65XX_INS_MVP,
+	MOS65XX_INS_NOP,
+	MOS65XX_INS_ORA,
+	MOS65XX_INS_PEA,
+	MOS65XX_INS_PEI,
+	MOS65XX_INS_PER,
+	MOS65XX_INS_PHA,
+	MOS65XX_INS_PHB,
+	MOS65XX_INS_PHD,
+	MOS65XX_INS_PHK,
+	MOS65XX_INS_PHP,
+	MOS65XX_INS_PHX,
+	MOS65XX_INS_PHY,
+	MOS65XX_INS_PLA,
+	MOS65XX_INS_PLB,
+	MOS65XX_INS_PLD,
+	MOS65XX_INS_PLP,
+	MOS65XX_INS_PLX,
+	MOS65XX_INS_PLY,
+	MOS65XX_INS_REP,
+	MOS65XX_INS_RMB,
+	MOS65XX_INS_ROL,
+	MOS65XX_INS_ROR,
+	MOS65XX_INS_RTI,
+	MOS65XX_INS_RTL,
+	MOS65XX_INS_RTS,
+	MOS65XX_INS_SBC,
+	MOS65XX_INS_SEC,
+	MOS65XX_INS_SED,
+	MOS65XX_INS_SEI,
+	MOS65XX_INS_SEP,
+	MOS65XX_INS_SMB,
+	MOS65XX_INS_STA,
+	MOS65XX_INS_STP,
+	MOS65XX_INS_STX,
+	MOS65XX_INS_STY,
+	MOS65XX_INS_STZ,
+	MOS65XX_INS_TAX,
+	MOS65XX_INS_TAY,
+	MOS65XX_INS_TCD,
+	MOS65XX_INS_TCS,
+	MOS65XX_INS_TDC,
+	MOS65XX_INS_TRB,
+	MOS65XX_INS_TSB,
+	MOS65XX_INS_TSC,
+	MOS65XX_INS_TSX,
+	MOS65XX_INS_TXA,
+	MOS65XX_INS_TXS,
+	MOS65XX_INS_TXY,
+	MOS65XX_INS_TYA,
+	MOS65XX_INS_TYX,
+	MOS65XX_INS_WAI,
+	MOS65XX_INS_WDM,
+	MOS65XX_INS_XBA,
+	MOS65XX_INS_XCE,
+	MOS65XX_INS_ENDING,   // <-- mark the end of the list of instructions
+} mos65xx_insn;
+
+/// Group of MOS65XX instructions
+typedef enum mos65xx_group_type {
+	MOS65XX_GRP_INVALID = 0,  ///< CS_GRP_INVALID
+	MOS65XX_GRP_JUMP,		 ///< = CS_GRP_JUMP
+	MOS65XX_GRP_CALL,		 ///< = CS_GRP_RET
+	MOS65XX_GRP_RET,		  ///< = CS_GRP_RET
+	MOS65XX_GRP_INT,		  ///< = CS_GRP_INT
+	MOS65XX_GRP_IRET = 5,	 ///< = CS_GRP_IRET
+	MOS65XX_GRP_BRANCH_RELATIVE = 6, ///< = CS_GRP_BRANCH_RELATIVE
+	MOS65XX_GRP_ENDING,// <-- mark the end of the list of groups
+} mos65xx_group_type;
+
+/// Operand type for instruction's operands
+typedef enum mos65xx_op_type {
+	MOS65XX_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+	MOS65XX_OP_REG, ///< = CS_OP_REG (Register operand).
+	MOS65XX_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	MOS65XX_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+} mos65xx_op_type;
+
+/// Instruction operand
+typedef struct cs_mos65xx_op {
+	mos65xx_op_type type;	///< operand type
+	union {
+		mos65xx_reg reg;	///< register value for REG operand
+		uint16_t imm;		///< immediate value for IMM operand
+		uint32_t mem;		///< address for MEM operand
+	};
+} cs_mos65xx_op;
+
+/// The MOS65XX address mode and it's operands
+typedef struct cs_mos65xx {
+	mos65xx_address_mode am;
+	bool modifies_flags;
+
+	/// Number of operands of this instruction,
+	/// or 0 when instruction has no operand.
+	uint8_t op_count;
+	cs_mos65xx_op operands[3]; ///< operands for this instruction.
+} cs_mos65xx;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //CAPSTONE_MOS65XX_H

.tools/python-revlibs/capstone/include/capstone/platform.h

@@ -0,0 +1,122 @@
+/* Capstone Disassembly Engine */
+/* By Axel Souchet & Nguyen Anh Quynh, 2014 */
+
+#ifndef CAPSTONE_PLATFORM_H
+#define CAPSTONE_PLATFORM_H
+
+
+// handle C99 issue (for pre-2013 VisualStudio)
+#if !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
+// MSVC
+
+// stdbool.h
+#if (_MSC_VER < 1800) || defined(_KERNEL_MODE)
+// this system does not have stdbool.h
+#ifndef __cplusplus
+typedef unsigned char bool;
+#define false 0
+#define true 1
+#endif  // __cplusplus
+
+#else
+// VisualStudio 2013+ -> C99 is supported
+#include <stdbool.h>
+#endif  // (_MSC_VER < 1800) || defined(_KERNEL_MODE)
+
+#else
+// not MSVC -> C99 is supported
+#include <stdbool.h>
+#endif  // !defined(__CYGWIN__) && !defined(__MINGW32__) && !defined(__MINGW64__) && (defined (WIN32) || defined (WIN64) || defined (_WIN32) || defined (_WIN64))
+
+
+// handle inttypes.h / stdint.h compatibility
+#if defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
+#include "windowsce/stdint.h"
+#endif  // defined(_WIN32_WCE) && (_WIN32_WCE < 0x800)
+
+#if defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
+// this system does not have inttypes.h
+
+#if defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE))
+// this system does not have stdint.h
+typedef signed char  int8_t;
+typedef signed short int16_t;
+typedef signed int   int32_t;
+typedef unsigned char  uint8_t;
+typedef unsigned short uint16_t;
+typedef unsigned int   uint32_t;
+typedef signed long long   int64_t;
+typedef unsigned long long uint64_t;
+#endif  // defined(_MSC_VER) && (_MSC_VER <= 1600 || defined(_KERNEL_MODE))
+
+#if defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))
+#define INT8_MIN         (-127i8 - 1)
+#define INT16_MIN        (-32767i16 - 1)
+#define INT32_MIN        (-2147483647i32 - 1)
+#define INT64_MIN        (-9223372036854775807i64 - 1)
+#define INT8_MAX         127i8
+#define INT16_MAX        32767i16
+#define INT32_MAX        2147483647i32
+#define INT64_MAX        9223372036854775807i64
+#define UINT8_MAX        0xffui8
+#define UINT16_MAX       0xffffui16
+#define UINT32_MAX       0xffffffffui32
+#define UINT64_MAX       0xffffffffffffffffui64
+#endif  // defined(_MSC_VER) && (_MSC_VER < 1600 || defined(_KERNEL_MODE))
+
+#ifdef CAPSTONE_HAS_OSXKERNEL
+// this system has stdint.h
+#include <stdint.h>
+#endif
+
+#define __PRI_8_LENGTH_MODIFIER__ "hh"
+#define __PRI_64_LENGTH_MODIFIER__ "ll"
+
+#define PRId8         __PRI_8_LENGTH_MODIFIER__ "d"
+#define PRIi8         __PRI_8_LENGTH_MODIFIER__ "i"
+#define PRIo8         __PRI_8_LENGTH_MODIFIER__ "o"
+#define PRIu8         __PRI_8_LENGTH_MODIFIER__ "u"
+#define PRIx8         __PRI_8_LENGTH_MODIFIER__ "x"
+#define PRIX8         __PRI_8_LENGTH_MODIFIER__ "X"
+
+#define PRId16        "hd"
+#define PRIi16        "hi"
+#define PRIo16        "ho"
+#define PRIu16        "hu"
+#define PRIx16        "hx"
+#define PRIX16        "hX"
+
+#if defined(_MSC_VER) && _MSC_VER <= 1700
+#define PRId32        "ld"
+#define PRIi32        "li"
+#define PRIo32        "lo"
+#define PRIu32        "lu"
+#define PRIx32        "lx"
+#define PRIX32        "lX"
+#else	// OSX
+#define PRId32        "d"
+#define PRIi32        "i"
+#define PRIo32        "o"
+#define PRIu32        "u"
+#define PRIx32        "x"
+#define PRIX32        "X"
+#endif  // defined(_MSC_VER) && _MSC_VER <= 1700
+
+#if defined(_MSC_VER) && _MSC_VER <= 1700
+// redefine functions from inttypes.h used in cstool
+#define strtoull _strtoui64
+#endif
+
+#define PRId64        __PRI_64_LENGTH_MODIFIER__ "d"
+#define PRIi64        __PRI_64_LENGTH_MODIFIER__ "i"
+#define PRIo64        __PRI_64_LENGTH_MODIFIER__ "o"
+#define PRIu64        __PRI_64_LENGTH_MODIFIER__ "u"
+#define PRIx64        __PRI_64_LENGTH_MODIFIER__ "x"
+#define PRIX64        __PRI_64_LENGTH_MODIFIER__ "X"
+
+#else
+// this system has inttypes.h by default
+#include <inttypes.h>
+#endif  // defined(CAPSTONE_HAS_OSXKERNEL) || (defined(_MSC_VER) && (_MSC_VER <= 1700 || defined(_KERNEL_MODE)))
+
+#endif

.tools/python-revlibs/capstone/include/capstone/riscv.h

@@ -0,0 +1,531 @@
+#ifndef CAPSTONE_RISCV_H
+#define CAPSTONE_RISCV_H
+
+/* Capstone Disassembly Engine */
+/* RISC-V Backend By Rodrigo Cortes Porto <porto703@gmail.com> & 
+   Shawn Chang <citypw@gmail.com>, HardenedLinux@2018 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+
+#include "platform.h"
+
+// GCC MIPS toolchain has a default macro called "mips" which breaks
+// compilation
+//#undef riscv
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+//> Operand type for instruction's operands
+typedef enum riscv_op_type {
+	RISCV_OP_INVALID = 0, // = CS_OP_INVALID (Uninitialized).
+	RISCV_OP_REG, // = CS_OP_REG (Register operand).
+	RISCV_OP_IMM, // = CS_OP_IMM (Immediate operand).
+	RISCV_OP_MEM, // = CS_OP_MEM (Memory operand).
+} riscv_op_type;
+
+// Instruction's operand referring to memory
+// This is associated with RISCV_OP_MEM operand type above
+typedef struct riscv_op_mem {
+	unsigned int base;	// base register
+	int64_t disp;	// displacement/offset value
+} riscv_op_mem;
+
+// Instruction operand
+typedef struct cs_riscv_op {
+	riscv_op_type type;	// operand type
+	union {
+		unsigned int reg;	// register value for REG operand
+		int64_t imm;		// immediate value for IMM operand
+		riscv_op_mem mem;	// base/disp value for MEM operand
+	};
+} cs_riscv_op;
+
+// Instruction structure
+typedef struct cs_riscv {
+	// Does this instruction need effective address or not.
+	bool need_effective_addr;
+	// Number of operands of this instruction, 
+	// or 0 when instruction has no operand.
+	uint8_t op_count;
+	cs_riscv_op operands[8]; // operands for this instruction.
+} cs_riscv;
+
+//> RISCV registers
+typedef enum riscv_reg {
+	RISCV_REG_INVALID = 0,
+	//> General purpose registers
+	RISCV_REG_X0,			// "zero" 
+	RISCV_REG_ZERO = RISCV_REG_X0, 	// "zero" 
+	RISCV_REG_X1, 			// "ra"
+	RISCV_REG_RA   = RISCV_REG_X1, 	// "ra"
+	RISCV_REG_X2, 			// "sp"
+	RISCV_REG_SP   = RISCV_REG_X2, 	// "sp"
+	RISCV_REG_X3, 			// "gp"
+	RISCV_REG_GP   = RISCV_REG_X3, 	// "gp"
+	RISCV_REG_X4, 			// "tp"
+	RISCV_REG_TP   = RISCV_REG_X4,	// "tp"
+	RISCV_REG_X5, 			// "t0"
+	RISCV_REG_T0   = RISCV_REG_X5, 	// "t0"
+	RISCV_REG_X6, 			// "t1"
+	RISCV_REG_T1   = RISCV_REG_X6, 	// "t1"
+	RISCV_REG_X7, 			// "t2"
+	RISCV_REG_T2   = RISCV_REG_X7, 	// "t2"
+	RISCV_REG_X8, 			// "s0/fp"
+	RISCV_REG_S0   = RISCV_REG_X8,	// "s0"
+	RISCV_REG_FP   = RISCV_REG_X8,	// "fp"
+	RISCV_REG_X9, 			// "s1"
+	RISCV_REG_S1   = RISCV_REG_X9, 	// "s1"
+	RISCV_REG_X10,			// "a0"
+	RISCV_REG_A0   = RISCV_REG_X10,	// "a0"
+	RISCV_REG_X11,			// "a1"
+	RISCV_REG_A1   = RISCV_REG_X11,	// "a1"
+	RISCV_REG_X12,			// "a2"
+	RISCV_REG_A2   = RISCV_REG_X12,	// "a2"
+	RISCV_REG_X13,			// "a3"
+	RISCV_REG_A3   = RISCV_REG_X13,	// "a3"
+	RISCV_REG_X14,			// "a4"
+	RISCV_REG_A4   = RISCV_REG_X14,	// "a4"
+	RISCV_REG_X15,			// "a5"
+	RISCV_REG_A5   = RISCV_REG_X15, // "a5"
+	RISCV_REG_X16,			// "a6"
+	RISCV_REG_A6   = RISCV_REG_X16,	// "a6"
+	RISCV_REG_X17,			// "a7"
+	RISCV_REG_A7   = RISCV_REG_X17,	// "a7"
+	RISCV_REG_X18,			// "s2"
+	RISCV_REG_S2   = RISCV_REG_X18,	// "s2"
+	RISCV_REG_X19,			// "s3"
+	RISCV_REG_S3   = RISCV_REG_X19, // "s3"
+	RISCV_REG_X20,			// "s4"
+	RISCV_REG_S4   = RISCV_REG_X20,	// "s4"
+	RISCV_REG_X21,			// "s5"
+	RISCV_REG_S5   = RISCV_REG_X21,	// "s5"
+	RISCV_REG_X22,			// "s6"
+	RISCV_REG_S6   = RISCV_REG_X22,	// "s6"
+	RISCV_REG_X23,			// "s7"
+	RISCV_REG_S7   = RISCV_REG_X23,	// "s7"
+	RISCV_REG_X24,			// "s8"
+	RISCV_REG_S8   = RISCV_REG_X24,	// "s8"
+	RISCV_REG_X25,			// "s9"
+	RISCV_REG_S9   = RISCV_REG_X25,	// "s9"
+	RISCV_REG_X26,			// "s10"
+	RISCV_REG_S10  = RISCV_REG_X26,	// "s10"
+	RISCV_REG_X27,			// "s11"
+	RISCV_REG_S11  = RISCV_REG_X27, // "s11"
+	RISCV_REG_X28,			// "t3"
+	RISCV_REG_T3   = RISCV_REG_X28,	// "t3"
+	RISCV_REG_X29,			// "t4"
+	RISCV_REG_T4   = RISCV_REG_X29, // "t4"
+	RISCV_REG_X30,			// "t5"
+	RISCV_REG_T5   = RISCV_REG_X30,	// "t5"
+	RISCV_REG_X31,			// "t6"
+	RISCV_REG_T6   = RISCV_REG_X31,	// "t6"
+	
+	//> Floating-point registers
+	RISCV_REG_F0_32,		// "ft0"
+	RISCV_REG_F0_64,		// "ft0"
+	RISCV_REG_F1_32,		// "ft1"
+	RISCV_REG_F1_64,		// "ft1"
+	RISCV_REG_F2_32,		// "ft2"
+	RISCV_REG_F2_64,		// "ft2"
+	RISCV_REG_F3_32,		// "ft3"
+	RISCV_REG_F3_64,		// "ft3"
+	RISCV_REG_F4_32,		// "ft4"
+	RISCV_REG_F4_64,		// "ft4"
+	RISCV_REG_F5_32,		// "ft5"
+	RISCV_REG_F5_64,		// "ft5"
+	RISCV_REG_F6_32,		// "ft6"
+	RISCV_REG_F6_64,		// "ft6"
+	RISCV_REG_F7_32,		// "ft7"
+	RISCV_REG_F7_64,		// "ft7"
+	RISCV_REG_F8_32,		// "fs0"
+	RISCV_REG_F8_64,		// "fs0"
+	RISCV_REG_F9_32,		// "fs1"
+	RISCV_REG_F9_64,		// "fs1"
+	RISCV_REG_F10_32,		// "fa0"
+	RISCV_REG_F10_64,		// "fa0"
+	RISCV_REG_F11_32,		// "fa1"
+	RISCV_REG_F11_64,		// "fa1"
+	RISCV_REG_F12_32,		// "fa2"
+	RISCV_REG_F12_64,		// "fa2"
+	RISCV_REG_F13_32,		// "fa3"
+	RISCV_REG_F13_64,		// "fa3"
+	RISCV_REG_F14_32,		// "fa4"
+	RISCV_REG_F14_64,		// "fa4"
+	RISCV_REG_F15_32,		// "fa5"
+	RISCV_REG_F15_64,		// "fa5"
+	RISCV_REG_F16_32,		// "fa6"
+	RISCV_REG_F16_64,		// "fa6"
+	RISCV_REG_F17_32,		// "fa7"
+	RISCV_REG_F17_64,		// "fa7"
+	RISCV_REG_F18_32,		// "fs2"
+	RISCV_REG_F18_64,		// "fs2"
+	RISCV_REG_F19_32,		// "fs3"
+	RISCV_REG_F19_64,		// "fs3"
+	RISCV_REG_F20_32,		// "fs4"
+	RISCV_REG_F20_64,		// "fs4"
+	RISCV_REG_F21_32,		// "fs5"
+	RISCV_REG_F21_64,		// "fs5"
+	RISCV_REG_F22_32,		// "fs6"
+	RISCV_REG_F22_64,		// "fs6"
+	RISCV_REG_F23_32,		// "fs7"
+	RISCV_REG_F23_64,		// "fs7"
+	RISCV_REG_F24_32,		// "fs8"
+	RISCV_REG_F24_64,		// "fs8"
+	RISCV_REG_F25_32,		// "fs9"
+	RISCV_REG_F25_64,		// "fs9"
+	RISCV_REG_F26_32,		// "fs10"
+	RISCV_REG_F26_64,		// "fs10"
+	RISCV_REG_F27_32,		// "fs11"
+	RISCV_REG_F27_64,		// "fs11"
+	RISCV_REG_F28_32,		// "ft8"
+	RISCV_REG_F28_64,		// "ft8"
+	RISCV_REG_F29_32,		// "ft9"
+	RISCV_REG_F29_64,		// "ft9"
+	RISCV_REG_F30_32,		// "ft10"
+	RISCV_REG_F30_64,		// "ft10"
+	RISCV_REG_F31_32,		// "ft11"
+	RISCV_REG_F31_64,		// "ft11"
+	
+	RISCV_REG_ENDING,		// <-- mark the end of the list or registers
+} riscv_reg;
+
+//> RISCV instruction
+typedef enum riscv_insn {
+  	RISCV_INS_INVALID = 0,
+
+  	RISCV_INS_ADD,
+  	RISCV_INS_ADDI,
+  	RISCV_INS_ADDIW,
+  	RISCV_INS_ADDW,
+  	RISCV_INS_AMOADD_D,
+  	RISCV_INS_AMOADD_D_AQ,
+  	RISCV_INS_AMOADD_D_AQ_RL,
+  	RISCV_INS_AMOADD_D_RL,
+  	RISCV_INS_AMOADD_W,
+  	RISCV_INS_AMOADD_W_AQ,
+  	RISCV_INS_AMOADD_W_AQ_RL,
+  	RISCV_INS_AMOADD_W_RL,
+  	RISCV_INS_AMOAND_D,
+  	RISCV_INS_AMOAND_D_AQ,
+  	RISCV_INS_AMOAND_D_AQ_RL,
+  	RISCV_INS_AMOAND_D_RL,
+  	RISCV_INS_AMOAND_W,
+  	RISCV_INS_AMOAND_W_AQ,
+  	RISCV_INS_AMOAND_W_AQ_RL,
+  	RISCV_INS_AMOAND_W_RL,
+  	RISCV_INS_AMOMAXU_D,
+  	RISCV_INS_AMOMAXU_D_AQ,
+  	RISCV_INS_AMOMAXU_D_AQ_RL,
+  	RISCV_INS_AMOMAXU_D_RL,
+  	RISCV_INS_AMOMAXU_W,
+  	RISCV_INS_AMOMAXU_W_AQ,
+  	RISCV_INS_AMOMAXU_W_AQ_RL,
+  	RISCV_INS_AMOMAXU_W_RL,
+  	RISCV_INS_AMOMAX_D,
+  	RISCV_INS_AMOMAX_D_AQ,
+  	RISCV_INS_AMOMAX_D_AQ_RL,
+  	RISCV_INS_AMOMAX_D_RL,
+  	RISCV_INS_AMOMAX_W,
+  	RISCV_INS_AMOMAX_W_AQ,
+  	RISCV_INS_AMOMAX_W_AQ_RL,
+  	RISCV_INS_AMOMAX_W_RL,
+  	RISCV_INS_AMOMINU_D,
+  	RISCV_INS_AMOMINU_D_AQ,
+  	RISCV_INS_AMOMINU_D_AQ_RL,
+  	RISCV_INS_AMOMINU_D_RL,
+  	RISCV_INS_AMOMINU_W,
+  	RISCV_INS_AMOMINU_W_AQ,
+  	RISCV_INS_AMOMINU_W_AQ_RL,
+  	RISCV_INS_AMOMINU_W_RL,
+  	RISCV_INS_AMOMIN_D,
+  	RISCV_INS_AMOMIN_D_AQ,
+  	RISCV_INS_AMOMIN_D_AQ_RL,
+  	RISCV_INS_AMOMIN_D_RL,
+  	RISCV_INS_AMOMIN_W,
+  	RISCV_INS_AMOMIN_W_AQ,
+  	RISCV_INS_AMOMIN_W_AQ_RL,
+  	RISCV_INS_AMOMIN_W_RL,
+  	RISCV_INS_AMOOR_D,
+  	RISCV_INS_AMOOR_D_AQ,
+  	RISCV_INS_AMOOR_D_AQ_RL,
+  	RISCV_INS_AMOOR_D_RL,
+  	RISCV_INS_AMOOR_W,
+  	RISCV_INS_AMOOR_W_AQ,
+  	RISCV_INS_AMOOR_W_AQ_RL,
+  	RISCV_INS_AMOOR_W_RL,
+  	RISCV_INS_AMOSWAP_D,
+  	RISCV_INS_AMOSWAP_D_AQ,
+  	RISCV_INS_AMOSWAP_D_AQ_RL,
+  	RISCV_INS_AMOSWAP_D_RL,
+  	RISCV_INS_AMOSWAP_W,
+  	RISCV_INS_AMOSWAP_W_AQ,
+  	RISCV_INS_AMOSWAP_W_AQ_RL,
+  	RISCV_INS_AMOSWAP_W_RL,
+  	RISCV_INS_AMOXOR_D,
+  	RISCV_INS_AMOXOR_D_AQ,
+  	RISCV_INS_AMOXOR_D_AQ_RL,
+  	RISCV_INS_AMOXOR_D_RL,
+  	RISCV_INS_AMOXOR_W,
+  	RISCV_INS_AMOXOR_W_AQ,
+  	RISCV_INS_AMOXOR_W_AQ_RL,
+  	RISCV_INS_AMOXOR_W_RL,
+  	RISCV_INS_AND,
+  	RISCV_INS_ANDI,
+  	RISCV_INS_AUIPC,
+  	RISCV_INS_BEQ,
+  	RISCV_INS_BGE,
+  	RISCV_INS_BGEU,
+  	RISCV_INS_BLT,
+  	RISCV_INS_BLTU,
+  	RISCV_INS_BNE,
+  	RISCV_INS_CSRRC,
+  	RISCV_INS_CSRRCI,
+  	RISCV_INS_CSRRS,
+  	RISCV_INS_CSRRSI,
+ 	RISCV_INS_CSRRW,
+  	RISCV_INS_CSRRWI,
+  	RISCV_INS_C_ADD,
+  	RISCV_INS_C_ADDI,
+  	RISCV_INS_C_ADDI16SP,
+  	RISCV_INS_C_ADDI4SPN,
+  	RISCV_INS_C_ADDIW,
+  	RISCV_INS_C_ADDW,
+  	RISCV_INS_C_AND,
+  	RISCV_INS_C_ANDI,
+  	RISCV_INS_C_BEQZ,
+  	RISCV_INS_C_BNEZ,
+  	RISCV_INS_C_EBREAK,
+  	RISCV_INS_C_FLD,
+  	RISCV_INS_C_FLDSP,
+  	RISCV_INS_C_FLW,
+  	RISCV_INS_C_FLWSP,
+  	RISCV_INS_C_FSD,
+  	RISCV_INS_C_FSDSP,
+  	RISCV_INS_C_FSW,
+  	RISCV_INS_C_FSWSP,
+  	RISCV_INS_C_J,
+  	RISCV_INS_C_JAL,
+  	RISCV_INS_C_JALR,
+  	RISCV_INS_C_JR,
+  	RISCV_INS_C_LD,
+  	RISCV_INS_C_LDSP,
+  	RISCV_INS_C_LI,
+  	RISCV_INS_C_LUI,
+  	RISCV_INS_C_LW,
+  	RISCV_INS_C_LWSP,
+  	RISCV_INS_C_MV,
+  	RISCV_INS_C_NOP,
+  	RISCV_INS_C_OR,
+  	RISCV_INS_C_SD,
+	RISCV_INS_C_SDSP,
+  	RISCV_INS_C_SLLI,
+  	RISCV_INS_C_SRAI,
+  	RISCV_INS_C_SRLI,
+  	RISCV_INS_C_SUB,
+  	RISCV_INS_C_SUBW,
+  	RISCV_INS_C_SW,
+  	RISCV_INS_C_SWSP,
+  	RISCV_INS_C_UNIMP,
+  	RISCV_INS_C_XOR,
+  	RISCV_INS_DIV,
+  	RISCV_INS_DIVU,
+  	RISCV_INS_DIVUW,
+  	RISCV_INS_DIVW,
+  	RISCV_INS_EBREAK,
+  	RISCV_INS_ECALL,
+  	RISCV_INS_FADD_D,
+  	RISCV_INS_FADD_S,
+  	RISCV_INS_FCLASS_D,
+  	RISCV_INS_FCLASS_S,
+  	RISCV_INS_FCVT_D_L,
+  	RISCV_INS_FCVT_D_LU,
+  	RISCV_INS_FCVT_D_S,
+  	RISCV_INS_FCVT_D_W,
+  	RISCV_INS_FCVT_D_WU,
+  	RISCV_INS_FCVT_LU_D,
+  	RISCV_INS_FCVT_LU_S,
+  	RISCV_INS_FCVT_L_D,
+  	RISCV_INS_FCVT_L_S,
+  	RISCV_INS_FCVT_S_D,
+  	RISCV_INS_FCVT_S_L,
+  	RISCV_INS_FCVT_S_LU,
+  	RISCV_INS_FCVT_S_W,
+  	RISCV_INS_FCVT_S_WU,
+  	RISCV_INS_FCVT_WU_D,
+  	RISCV_INS_FCVT_WU_S,
+  	RISCV_INS_FCVT_W_D,
+  	RISCV_INS_FCVT_W_S,
+  	RISCV_INS_FDIV_D,
+  	RISCV_INS_FDIV_S,
+  	RISCV_INS_FENCE,
+  	RISCV_INS_FENCE_I,
+  	RISCV_INS_FENCE_TSO,
+  	RISCV_INS_FEQ_D,
+  	RISCV_INS_FEQ_S,
+  	RISCV_INS_FLD,
+  	RISCV_INS_FLE_D,
+  	RISCV_INS_FLE_S,
+  	RISCV_INS_FLT_D,
+  	RISCV_INS_FLT_S,
+  	RISCV_INS_FLW,
+  	RISCV_INS_FMADD_D,
+  	RISCV_INS_FMADD_S,
+  	RISCV_INS_FMAX_D,
+  	RISCV_INS_FMAX_S,
+  	RISCV_INS_FMIN_D,
+  	RISCV_INS_FMIN_S,
+  	RISCV_INS_FMSUB_D,
+  	RISCV_INS_FMSUB_S,
+  	RISCV_INS_FMUL_D,
+  	RISCV_INS_FMUL_S,
+  	RISCV_INS_FMV_D_X,
+  	RISCV_INS_FMV_W_X,
+  	RISCV_INS_FMV_X_D,
+  	RISCV_INS_FMV_X_W,
+  	RISCV_INS_FNMADD_D,
+  	RISCV_INS_FNMADD_S,
+  	RISCV_INS_FNMSUB_D,
+  	RISCV_INS_FNMSUB_S,
+  	RISCV_INS_FSD,
+  	RISCV_INS_FSGNJN_D,
+  	RISCV_INS_FSGNJN_S,
+  	RISCV_INS_FSGNJX_D,
+  	RISCV_INS_FSGNJX_S,
+  	RISCV_INS_FSGNJ_D,
+  	RISCV_INS_FSGNJ_S,
+  	RISCV_INS_FSQRT_D,
+  	RISCV_INS_FSQRT_S,
+  	RISCV_INS_FSUB_D,
+  	RISCV_INS_FSUB_S,
+  	RISCV_INS_FSW,
+  	RISCV_INS_JAL,
+  	RISCV_INS_JALR,
+  	RISCV_INS_LB,
+  	RISCV_INS_LBU,
+  	RISCV_INS_LD,
+  	RISCV_INS_LH,
+  	RISCV_INS_LHU,
+  	RISCV_INS_LR_D,
+  	RISCV_INS_LR_D_AQ,
+  	RISCV_INS_LR_D_AQ_RL,
+  	RISCV_INS_LR_D_RL,
+  	RISCV_INS_LR_W,
+  	RISCV_INS_LR_W_AQ,
+  	RISCV_INS_LR_W_AQ_RL,
+  	RISCV_INS_LR_W_RL,
+  	RISCV_INS_LUI,
+  	RISCV_INS_LW,
+  	RISCV_INS_LWU,
+  	RISCV_INS_MRET,
+  	RISCV_INS_MUL,
+  	RISCV_INS_MULH,
+  	RISCV_INS_MULHSU,
+  	RISCV_INS_MULHU,
+  	RISCV_INS_MULW,
+  	RISCV_INS_OR,
+  	RISCV_INS_ORI,
+  	RISCV_INS_REM,
+  	RISCV_INS_REMU,
+  	RISCV_INS_REMUW,
+  	RISCV_INS_REMW,
+  	RISCV_INS_SB,
+  	RISCV_INS_SC_D,
+  	RISCV_INS_SC_D_AQ,
+  	RISCV_INS_SC_D_AQ_RL,
+  	RISCV_INS_SC_D_RL,
+  	RISCV_INS_SC_W,
+  	RISCV_INS_SC_W_AQ,
+  	RISCV_INS_SC_W_AQ_RL,
+  	RISCV_INS_SC_W_RL,
+  	RISCV_INS_SD,
+  	RISCV_INS_SFENCE_VMA,
+  	RISCV_INS_SH,
+  	RISCV_INS_SLL,
+  	RISCV_INS_SLLI,
+  	RISCV_INS_SLLIW,
+  	RISCV_INS_SLLW,
+  	RISCV_INS_SLT,
+  	RISCV_INS_SLTI,
+  	RISCV_INS_SLTIU,
+  	RISCV_INS_SLTU,
+  	RISCV_INS_SRA,
+  	RISCV_INS_SRAI,
+  	RISCV_INS_SRAIW,
+  	RISCV_INS_SRAW,
+  	RISCV_INS_SRET,
+  	RISCV_INS_SRL,
+  	RISCV_INS_SRLI,
+  	RISCV_INS_SRLIW,
+  	RISCV_INS_SRLW,
+  	RISCV_INS_SUB,
+  	RISCV_INS_SUBW,
+  	RISCV_INS_SW,
+  	RISCV_INS_UNIMP,
+  	RISCV_INS_URET,
+  	RISCV_INS_WFI,
+  	RISCV_INS_XOR,
+  	RISCV_INS_XORI,	
+	
+  	RISCV_INS_ENDING,
+} riscv_insn;
+
+//> Group of RISCV instructions
+typedef enum riscv_insn_group {
+  	RISCV_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+  	// Generic groups
+  	// all jump instructions (conditional+direct+indirect jumps)
+  	RISCV_GRP_JUMP,	///< = CS_GRP_JUMP
+  	// all call instructions
+  	RISCV_GRP_CALL,	///< = CS_GRP_CALL
+  	// all return instructions
+  	RISCV_GRP_RET,	///< = CS_GRP_RET
+  	// all interrupt instructions (int+syscall)
+  	RISCV_GRP_INT,	///< = CS_GRP_INT
+  	// all interrupt return instructions
+  	RISCV_GRP_IRET,	///< = CS_GRP_IRET
+  	// all privileged instructions
+  	RISCV_GRP_PRIVILEGE,	///< = CS_GRP_PRIVILEGE
+  	// all relative branching instructions
+  	RISCV_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
+  
+  	// Architecture-specific groups
+  	RISCV_GRP_ISRV32 = 128,
+  	RISCV_GRP_ISRV64,
+  	RISCV_GRP_HASSTDEXTA,
+  	RISCV_GRP_HASSTDEXTC,
+  	RISCV_GRP_HASSTDEXTD,
+  	RISCV_GRP_HASSTDEXTF,
+  	RISCV_GRP_HASSTDEXTM,
+  	/*
+  	RISCV_GRP_ISRVA,
+  	RISCV_GRP_ISRVC,
+  	RISCV_GRP_ISRVD,
+  	RISCV_GRP_ISRVCD,
+  	RISCV_GRP_ISRVF,
+  	RISCV_GRP_ISRV32C,
+  	RISCV_GRP_ISRV32CF,
+  	RISCV_GRP_ISRVM,
+  	RISCV_GRP_ISRV64A,
+  	RISCV_GRP_ISRV64C,
+  	RISCV_GRP_ISRV64D,
+  	RISCV_GRP_ISRV64F,
+  	RISCV_GRP_ISRV64M,
+  	*/
+  	RISCV_GRP_ENDING,
+} riscv_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

.tools/python-revlibs/capstone/include/capstone/sh.h

@@ -0,0 +1,465 @@
+#ifndef CAPSTONE_SH_H
+#define CAPSTONE_SH_H
+
+/* Capstone Disassembly Engine */
+/* By Yoshinori Sato, 2022 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// SH registers and special registers
+typedef enum {
+	SH_REG_INVALID = 0,
+
+	SH_REG_R0,
+	SH_REG_R1,
+	SH_REG_R2,
+	SH_REG_R3,
+	SH_REG_R4,
+	SH_REG_R5,
+	SH_REG_R6,
+	SH_REG_R7,
+
+	SH_REG_R8,
+	SH_REG_R9,
+	SH_REG_R10,
+	SH_REG_R11,
+	SH_REG_R12,
+	SH_REG_R13,
+	SH_REG_R14,
+	SH_REG_R15,
+
+	SH_REG_R0_BANK,
+	SH_REG_R1_BANK,
+	SH_REG_R2_BANK,
+	SH_REG_R3_BANK,
+	SH_REG_R4_BANK,
+	SH_REG_R5_BANK,
+	SH_REG_R6_BANK,
+	SH_REG_R7_BANK,
+
+	SH_REG_FR0,
+	SH_REG_FR1,
+	SH_REG_FR2,
+	SH_REG_FR3,
+	SH_REG_FR4,
+	SH_REG_FR5,
+	SH_REG_FR6,
+	SH_REG_FR7,
+	SH_REG_FR8,
+	SH_REG_FR9,
+	SH_REG_FR10,
+	SH_REG_FR11,
+	SH_REG_FR12,
+	SH_REG_FR13,
+	SH_REG_FR14,
+	SH_REG_FR15,
+
+	SH_REG_DR0,
+	SH_REG_DR2,
+	SH_REG_DR4,
+	SH_REG_DR6,
+	SH_REG_DR8,
+	SH_REG_DR10,
+	SH_REG_DR12,
+	SH_REG_DR14,
+
+	SH_REG_XD0,
+	SH_REG_XD2,
+	SH_REG_XD4,
+	SH_REG_XD6,
+	SH_REG_XD8,
+	SH_REG_XD10,
+	SH_REG_XD12,
+	SH_REG_XD14,
+
+	SH_REG_XF0,
+	SH_REG_XF1,
+	SH_REG_XF2,
+	SH_REG_XF3,
+	SH_REG_XF4,
+	SH_REG_XF5,
+	SH_REG_XF6,
+	SH_REG_XF7,
+	SH_REG_XF8,
+	SH_REG_XF9,
+	SH_REG_XF10,
+	SH_REG_XF11,
+	SH_REG_XF12,
+	SH_REG_XF13,
+	SH_REG_XF14,
+	SH_REG_XF15,
+
+	SH_REG_FV0,
+	SH_REG_FV4,
+	SH_REG_FV8,
+	SH_REG_FV12,
+
+	SH_REG_XMATRX,
+
+	SH_REG_PC,
+	SH_REG_PR,
+	SH_REG_MACH,
+	SH_REG_MACL,
+
+	SH_REG_SR,
+	SH_REG_GBR,
+	SH_REG_SSR,
+	SH_REG_SPC,
+	SH_REG_SGR,
+	SH_REG_DBR,
+	SH_REG_VBR,
+	SH_REG_TBR,
+	SH_REG_RS,
+	SH_REG_RE,
+	SH_REG_MOD,
+
+	SH_REG_FPUL,
+	SH_REG_FPSCR,
+
+	SH_REG_DSP_X0,
+	SH_REG_DSP_X1,
+	SH_REG_DSP_Y0,
+	SH_REG_DSP_Y1,
+	SH_REG_DSP_A0,
+	SH_REG_DSP_A1,
+	SH_REG_DSP_A0G,
+	SH_REG_DSP_A1G,
+	SH_REG_DSP_M0,
+	SH_REG_DSP_M1,
+	SH_REG_DSP_DSR,
+
+	SH_REG_DSP_RSV0,
+	SH_REG_DSP_RSV1,
+	SH_REG_DSP_RSV2,
+	SH_REG_DSP_RSV3,
+	SH_REG_DSP_RSV4,
+	SH_REG_DSP_RSV5,
+	SH_REG_DSP_RSV6,
+	SH_REG_DSP_RSV7,
+	SH_REG_DSP_RSV8,
+	SH_REG_DSP_RSV9,
+	SH_REG_DSP_RSVA,
+	SH_REG_DSP_RSVB,
+	SH_REG_DSP_RSVC,
+	SH_REG_DSP_RSVD,
+	SH_REG_DSP_RSVE,
+	SH_REG_DSP_RSVF,
+
+	SH_REG_ENDING,   // <-- mark the end of the list of registers
+} sh_reg;
+
+typedef enum {
+	SH_OP_INVALID = 0,  ///< = CS_OP_INVALID (Uninitialized).
+	SH_OP_REG, ///< = CS_OP_REG (Register operand).
+	SH_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	SH_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+} sh_op_type;	
+
+typedef enum {
+	SH_OP_MEM_INVALID = 0,   /// <= Invalid
+	SH_OP_MEM_REG_IND,   /// <= Register indirect
+	SH_OP_MEM_REG_POST,  /// <= Register post increment
+	SH_OP_MEM_REG_PRE,   /// <= Register pre decrement
+	SH_OP_MEM_REG_DISP,  /// <= displacement
+	SH_OP_MEM_REG_R0,    /// <= R0 indexed
+	SH_OP_MEM_GBR_DISP,  /// <= GBR based displacement
+	SH_OP_MEM_GBR_R0,    /// <= GBR based R0 indexed
+	SH_OP_MEM_PCR,       /// <= PC relative
+	SH_OP_MEM_TBR_DISP,  /// <= TBR based displaysment
+} sh_op_mem_type;
+
+typedef struct sh_op_mem {
+	sh_op_mem_type address;  /// <= memory address
+	sh_reg reg;              /// <= base register
+	uint32_t disp;           /// <= displacement
+} sh_op_mem;
+
+// SH-DSP instcutions define
+typedef enum sh_dsp_insn_type {
+	SH_INS_DSP_INVALID,
+	SH_INS_DSP_DOUBLE,
+	SH_INS_DSP_SINGLE,
+	SH_INS_DSP_PARALLEL,
+} sh_dsp_insn_type;
+
+typedef enum sh_dsp_insn {
+	SH_INS_DSP_NOP = 1,
+	SH_INS_DSP_MOV,
+	SH_INS_DSP_PSHL,
+	SH_INS_DSP_PSHA,
+	SH_INS_DSP_PMULS,
+	SH_INS_DSP_PCLR_PMULS,
+	SH_INS_DSP_PSUB_PMULS,
+	SH_INS_DSP_PADD_PMULS,
+	SH_INS_DSP_PSUBC,
+	SH_INS_DSP_PADDC,
+	SH_INS_DSP_PCMP,
+	SH_INS_DSP_PABS,
+	SH_INS_DSP_PRND,
+	SH_INS_DSP_PSUB,
+	SH_INS_DSP_PSUBr,
+	SH_INS_DSP_PADD,
+	SH_INS_DSP_PAND,
+	SH_INS_DSP_PXOR,
+	SH_INS_DSP_POR,
+	SH_INS_DSP_PDEC,
+	SH_INS_DSP_PINC,
+	SH_INS_DSP_PCLR,
+	SH_INS_DSP_PDMSB,
+	SH_INS_DSP_PNEG, 
+	SH_INS_DSP_PCOPY,
+	SH_INS_DSP_PSTS,
+	SH_INS_DSP_PLDS,
+	SH_INS_DSP_PSWAP,
+	SH_INS_DSP_PWAD,
+	SH_INS_DSP_PWSB,
+} sh_dsp_insn;
+
+typedef enum sh_dsp_operand {
+	SH_OP_DSP_INVALID,
+	SH_OP_DSP_REG_PRE,
+	SH_OP_DSP_REG_IND,
+	SH_OP_DSP_REG_POST,
+	SH_OP_DSP_REG_INDEX,
+	SH_OP_DSP_REG,
+	SH_OP_DSP_IMM,
+	
+} sh_dsp_operand;
+
+typedef enum sh_dsp_cc {
+	SH_DSP_CC_INVALID,
+	SH_DSP_CC_NONE,
+	SH_DSP_CC_DCT,
+	SH_DSP_CC_DCF,
+} sh_dsp_cc;
+
+typedef struct sh_op_dsp {
+	sh_dsp_insn insn;
+	sh_dsp_operand operand[2];
+	sh_reg r[6];
+	sh_dsp_cc cc;
+	uint8_t imm;
+	int size;
+} sh_op_dsp;
+	
+/// Instruction operand
+typedef struct cs_sh_op {
+	sh_op_type type;
+	union {
+		uint64_t imm;       ///< immediate value for IMM operand
+		sh_reg reg;	    ///< register value for REG operand
+		sh_op_mem mem; 	    ///< data when operand is targeting memory
+		sh_op_dsp dsp;	    ///< dsp instruction
+	};
+} cs_sh_op;
+
+/// SH instruction
+typedef enum sh_insn {
+	SH_INS_INVALID,
+	SH_INS_ADD_r,
+	SH_INS_ADD,
+	SH_INS_ADDC,
+	SH_INS_ADDV,
+	SH_INS_AND,
+	SH_INS_BAND,
+	SH_INS_BANDNOT,
+	SH_INS_BCLR,
+	SH_INS_BF,
+	SH_INS_BF_S,
+	SH_INS_BLD,
+	SH_INS_BLDNOT,
+	SH_INS_BOR,
+	SH_INS_BORNOT,
+	SH_INS_BRA,
+	SH_INS_BRAF,
+	SH_INS_BSET,
+	SH_INS_BSR,
+	SH_INS_BSRF,
+	SH_INS_BST,
+	SH_INS_BT,
+	SH_INS_BT_S,
+	SH_INS_BXOR,
+	SH_INS_CLIPS,
+	SH_INS_CLIPU,
+	SH_INS_CLRDMXY,
+	SH_INS_CLRMAC,
+	SH_INS_CLRS,
+	SH_INS_CLRT,
+	SH_INS_CMP_EQ,
+	SH_INS_CMP_GE,
+	SH_INS_CMP_GT,
+	SH_INS_CMP_HI,
+	SH_INS_CMP_HS,
+	SH_INS_CMP_PL,
+	SH_INS_CMP_PZ,
+	SH_INS_CMP_STR,
+	SH_INS_DIV0S,
+	SH_INS_DIV0U,
+	SH_INS_DIV1,
+	SH_INS_DIVS,
+	SH_INS_DIVU,
+	SH_INS_DMULS_L,
+	SH_INS_DMULU_L,
+	SH_INS_DT,
+	SH_INS_EXTS_B,
+	SH_INS_EXTS_W,
+	SH_INS_EXTU_B,
+	SH_INS_EXTU_W,
+	SH_INS_FABS,
+	SH_INS_FADD,
+	SH_INS_FCMP_EQ,
+	SH_INS_FCMP_GT,
+	SH_INS_FCNVDS,
+	SH_INS_FCNVSD,
+	SH_INS_FDIV,
+	SH_INS_FIPR,
+	SH_INS_FLDI0,
+	SH_INS_FLDI1,
+	SH_INS_FLDS,
+	SH_INS_FLOAT,
+	SH_INS_FMAC,
+	SH_INS_FMOV,
+	SH_INS_FMUL,
+	SH_INS_FNEG,
+	SH_INS_FPCHG,
+	SH_INS_FRCHG,
+	SH_INS_FSCA,
+	SH_INS_FSCHG,
+	SH_INS_FSQRT,
+	SH_INS_FSRRA,
+	SH_INS_FSTS,
+	SH_INS_FSUB,
+	SH_INS_FTRC,
+	SH_INS_FTRV,
+	SH_INS_ICBI,
+	SH_INS_JMP,
+	SH_INS_JSR,
+	SH_INS_JSR_N,
+	SH_INS_LDBANK,
+	SH_INS_LDC,
+	SH_INS_LDRC,
+	SH_INS_LDRE,
+	SH_INS_LDRS,
+	SH_INS_LDS,
+	SH_INS_LDTLB,
+	SH_INS_MAC_L,
+	SH_INS_MAC_W,
+	SH_INS_MOV,
+	SH_INS_MOVA,
+	SH_INS_MOVCA,
+	SH_INS_MOVCO,
+	SH_INS_MOVI20,
+	SH_INS_MOVI20S,
+	SH_INS_MOVLI,
+	SH_INS_MOVML,
+	SH_INS_MOVMU,
+	SH_INS_MOVRT,
+	SH_INS_MOVT,
+	SH_INS_MOVU,
+	SH_INS_MOVUA,
+	SH_INS_MUL_L,
+	SH_INS_MULR,
+	SH_INS_MULS_W,
+	SH_INS_MULU_W,
+	SH_INS_NEG,
+	SH_INS_NEGC,
+	SH_INS_NOP,
+	SH_INS_NOT,
+	SH_INS_NOTT,
+	SH_INS_OCBI,
+	SH_INS_OCBP,
+	SH_INS_OCBWB,
+	SH_INS_OR,
+	SH_INS_PREF,
+	SH_INS_PREFI,
+	SH_INS_RESBANK,
+	SH_INS_ROTCL,
+	SH_INS_ROTCR,
+	SH_INS_ROTL,
+	SH_INS_ROTR,
+	SH_INS_RTE,
+	SH_INS_RTS,
+	SH_INS_RTS_N,
+	SH_INS_RTV_N,
+	SH_INS_SETDMX,
+	SH_INS_SETDMY,
+	SH_INS_SETRC,
+	SH_INS_SETS,
+	SH_INS_SETT,
+	SH_INS_SHAD,
+	SH_INS_SHAL,
+	SH_INS_SHAR,
+	SH_INS_SHLD,
+	SH_INS_SHLL,
+	SH_INS_SHLL16,
+	SH_INS_SHLL2,
+	SH_INS_SHLL8,
+	SH_INS_SHLR,
+	SH_INS_SHLR16,
+	SH_INS_SHLR2,
+	SH_INS_SHLR8,
+	SH_INS_SLEEP,
+	SH_INS_STBANK,
+	SH_INS_STC,
+	SH_INS_STS,
+	SH_INS_SUB,
+	SH_INS_SUBC,
+	SH_INS_SUBV,
+	SH_INS_SWAP_B,
+	SH_INS_SWAP_W,
+	SH_INS_SYNCO,
+	SH_INS_TAS,
+	SH_INS_TRAPA,
+	SH_INS_TST,
+	SH_INS_XOR,
+	SH_INS_XTRCT,
+	SH_INS_DSP,
+	SH_INS_ENDING,   // <-- mark the end of the list of instructions
+} sh_insn;
+
+/// Instruction structure
+typedef struct cs_sh {
+	sh_insn insn;
+	uint8_t size;
+	uint8_t op_count;
+	cs_sh_op operands[3];
+} cs_sh;
+
+/// Group of SH instructions
+typedef enum sh_insn_group {
+	SH_GRP_INVALID = 0,  ///< CS_GRUP_INVALID
+	SH_GRP_JUMP,  ///< = CS_GRP_JUMP
+	SH_GRP_CALL,  ///< = CS_GRP_CALL
+	SH_GRP_INT,  ///< = CS_GRP_INT
+	SH_GRP_RET,  ///< = CS_GRP_RET
+	SH_GRP_IRET, ///< = CS_GRP_IRET
+        SH_GRP_PRIVILEGE,     ///< = CS_GRP_PRIVILEGE
+	SH_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
+
+	SH_GRP_SH1,
+	SH_GRP_SH2,
+	SH_GRP_SH2E,
+	SH_GRP_SH2DSP,
+	SH_GRP_SH2A,
+	SH_GRP_SH2AFPU,
+	SH_GRP_SH3,
+	SH_GRP_SH3DSP,
+	SH_GRP_SH4,
+	SH_GRP_SH4A,
+	
+	SH_GRP_ENDING,// <-- mark the end of the list of groups
+} sh_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

.tools/python-revlibs/capstone/include/capstone/sparc.h

@@ -0,0 +1,520 @@
+#ifndef CAPSTONE_SPARC_H
+#define CAPSTONE_SPARC_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+// GCC SPARC toolchain has a default macro called "sparc" which breaks
+// compilation
+#undef sparc
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// Enums corresponding to Sparc condition codes, both icc's and fcc's.
+typedef enum sparc_cc {
+	SPARC_CC_INVALID = 0,	///< invalid CC (default)
+	// Integer condition codes
+	SPARC_CC_ICC_A   =  8+256,  ///< Always
+	SPARC_CC_ICC_N   =  0+256,  ///< Never
+	SPARC_CC_ICC_NE  =  9+256,  ///< Not Equal
+	SPARC_CC_ICC_E   =  1+256,  ///< Equal
+	SPARC_CC_ICC_G   = 10+256,  ///< Greater
+	SPARC_CC_ICC_LE  =  2+256,  ///< Less or Equal
+	SPARC_CC_ICC_GE  = 11+256,  ///< Greater or Equal
+	SPARC_CC_ICC_L   =  3+256,  ///< Less
+	SPARC_CC_ICC_GU  = 12+256,  ///< Greater Unsigned
+	SPARC_CC_ICC_LEU =  4+256,  ///< Less or Equal Unsigned
+	SPARC_CC_ICC_CC  = 13+256,  ///< Carry Clear/Great or Equal Unsigned
+	SPARC_CC_ICC_CS  =  5+256,  ///< Carry Set/Less Unsigned
+	SPARC_CC_ICC_POS = 14+256,  ///< Positive
+	SPARC_CC_ICC_NEG =  6+256,  ///< Negative
+	SPARC_CC_ICC_VC  = 15+256,  ///< Overflow Clear
+	SPARC_CC_ICC_VS  =  7+256,  ///< Overflow Set
+
+	// Floating condition codes
+	SPARC_CC_FCC_A   =  8+16+256,  ///< Always
+	SPARC_CC_FCC_N   =  0+16+256,  ///< Never
+	SPARC_CC_FCC_U   =  7+16+256,  ///< Unordered
+	SPARC_CC_FCC_G   =  6+16+256,  ///< Greater
+	SPARC_CC_FCC_UG  =  5+16+256,  ///< Unordered or Greater
+	SPARC_CC_FCC_L   =  4+16+256,  ///< Less
+	SPARC_CC_FCC_UL  =  3+16+256,  ///< Unordered or Less
+	SPARC_CC_FCC_LG  =  2+16+256,  ///< Less or Greater
+	SPARC_CC_FCC_NE  =  1+16+256,  ///< Not Equal
+	SPARC_CC_FCC_E   =  9+16+256,  ///< Equal
+	SPARC_CC_FCC_UE  = 10+16+256,  ///< Unordered or Equal
+	SPARC_CC_FCC_GE  = 11+16+256,  ///< Greater or Equal
+	SPARC_CC_FCC_UGE = 12+16+256,  ///< Unordered or Greater or Equal
+	SPARC_CC_FCC_LE  = 13+16+256,  ///< Less or Equal
+	SPARC_CC_FCC_ULE = 14+16+256,  ///< Unordered or Less or Equal
+	SPARC_CC_FCC_O   = 15+16+256,  ///< Ordered
+} sparc_cc;
+
+/// Branch hint
+typedef enum sparc_hint {
+	SPARC_HINT_INVALID = 0,	///< no hint
+	SPARC_HINT_A	= 1 << 0,	///< annul delay slot instruction
+	SPARC_HINT_PT	= 1 << 1,	///< branch taken
+	SPARC_HINT_PN	= 1 << 2,	///< branch NOT taken
+} sparc_hint;
+
+/// Operand type for instruction's operands
+typedef enum sparc_op_type {
+	SPARC_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+	SPARC_OP_REG, ///< = CS_OP_REG (Register operand).
+	SPARC_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	SPARC_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+} sparc_op_type;
+
+/// SPARC registers
+typedef enum sparc_reg {
+	SPARC_REG_INVALID = 0,
+
+	SPARC_REG_F0,
+	SPARC_REG_F1,
+	SPARC_REG_F2,
+	SPARC_REG_F3,
+	SPARC_REG_F4,
+	SPARC_REG_F5,
+	SPARC_REG_F6,
+	SPARC_REG_F7,
+	SPARC_REG_F8,
+	SPARC_REG_F9,
+	SPARC_REG_F10,
+	SPARC_REG_F11,
+	SPARC_REG_F12,
+	SPARC_REG_F13,
+	SPARC_REG_F14,
+	SPARC_REG_F15,
+	SPARC_REG_F16,
+	SPARC_REG_F17,
+	SPARC_REG_F18,
+	SPARC_REG_F19,
+	SPARC_REG_F20,
+	SPARC_REG_F21,
+	SPARC_REG_F22,
+	SPARC_REG_F23,
+	SPARC_REG_F24,
+	SPARC_REG_F25,
+	SPARC_REG_F26,
+	SPARC_REG_F27,
+	SPARC_REG_F28,
+	SPARC_REG_F29,
+	SPARC_REG_F30,
+	SPARC_REG_F31,
+	SPARC_REG_F32,
+	SPARC_REG_F34,
+	SPARC_REG_F36,
+	SPARC_REG_F38,
+	SPARC_REG_F40,
+	SPARC_REG_F42,
+	SPARC_REG_F44,
+	SPARC_REG_F46,
+	SPARC_REG_F48,
+	SPARC_REG_F50,
+	SPARC_REG_F52,
+	SPARC_REG_F54,
+	SPARC_REG_F56,
+	SPARC_REG_F58,
+	SPARC_REG_F60,
+	SPARC_REG_F62,
+	SPARC_REG_FCC0,	// Floating condition codes
+	SPARC_REG_FCC1,
+	SPARC_REG_FCC2,
+	SPARC_REG_FCC3,
+	SPARC_REG_FP,
+	SPARC_REG_G0,
+	SPARC_REG_G1,
+	SPARC_REG_G2,
+	SPARC_REG_G3,
+	SPARC_REG_G4,
+	SPARC_REG_G5,
+	SPARC_REG_G6,
+	SPARC_REG_G7,
+	SPARC_REG_I0,
+	SPARC_REG_I1,
+	SPARC_REG_I2,
+	SPARC_REG_I3,
+	SPARC_REG_I4,
+	SPARC_REG_I5,
+	SPARC_REG_I7,
+	SPARC_REG_ICC,	// Integer condition codes
+	SPARC_REG_L0,
+	SPARC_REG_L1,
+	SPARC_REG_L2,
+	SPARC_REG_L3,
+	SPARC_REG_L4,
+	SPARC_REG_L5,
+	SPARC_REG_L6,
+	SPARC_REG_L7,
+	SPARC_REG_O0,
+	SPARC_REG_O1,
+	SPARC_REG_O2,
+	SPARC_REG_O3,
+	SPARC_REG_O4,
+	SPARC_REG_O5,
+	SPARC_REG_O7,
+	SPARC_REG_SP,
+	SPARC_REG_Y,
+
+	// special register
+	SPARC_REG_XCC,
+
+	SPARC_REG_ENDING,   // <-- mark the end of the list of registers
+
+	// extras
+	SPARC_REG_O6 = SPARC_REG_SP,
+	SPARC_REG_I6 = SPARC_REG_FP,
+} sparc_reg;
+
+/// Instruction's operand referring to memory
+/// This is associated with SPARC_OP_MEM operand type above
+typedef struct sparc_op_mem {
+	uint8_t base;		///< base register, can be safely interpreted as
+				///< a value of type `sparc_reg`, but it is only
+				///< one byte wide
+	uint8_t index;		///< index register, same conditions apply here
+	int32_t disp;		///< displacement/offset value
+} sparc_op_mem;
+
+/// Instruction operand
+typedef struct cs_sparc_op {
+	sparc_op_type type;	///< operand type
+	union {
+		sparc_reg reg;	///< register value for REG operand
+		int64_t imm;		///< immediate value for IMM operand
+		sparc_op_mem mem;		///< base/disp value for MEM operand
+	};
+} cs_sparc_op;
+
+/// Instruction structure
+typedef struct cs_sparc {
+	sparc_cc cc;	///< code condition for this insn
+	sparc_hint hint;	///< branch hint: encoding as bitwise OR of sparc_hint.
+	/// Number of operands of this instruction,
+	/// or 0 when instruction has no operand.
+	uint8_t op_count;
+	cs_sparc_op operands[4]; ///< operands for this instruction.
+} cs_sparc;
+
+/// SPARC instruction
+typedef enum sparc_insn {
+	SPARC_INS_INVALID = 0,
+
+	SPARC_INS_ADDCC,
+	SPARC_INS_ADDX,
+	SPARC_INS_ADDXCC,
+	SPARC_INS_ADDXC,
+	SPARC_INS_ADDXCCC,
+	SPARC_INS_ADD,
+	SPARC_INS_ALIGNADDR,
+	SPARC_INS_ALIGNADDRL,
+	SPARC_INS_ANDCC,
+	SPARC_INS_ANDNCC,
+	SPARC_INS_ANDN,
+	SPARC_INS_AND,
+	SPARC_INS_ARRAY16,
+	SPARC_INS_ARRAY32,
+	SPARC_INS_ARRAY8,
+	SPARC_INS_B,
+	SPARC_INS_JMP,
+	SPARC_INS_BMASK,
+	SPARC_INS_FB,
+	SPARC_INS_BRGEZ,
+	SPARC_INS_BRGZ,
+	SPARC_INS_BRLEZ,
+	SPARC_INS_BRLZ,
+	SPARC_INS_BRNZ,
+	SPARC_INS_BRZ,
+	SPARC_INS_BSHUFFLE,
+	SPARC_INS_CALL,
+	SPARC_INS_CASX,
+	SPARC_INS_CAS,
+	SPARC_INS_CMASK16,
+	SPARC_INS_CMASK32,
+	SPARC_INS_CMASK8,
+	SPARC_INS_CMP,
+	SPARC_INS_EDGE16,
+	SPARC_INS_EDGE16L,
+	SPARC_INS_EDGE16LN,
+	SPARC_INS_EDGE16N,
+	SPARC_INS_EDGE32,
+	SPARC_INS_EDGE32L,
+	SPARC_INS_EDGE32LN,
+	SPARC_INS_EDGE32N,
+	SPARC_INS_EDGE8,
+	SPARC_INS_EDGE8L,
+	SPARC_INS_EDGE8LN,
+	SPARC_INS_EDGE8N,
+	SPARC_INS_FABSD,
+	SPARC_INS_FABSQ,
+	SPARC_INS_FABSS,
+	SPARC_INS_FADDD,
+	SPARC_INS_FADDQ,
+	SPARC_INS_FADDS,
+	SPARC_INS_FALIGNDATA,
+	SPARC_INS_FAND,
+	SPARC_INS_FANDNOT1,
+	SPARC_INS_FANDNOT1S,
+	SPARC_INS_FANDNOT2,
+	SPARC_INS_FANDNOT2S,
+	SPARC_INS_FANDS,
+	SPARC_INS_FCHKSM16,
+	SPARC_INS_FCMPD,
+	SPARC_INS_FCMPEQ16,
+	SPARC_INS_FCMPEQ32,
+	SPARC_INS_FCMPGT16,
+	SPARC_INS_FCMPGT32,
+	SPARC_INS_FCMPLE16,
+	SPARC_INS_FCMPLE32,
+	SPARC_INS_FCMPNE16,
+	SPARC_INS_FCMPNE32,
+	SPARC_INS_FCMPQ,
+	SPARC_INS_FCMPS,
+	SPARC_INS_FDIVD,
+	SPARC_INS_FDIVQ,
+	SPARC_INS_FDIVS,
+	SPARC_INS_FDMULQ,
+	SPARC_INS_FDTOI,
+	SPARC_INS_FDTOQ,
+	SPARC_INS_FDTOS,
+	SPARC_INS_FDTOX,
+	SPARC_INS_FEXPAND,
+	SPARC_INS_FHADDD,
+	SPARC_INS_FHADDS,
+	SPARC_INS_FHSUBD,
+	SPARC_INS_FHSUBS,
+	SPARC_INS_FITOD,
+	SPARC_INS_FITOQ,
+	SPARC_INS_FITOS,
+	SPARC_INS_FLCMPD,
+	SPARC_INS_FLCMPS,
+	SPARC_INS_FLUSHW,
+	SPARC_INS_FMEAN16,
+	SPARC_INS_FMOVD,
+	SPARC_INS_FMOVQ,
+	SPARC_INS_FMOVRDGEZ,
+	SPARC_INS_FMOVRQGEZ,
+	SPARC_INS_FMOVRSGEZ,
+	SPARC_INS_FMOVRDGZ,
+	SPARC_INS_FMOVRQGZ,
+	SPARC_INS_FMOVRSGZ,
+	SPARC_INS_FMOVRDLEZ,
+	SPARC_INS_FMOVRQLEZ,
+	SPARC_INS_FMOVRSLEZ,
+	SPARC_INS_FMOVRDLZ,
+	SPARC_INS_FMOVRQLZ,
+	SPARC_INS_FMOVRSLZ,
+	SPARC_INS_FMOVRDNZ,
+	SPARC_INS_FMOVRQNZ,
+	SPARC_INS_FMOVRSNZ,
+	SPARC_INS_FMOVRDZ,
+	SPARC_INS_FMOVRQZ,
+	SPARC_INS_FMOVRSZ,
+	SPARC_INS_FMOVS,
+	SPARC_INS_FMUL8SUX16,
+	SPARC_INS_FMUL8ULX16,
+	SPARC_INS_FMUL8X16,
+	SPARC_INS_FMUL8X16AL,
+	SPARC_INS_FMUL8X16AU,
+	SPARC_INS_FMULD,
+	SPARC_INS_FMULD8SUX16,
+	SPARC_INS_FMULD8ULX16,
+	SPARC_INS_FMULQ,
+	SPARC_INS_FMULS,
+	SPARC_INS_FNADDD,
+	SPARC_INS_FNADDS,
+	SPARC_INS_FNAND,
+	SPARC_INS_FNANDS,
+	SPARC_INS_FNEGD,
+	SPARC_INS_FNEGQ,
+	SPARC_INS_FNEGS,
+	SPARC_INS_FNHADDD,
+	SPARC_INS_FNHADDS,
+	SPARC_INS_FNOR,
+	SPARC_INS_FNORS,
+	SPARC_INS_FNOT1,
+	SPARC_INS_FNOT1S,
+	SPARC_INS_FNOT2,
+	SPARC_INS_FNOT2S,
+	SPARC_INS_FONE,
+	SPARC_INS_FONES,
+	SPARC_INS_FOR,
+	SPARC_INS_FORNOT1,
+	SPARC_INS_FORNOT1S,
+	SPARC_INS_FORNOT2,
+	SPARC_INS_FORNOT2S,
+	SPARC_INS_FORS,
+	SPARC_INS_FPACK16,
+	SPARC_INS_FPACK32,
+	SPARC_INS_FPACKFIX,
+	SPARC_INS_FPADD16,
+	SPARC_INS_FPADD16S,
+	SPARC_INS_FPADD32,
+	SPARC_INS_FPADD32S,
+	SPARC_INS_FPADD64,
+	SPARC_INS_FPMERGE,
+	SPARC_INS_FPSUB16,
+	SPARC_INS_FPSUB16S,
+	SPARC_INS_FPSUB32,
+	SPARC_INS_FPSUB32S,
+	SPARC_INS_FQTOD,
+	SPARC_INS_FQTOI,
+	SPARC_INS_FQTOS,
+	SPARC_INS_FQTOX,
+	SPARC_INS_FSLAS16,
+	SPARC_INS_FSLAS32,
+	SPARC_INS_FSLL16,
+	SPARC_INS_FSLL32,
+	SPARC_INS_FSMULD,
+	SPARC_INS_FSQRTD,
+	SPARC_INS_FSQRTQ,
+	SPARC_INS_FSQRTS,
+	SPARC_INS_FSRA16,
+	SPARC_INS_FSRA32,
+	SPARC_INS_FSRC1,
+	SPARC_INS_FSRC1S,
+	SPARC_INS_FSRC2,
+	SPARC_INS_FSRC2S,
+	SPARC_INS_FSRL16,
+	SPARC_INS_FSRL32,
+	SPARC_INS_FSTOD,
+	SPARC_INS_FSTOI,
+	SPARC_INS_FSTOQ,
+	SPARC_INS_FSTOX,
+	SPARC_INS_FSUBD,
+	SPARC_INS_FSUBQ,
+	SPARC_INS_FSUBS,
+	SPARC_INS_FXNOR,
+	SPARC_INS_FXNORS,
+	SPARC_INS_FXOR,
+	SPARC_INS_FXORS,
+	SPARC_INS_FXTOD,
+	SPARC_INS_FXTOQ,
+	SPARC_INS_FXTOS,
+	SPARC_INS_FZERO,
+	SPARC_INS_FZEROS,
+	SPARC_INS_JMPL,
+	SPARC_INS_LDD,
+	SPARC_INS_LD,
+	SPARC_INS_LDQ,
+	SPARC_INS_LDSB,
+	SPARC_INS_LDSH,
+	SPARC_INS_LDSW,
+	SPARC_INS_LDUB,
+	SPARC_INS_LDUH,
+	SPARC_INS_LDX,
+	SPARC_INS_LZCNT,
+	SPARC_INS_MEMBAR,
+	SPARC_INS_MOVDTOX,
+	SPARC_INS_MOV,
+	SPARC_INS_MOVRGEZ,
+	SPARC_INS_MOVRGZ,
+	SPARC_INS_MOVRLEZ,
+	SPARC_INS_MOVRLZ,
+	SPARC_INS_MOVRNZ,
+	SPARC_INS_MOVRZ,
+	SPARC_INS_MOVSTOSW,
+	SPARC_INS_MOVSTOUW,
+	SPARC_INS_MULX,
+	SPARC_INS_NOP,
+	SPARC_INS_ORCC,
+	SPARC_INS_ORNCC,
+	SPARC_INS_ORN,
+	SPARC_INS_OR,
+	SPARC_INS_PDIST,
+	SPARC_INS_PDISTN,
+	SPARC_INS_POPC,
+	SPARC_INS_RD,
+	SPARC_INS_RESTORE,
+	SPARC_INS_RETT,
+	SPARC_INS_SAVE,
+	SPARC_INS_SDIVCC,
+	SPARC_INS_SDIVX,
+	SPARC_INS_SDIV,
+	SPARC_INS_SETHI,
+	SPARC_INS_SHUTDOWN,
+	SPARC_INS_SIAM,
+	SPARC_INS_SLLX,
+	SPARC_INS_SLL,
+	SPARC_INS_SMULCC,
+	SPARC_INS_SMUL,
+	SPARC_INS_SRAX,
+	SPARC_INS_SRA,
+	SPARC_INS_SRLX,
+	SPARC_INS_SRL,
+	SPARC_INS_STBAR,
+	SPARC_INS_STB,
+	SPARC_INS_STD,
+	SPARC_INS_ST,
+	SPARC_INS_STH,
+	SPARC_INS_STQ,
+	SPARC_INS_STX,
+	SPARC_INS_SUBCC,
+	SPARC_INS_SUBX,
+	SPARC_INS_SUBXCC,
+	SPARC_INS_SUB,
+	SPARC_INS_SWAP,
+	SPARC_INS_TADDCCTV,
+	SPARC_INS_TADDCC,
+	SPARC_INS_T,
+	SPARC_INS_TSUBCCTV,
+	SPARC_INS_TSUBCC,
+	SPARC_INS_UDIVCC,
+	SPARC_INS_UDIVX,
+	SPARC_INS_UDIV,
+	SPARC_INS_UMULCC,
+	SPARC_INS_UMULXHI,
+	SPARC_INS_UMUL,
+	SPARC_INS_UNIMP,
+	SPARC_INS_FCMPED,
+	SPARC_INS_FCMPEQ,
+	SPARC_INS_FCMPES,
+	SPARC_INS_WR,
+	SPARC_INS_XMULX,
+	SPARC_INS_XMULXHI,
+	SPARC_INS_XNORCC,
+	SPARC_INS_XNOR,
+	SPARC_INS_XORCC,
+	SPARC_INS_XOR,
+
+	// alias instructions
+	SPARC_INS_RET,
+	SPARC_INS_RETL,
+
+	SPARC_INS_ENDING,   // <-- mark the end of the list of instructions
+} sparc_insn;
+
+/// Group of SPARC instructions
+typedef enum sparc_insn_group {
+	SPARC_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+	// Generic groups
+	// all jump instructions (conditional+direct+indirect jumps)
+	SPARC_GRP_JUMP,	///< = CS_GRP_JUMP
+
+	// Architecture-specific groups
+	SPARC_GRP_HARDQUAD = 128,
+	SPARC_GRP_V9,
+	SPARC_GRP_VIS,
+	SPARC_GRP_VIS2,
+	SPARC_GRP_VIS3, 
+	SPARC_GRP_32BIT,
+	SPARC_GRP_64BIT,
+
+	SPARC_GRP_ENDING,   // <-- mark the end of the list of groups
+} sparc_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

.tools/python-revlibs/capstone/include/capstone/tms320c64x.h

@@ -0,0 +1,359 @@
+/* Capstone Disassembly Engine */
+/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
+
+#ifndef CAPSTONE_TMS320C64X_H
+#define CAPSTONE_TMS320C64X_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+typedef enum tms320c64x_op_type {
+	TMS320C64X_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+	TMS320C64X_OP_REG, ///< = CS_OP_REG (Register operand).
+	TMS320C64X_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	TMS320C64X_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+	TMS320C64X_OP_REGPAIR = 64, ///< Register pair for double word ops
+} tms320c64x_op_type;
+
+typedef enum tms320c64x_mem_disp {
+	TMS320C64X_MEM_DISP_INVALID = 0,
+	TMS320C64X_MEM_DISP_CONSTANT,
+	TMS320C64X_MEM_DISP_REGISTER,
+} tms320c64x_mem_disp;
+
+typedef enum tms320c64x_mem_dir {
+	TMS320C64X_MEM_DIR_INVALID = 0,
+	TMS320C64X_MEM_DIR_FW,
+	TMS320C64X_MEM_DIR_BW,
+} tms320c64x_mem_dir;
+
+typedef enum tms320c64x_mem_mod {
+	TMS320C64X_MEM_MOD_INVALID = 0,
+	TMS320C64X_MEM_MOD_NO,
+	TMS320C64X_MEM_MOD_PRE,
+	TMS320C64X_MEM_MOD_POST,
+} tms320c64x_mem_mod;
+
+typedef struct tms320c64x_op_mem {
+	unsigned int	base;	///< base register
+	unsigned int	disp;	///< displacement/offset value
+	unsigned int	unit;	///< unit of base and offset register
+	unsigned int	scaled;	///< offset scaled
+	unsigned int	disptype;	///< displacement type
+	unsigned int	direction;	///< direction
+	unsigned int	modify;	///< modification
+} tms320c64x_op_mem;
+
+typedef struct cs_tms320c64x_op {
+	tms320c64x_op_type type;	///< operand type
+	union {
+		unsigned int reg;	///< register value for REG operand or first register for REGPAIR operand
+		int32_t imm;		///< immediate value for IMM operand
+		tms320c64x_op_mem mem;		///< base/disp value for MEM operand
+	};
+} cs_tms320c64x_op;
+
+typedef struct cs_tms320c64x {
+	uint8_t op_count;
+	cs_tms320c64x_op operands[8]; ///< operands for this instruction.
+	struct {
+		unsigned int reg;
+		unsigned int zero;
+	} condition;
+	struct {
+		unsigned int unit;
+		unsigned int side;
+		unsigned int crosspath;
+	} funit;
+	unsigned int parallel;
+} cs_tms320c64x;
+
+typedef enum tms320c64x_reg {
+	TMS320C64X_REG_INVALID = 0,
+
+	TMS320C64X_REG_AMR,
+	TMS320C64X_REG_CSR,
+	TMS320C64X_REG_DIER,
+	TMS320C64X_REG_DNUM,
+	TMS320C64X_REG_ECR,
+	TMS320C64X_REG_GFPGFR,
+	TMS320C64X_REG_GPLYA,
+	TMS320C64X_REG_GPLYB,
+	TMS320C64X_REG_ICR,
+	TMS320C64X_REG_IER,
+	TMS320C64X_REG_IERR,
+	TMS320C64X_REG_ILC,
+	TMS320C64X_REG_IRP,
+	TMS320C64X_REG_ISR,
+	TMS320C64X_REG_ISTP,
+	TMS320C64X_REG_ITSR,
+	TMS320C64X_REG_NRP,
+	TMS320C64X_REG_NTSR,
+	TMS320C64X_REG_REP,
+	TMS320C64X_REG_RILC,
+	TMS320C64X_REG_SSR,
+	TMS320C64X_REG_TSCH,
+	TMS320C64X_REG_TSCL,
+	TMS320C64X_REG_TSR,
+	TMS320C64X_REG_A0,
+	TMS320C64X_REG_A1,
+	TMS320C64X_REG_A2,
+	TMS320C64X_REG_A3,
+	TMS320C64X_REG_A4,
+	TMS320C64X_REG_A5,
+	TMS320C64X_REG_A6,
+	TMS320C64X_REG_A7,
+	TMS320C64X_REG_A8,
+	TMS320C64X_REG_A9,
+	TMS320C64X_REG_A10,
+	TMS320C64X_REG_A11,
+	TMS320C64X_REG_A12,
+	TMS320C64X_REG_A13,
+	TMS320C64X_REG_A14,
+	TMS320C64X_REG_A15,
+	TMS320C64X_REG_A16,
+	TMS320C64X_REG_A17,
+	TMS320C64X_REG_A18,
+	TMS320C64X_REG_A19,
+	TMS320C64X_REG_A20,
+	TMS320C64X_REG_A21,
+	TMS320C64X_REG_A22,
+	TMS320C64X_REG_A23,
+	TMS320C64X_REG_A24,
+	TMS320C64X_REG_A25,
+	TMS320C64X_REG_A26,
+	TMS320C64X_REG_A27,
+	TMS320C64X_REG_A28,
+	TMS320C64X_REG_A29,
+	TMS320C64X_REG_A30,
+	TMS320C64X_REG_A31,
+	TMS320C64X_REG_B0,
+	TMS320C64X_REG_B1,
+	TMS320C64X_REG_B2,
+	TMS320C64X_REG_B3,
+	TMS320C64X_REG_B4,
+	TMS320C64X_REG_B5,
+	TMS320C64X_REG_B6,
+	TMS320C64X_REG_B7,
+	TMS320C64X_REG_B8,
+	TMS320C64X_REG_B9,
+	TMS320C64X_REG_B10,
+	TMS320C64X_REG_B11,
+	TMS320C64X_REG_B12,
+	TMS320C64X_REG_B13,
+	TMS320C64X_REG_B14,
+	TMS320C64X_REG_B15,
+	TMS320C64X_REG_B16,
+	TMS320C64X_REG_B17,
+	TMS320C64X_REG_B18,
+	TMS320C64X_REG_B19,
+	TMS320C64X_REG_B20,
+	TMS320C64X_REG_B21,
+	TMS320C64X_REG_B22,
+	TMS320C64X_REG_B23,
+	TMS320C64X_REG_B24,
+	TMS320C64X_REG_B25,
+	TMS320C64X_REG_B26,
+	TMS320C64X_REG_B27,
+	TMS320C64X_REG_B28,
+	TMS320C64X_REG_B29,
+	TMS320C64X_REG_B30,
+	TMS320C64X_REG_B31,
+	TMS320C64X_REG_PCE1,
+
+	TMS320C64X_REG_ENDING,	// <-- mark the end of the list of registers
+
+	// Alias registers
+	TMS320C64X_REG_EFR = TMS320C64X_REG_ECR,
+	TMS320C64X_REG_IFR = TMS320C64X_REG_ISR,
+} tms320c64x_reg;
+
+typedef enum tms320c64x_insn {
+	TMS320C64X_INS_INVALID = 0,
+
+	TMS320C64X_INS_ABS,
+	TMS320C64X_INS_ABS2,
+	TMS320C64X_INS_ADD,
+	TMS320C64X_INS_ADD2,
+	TMS320C64X_INS_ADD4,
+	TMS320C64X_INS_ADDAB,
+	TMS320C64X_INS_ADDAD,
+	TMS320C64X_INS_ADDAH,
+	TMS320C64X_INS_ADDAW,
+	TMS320C64X_INS_ADDK,
+	TMS320C64X_INS_ADDKPC,
+	TMS320C64X_INS_ADDU,
+	TMS320C64X_INS_AND,
+	TMS320C64X_INS_ANDN,
+	TMS320C64X_INS_AVG2,
+	TMS320C64X_INS_AVGU4,
+	TMS320C64X_INS_B,
+	TMS320C64X_INS_BDEC,
+	TMS320C64X_INS_BITC4,
+	TMS320C64X_INS_BNOP,
+	TMS320C64X_INS_BPOS,
+	TMS320C64X_INS_CLR,
+	TMS320C64X_INS_CMPEQ,
+	TMS320C64X_INS_CMPEQ2,
+	TMS320C64X_INS_CMPEQ4,
+	TMS320C64X_INS_CMPGT,
+	TMS320C64X_INS_CMPGT2,
+	TMS320C64X_INS_CMPGTU4,
+	TMS320C64X_INS_CMPLT,
+	TMS320C64X_INS_CMPLTU,
+	TMS320C64X_INS_DEAL,
+	TMS320C64X_INS_DOTP2,
+	TMS320C64X_INS_DOTPN2,
+	TMS320C64X_INS_DOTPNRSU2,
+	TMS320C64X_INS_DOTPRSU2,
+	TMS320C64X_INS_DOTPSU4,
+	TMS320C64X_INS_DOTPU4,
+	TMS320C64X_INS_EXT,
+	TMS320C64X_INS_EXTU,
+	TMS320C64X_INS_GMPGTU,
+	TMS320C64X_INS_GMPY4,
+	TMS320C64X_INS_LDB,
+	TMS320C64X_INS_LDBU,
+	TMS320C64X_INS_LDDW,
+	TMS320C64X_INS_LDH,
+	TMS320C64X_INS_LDHU,
+	TMS320C64X_INS_LDNDW,
+	TMS320C64X_INS_LDNW,
+	TMS320C64X_INS_LDW,
+	TMS320C64X_INS_LMBD,
+	TMS320C64X_INS_MAX2,
+	TMS320C64X_INS_MAXU4,
+	TMS320C64X_INS_MIN2,
+	TMS320C64X_INS_MINU4,
+	TMS320C64X_INS_MPY,
+	TMS320C64X_INS_MPY2,
+	TMS320C64X_INS_MPYH,
+	TMS320C64X_INS_MPYHI,
+	TMS320C64X_INS_MPYHIR,
+	TMS320C64X_INS_MPYHL,
+	TMS320C64X_INS_MPYHLU,
+	TMS320C64X_INS_MPYHSLU,
+	TMS320C64X_INS_MPYHSU,
+	TMS320C64X_INS_MPYHU,
+	TMS320C64X_INS_MPYHULS,
+	TMS320C64X_INS_MPYHUS,
+	TMS320C64X_INS_MPYLH,
+	TMS320C64X_INS_MPYLHU,
+	TMS320C64X_INS_MPYLI,
+	TMS320C64X_INS_MPYLIR,
+	TMS320C64X_INS_MPYLSHU,
+	TMS320C64X_INS_MPYLUHS,
+	TMS320C64X_INS_MPYSU,
+	TMS320C64X_INS_MPYSU4,
+	TMS320C64X_INS_MPYU,
+	TMS320C64X_INS_MPYU4,
+	TMS320C64X_INS_MPYUS,
+	TMS320C64X_INS_MVC,
+	TMS320C64X_INS_MVD,
+	TMS320C64X_INS_MVK,
+	TMS320C64X_INS_MVKL,
+	TMS320C64X_INS_MVKLH,
+	TMS320C64X_INS_NOP,
+	TMS320C64X_INS_NORM,
+	TMS320C64X_INS_OR,
+	TMS320C64X_INS_PACK2,
+	TMS320C64X_INS_PACKH2,
+	TMS320C64X_INS_PACKH4,
+	TMS320C64X_INS_PACKHL2,
+	TMS320C64X_INS_PACKL4,
+	TMS320C64X_INS_PACKLH2,
+	TMS320C64X_INS_ROTL,
+	TMS320C64X_INS_SADD,
+	TMS320C64X_INS_SADD2,
+	TMS320C64X_INS_SADDU4,
+	TMS320C64X_INS_SADDUS2,
+	TMS320C64X_INS_SAT,
+	TMS320C64X_INS_SET,
+	TMS320C64X_INS_SHFL,
+	TMS320C64X_INS_SHL,
+	TMS320C64X_INS_SHLMB,
+	TMS320C64X_INS_SHR,
+	TMS320C64X_INS_SHR2,
+	TMS320C64X_INS_SHRMB,
+	TMS320C64X_INS_SHRU,
+	TMS320C64X_INS_SHRU2,
+	TMS320C64X_INS_SMPY,
+	TMS320C64X_INS_SMPY2,
+	TMS320C64X_INS_SMPYH,
+	TMS320C64X_INS_SMPYHL,
+	TMS320C64X_INS_SMPYLH,
+	TMS320C64X_INS_SPACK2,
+	TMS320C64X_INS_SPACKU4,
+	TMS320C64X_INS_SSHL,
+	TMS320C64X_INS_SSHVL,
+	TMS320C64X_INS_SSHVR,
+	TMS320C64X_INS_SSUB,
+	TMS320C64X_INS_STB,
+	TMS320C64X_INS_STDW,
+	TMS320C64X_INS_STH,
+	TMS320C64X_INS_STNDW,
+	TMS320C64X_INS_STNW,
+	TMS320C64X_INS_STW,
+	TMS320C64X_INS_SUB,
+	TMS320C64X_INS_SUB2,
+	TMS320C64X_INS_SUB4,
+	TMS320C64X_INS_SUBAB,
+	TMS320C64X_INS_SUBABS4,
+	TMS320C64X_INS_SUBAH,
+	TMS320C64X_INS_SUBAW,
+	TMS320C64X_INS_SUBC,
+	TMS320C64X_INS_SUBU,
+	TMS320C64X_INS_SWAP4,
+	TMS320C64X_INS_UNPKHU4,
+	TMS320C64X_INS_UNPKLU4,
+	TMS320C64X_INS_XOR,
+	TMS320C64X_INS_XPND2,
+	TMS320C64X_INS_XPND4,
+	// Aliases
+	TMS320C64X_INS_IDLE,
+	TMS320C64X_INS_MV,
+	TMS320C64X_INS_NEG,
+	TMS320C64X_INS_NOT,
+	TMS320C64X_INS_SWAP2,
+	TMS320C64X_INS_ZERO,
+
+	TMS320C64X_INS_ENDING,   // <-- mark the end of the list of instructions
+} tms320c64x_insn;
+
+typedef enum tms320c64x_insn_group {
+	TMS320C64X_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+	TMS320C64X_GRP_JUMP,	///< = CS_GRP_JUMP
+
+	TMS320C64X_GRP_FUNIT_D = 128,
+	TMS320C64X_GRP_FUNIT_L,
+	TMS320C64X_GRP_FUNIT_M,
+	TMS320C64X_GRP_FUNIT_S,
+	TMS320C64X_GRP_FUNIT_NO,
+
+	TMS320C64X_GRP_ENDING,   // <-- mark the end of the list of groups
+} tms320c64x_insn_group;
+
+typedef enum tms320c64x_funit {
+	TMS320C64X_FUNIT_INVALID = 0,
+	TMS320C64X_FUNIT_D,
+	TMS320C64X_FUNIT_L,
+	TMS320C64X_FUNIT_M,
+	TMS320C64X_FUNIT_S,
+	TMS320C64X_FUNIT_NO
+} tms320c64x_funit;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+

.tools/python-revlibs/capstone/include/capstone/tricore.h

@@ -0,0 +1,567 @@
+#ifndef CAPSTONE_TRICORE_H
+#define CAPSTONE_TRICORE_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
+#include <stdint.h>
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable : 4201)
+#endif
+
+/// Operand type for instruction's operands
+typedef enum tricore_op_type {
+	TRICORE_OP_INVALID = CS_OP_INVALID, ///< CS_OP_INVALID (Uninitialized).
+	TRICORE_OP_REG = CS_OP_REG,	    ///< CS_OP_REG (Register operand).
+	TRICORE_OP_IMM = CS_OP_IMM,	    ///< CS_OP_IMM (Immediate operand).
+	TRICORE_OP_MEM = CS_OP_MEM,	    ///< CS_OP_MEM (Memory operand).
+} tricore_op_type;
+
+/// Instruction's operand referring to memory
+/// This is associated with TRICORE_OP_MEM operand type above
+typedef struct tricore_op_mem {
+	uint8_t base; ///< base register
+	int32_t disp; ///< displacement/offset value
+} tricore_op_mem;
+
+/// Instruction operand
+typedef struct cs_tricore_op {
+	tricore_op_type type;	    ///< operand type
+	union {
+		unsigned int reg;   ///< register value for REG operand
+		int32_t imm;	    ///< immediate value for IMM operand
+		tricore_op_mem mem; ///< base/disp value for MEM operand
+	};
+	/// This field is combined of cs_ac_type.
+	/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
+	uint8_t access; ///< How is this operand accessed? (READ, WRITE or READ|WRITE)
+} cs_tricore_op;
+
+#define TRICORE_OP_COUNT 8
+
+/// Instruction structure
+typedef struct cs_tricore {
+	uint8_t op_count; ///< number of operands of this instruction.
+	cs_tricore_op
+		operands[TRICORE_OP_COUNT]; ///< operands for this instruction.
+	/// TODO: Mark the modified flags register in td files and regenerate inc files
+	bool update_flags; ///< whether the flags register is updated.
+} cs_tricore;
+
+/// TriCore registers
+typedef enum tricore_reg {
+	// generate content <TriCoreGenCSRegEnum.inc> begin
+	// clang-format off
+
+	TRICORE_REG_INVALID = 0,
+	TRICORE_REG_FCX = 1,
+	TRICORE_REG_PC = 2,
+	TRICORE_REG_PCXI = 3,
+	TRICORE_REG_PSW = 4,
+	TRICORE_REG_A0 = 5,
+	TRICORE_REG_A1 = 6,
+	TRICORE_REG_A2 = 7,
+	TRICORE_REG_A3 = 8,
+	TRICORE_REG_A4 = 9,
+	TRICORE_REG_A5 = 10,
+	TRICORE_REG_A6 = 11,
+	TRICORE_REG_A7 = 12,
+	TRICORE_REG_A8 = 13,
+	TRICORE_REG_A9 = 14,
+	TRICORE_REG_A10 = 15,
+	TRICORE_REG_A11 = 16,
+	TRICORE_REG_A12 = 17,
+	TRICORE_REG_A13 = 18,
+	TRICORE_REG_A14 = 19,
+	TRICORE_REG_A15 = 20,
+	TRICORE_REG_D0 = 21,
+	TRICORE_REG_D1 = 22,
+	TRICORE_REG_D2 = 23,
+	TRICORE_REG_D3 = 24,
+	TRICORE_REG_D4 = 25,
+	TRICORE_REG_D5 = 26,
+	TRICORE_REG_D6 = 27,
+	TRICORE_REG_D7 = 28,
+	TRICORE_REG_D8 = 29,
+	TRICORE_REG_D9 = 30,
+	TRICORE_REG_D10 = 31,
+	TRICORE_REG_D11 = 32,
+	TRICORE_REG_D12 = 33,
+	TRICORE_REG_D13 = 34,
+	TRICORE_REG_D14 = 35,
+	TRICORE_REG_D15 = 36,
+	TRICORE_REG_E0 = 37,
+	TRICORE_REG_E2 = 38,
+	TRICORE_REG_E4 = 39,
+	TRICORE_REG_E6 = 40,
+	TRICORE_REG_E8 = 41,
+	TRICORE_REG_E10 = 42,
+	TRICORE_REG_E12 = 43,
+	TRICORE_REG_E14 = 44,
+	TRICORE_REG_P0 = 45,
+	TRICORE_REG_P2 = 46,
+	TRICORE_REG_P4 = 47,
+	TRICORE_REG_P6 = 48,
+	TRICORE_REG_P8 = 49,
+	TRICORE_REG_P10 = 50,
+	TRICORE_REG_P12 = 51,
+	TRICORE_REG_P14 = 52,
+	TRICORE_REG_A0_A1 = 53,
+	TRICORE_REG_A2_A3 = 54,
+	TRICORE_REG_A4_A5 = 55,
+	TRICORE_REG_A6_A7 = 56,
+	TRICORE_REG_A8_A9 = 57,
+	TRICORE_REG_A10_A11 = 58,
+	TRICORE_REG_A12_A13 = 59,
+	TRICORE_REG_A14_A15 = 60,
+	TRICORE_REG_ENDING, // 61
+
+	// clang-format on
+	// generate content <TriCoreGenCSRegEnum.inc> end
+} tricore_reg;
+
+/// TriCore instruction
+typedef enum tricore_insn {
+	TRICORE_INS_INVALID = 0,
+	// generate content <TriCoreGenCSInsnEnum.inc> begin
+	// clang-format off
+
+	TRICORE_INS_XOR_T,
+	TRICORE_INS_ABSDIFS_B,
+	TRICORE_INS_ABSDIFS_H,
+	TRICORE_INS_ABSDIFS,
+	TRICORE_INS_ABSDIF_B,
+	TRICORE_INS_ABSDIF_H,
+	TRICORE_INS_ABSDIF,
+	TRICORE_INS_ABSS_B,
+	TRICORE_INS_ABSS_H,
+	TRICORE_INS_ABSS,
+	TRICORE_INS_ABS_B,
+	TRICORE_INS_ABS_H,
+	TRICORE_INS_ABS,
+	TRICORE_INS_ADDC,
+	TRICORE_INS_ADDIH_A,
+	TRICORE_INS_ADDIH,
+	TRICORE_INS_ADDI,
+	TRICORE_INS_ADDSC_AT,
+	TRICORE_INS_ADDSC_A,
+	TRICORE_INS_ADDS_BU,
+	TRICORE_INS_ADDS_B,
+	TRICORE_INS_ADDS_H,
+	TRICORE_INS_ADDS_HU,
+	TRICORE_INS_ADDS_U,
+	TRICORE_INS_ADDS,
+	TRICORE_INS_ADDX,
+	TRICORE_INS_ADD_A,
+	TRICORE_INS_ADD_B,
+	TRICORE_INS_ADD_F,
+	TRICORE_INS_ADD_H,
+	TRICORE_INS_ADD,
+	TRICORE_INS_ANDN_T,
+	TRICORE_INS_ANDN,
+	TRICORE_INS_AND_ANDN_T,
+	TRICORE_INS_AND_AND_T,
+	TRICORE_INS_AND_EQ,
+	TRICORE_INS_AND_GE_U,
+	TRICORE_INS_AND_GE,
+	TRICORE_INS_AND_LT_U,
+	TRICORE_INS_AND_LT,
+	TRICORE_INS_AND_NE,
+	TRICORE_INS_AND_NOR_T,
+	TRICORE_INS_AND_OR_T,
+	TRICORE_INS_AND_T,
+	TRICORE_INS_AND,
+	TRICORE_INS_BISR,
+	TRICORE_INS_BMERGE,
+	TRICORE_INS_BSPLIT,
+	TRICORE_INS_CACHEA_I,
+	TRICORE_INS_CACHEA_WI,
+	TRICORE_INS_CACHEA_W,
+	TRICORE_INS_CACHEI_I,
+	TRICORE_INS_CACHEI_WI,
+	TRICORE_INS_CACHEI_W,
+	TRICORE_INS_CADDN_A,
+	TRICORE_INS_CADDN,
+	TRICORE_INS_CADD_A,
+	TRICORE_INS_CADD,
+	TRICORE_INS_CALLA,
+	TRICORE_INS_CALLI,
+	TRICORE_INS_CALL,
+	TRICORE_INS_CLO_B,
+	TRICORE_INS_CLO_H,
+	TRICORE_INS_CLO,
+	TRICORE_INS_CLS_B,
+	TRICORE_INS_CLS_H,
+	TRICORE_INS_CLS,
+	TRICORE_INS_CLZ_B,
+	TRICORE_INS_CLZ_H,
+	TRICORE_INS_CLZ,
+	TRICORE_INS_CMOVN,
+	TRICORE_INS_CMOV,
+	TRICORE_INS_CMPSWAP_W,
+	TRICORE_INS_CMP_F,
+	TRICORE_INS_CRC32B_W,
+	TRICORE_INS_CRC32L_W,
+	TRICORE_INS_CRC32_B,
+	TRICORE_INS_CRCN,
+	TRICORE_INS_CSUBN_A,
+	TRICORE_INS_CSUBN,
+	TRICORE_INS_CSUB_A,
+	TRICORE_INS_CSUB,
+	TRICORE_INS_DEBUG,
+	TRICORE_INS_DEXTR,
+	TRICORE_INS_DIFSC_A,
+	TRICORE_INS_DISABLE,
+	TRICORE_INS_DIV_F,
+	TRICORE_INS_DIV_U,
+	TRICORE_INS_DIV,
+	TRICORE_INS_DSYNC,
+	TRICORE_INS_DVADJ,
+	TRICORE_INS_DVINIT_BU,
+	TRICORE_INS_DVINIT_B,
+	TRICORE_INS_DVINIT_HU,
+	TRICORE_INS_DVINIT_H,
+	TRICORE_INS_DVINIT_U,
+	TRICORE_INS_DVINIT,
+	TRICORE_INS_DVSTEP_U,
+	TRICORE_INS_DVSTEP,
+	TRICORE_INS_ENABLE,
+	TRICORE_INS_EQANY_B,
+	TRICORE_INS_EQANY_H,
+	TRICORE_INS_EQZ_A,
+	TRICORE_INS_EQ_A,
+	TRICORE_INS_EQ_B,
+	TRICORE_INS_EQ_H,
+	TRICORE_INS_EQ_W,
+	TRICORE_INS_EQ,
+	TRICORE_INS_EXTR_U,
+	TRICORE_INS_EXTR,
+	TRICORE_INS_FCALLA,
+	TRICORE_INS_FCALLI,
+	TRICORE_INS_FCALL,
+	TRICORE_INS_FRET,
+	TRICORE_INS_FTOHP,
+	TRICORE_INS_FTOIZ,
+	TRICORE_INS_FTOI,
+	TRICORE_INS_FTOQ31Z,
+	TRICORE_INS_FTOQ31,
+	TRICORE_INS_FTOUZ,
+	TRICORE_INS_FTOU,
+	TRICORE_INS_GE_A,
+	TRICORE_INS_GE_U,
+	TRICORE_INS_GE,
+	TRICORE_INS_HPTOF,
+	TRICORE_INS_IMASK,
+	TRICORE_INS_INSERT,
+	TRICORE_INS_INSN_T,
+	TRICORE_INS_INS_T,
+	TRICORE_INS_ISYNC,
+	TRICORE_INS_ITOF,
+	TRICORE_INS_IXMAX_U,
+	TRICORE_INS_IXMAX,
+	TRICORE_INS_IXMIN_U,
+	TRICORE_INS_IXMIN,
+	TRICORE_INS_JA,
+	TRICORE_INS_JEQ_A,
+	TRICORE_INS_JEQ,
+	TRICORE_INS_JGEZ,
+	TRICORE_INS_JGE_U,
+	TRICORE_INS_JGE,
+	TRICORE_INS_JGTZ,
+	TRICORE_INS_JI,
+	TRICORE_INS_JLA,
+	TRICORE_INS_JLEZ,
+	TRICORE_INS_JLI,
+	TRICORE_INS_JLTZ,
+	TRICORE_INS_JLT_U,
+	TRICORE_INS_JLT,
+	TRICORE_INS_JL,
+	TRICORE_INS_JNED,
+	TRICORE_INS_JNEI,
+	TRICORE_INS_JNE_A,
+	TRICORE_INS_JNE,
+	TRICORE_INS_JNZ_A,
+	TRICORE_INS_JNZ_T,
+	TRICORE_INS_JNZ,
+	TRICORE_INS_JZ_A,
+	TRICORE_INS_JZ_T,
+	TRICORE_INS_JZ,
+	TRICORE_INS_J,
+	TRICORE_INS_LDLCX,
+	TRICORE_INS_LDMST,
+	TRICORE_INS_LDUCX,
+	TRICORE_INS_LD_A,
+	TRICORE_INS_LD_BU,
+	TRICORE_INS_LD_B,
+	TRICORE_INS_LD_DA,
+	TRICORE_INS_LD_D,
+	TRICORE_INS_LD_HU,
+	TRICORE_INS_LD_H,
+	TRICORE_INS_LD_Q,
+	TRICORE_INS_LD_W,
+	TRICORE_INS_LEA,
+	TRICORE_INS_LHA,
+	TRICORE_INS_LOOPU,
+	TRICORE_INS_LOOP,
+	TRICORE_INS_LT_A,
+	TRICORE_INS_LT_B,
+	TRICORE_INS_LT_BU,
+	TRICORE_INS_LT_H,
+	TRICORE_INS_LT_HU,
+	TRICORE_INS_LT_U,
+	TRICORE_INS_LT_W,
+	TRICORE_INS_LT_WU,
+	TRICORE_INS_LT,
+	TRICORE_INS_MADDMS_H,
+	TRICORE_INS_MADDMS_U,
+	TRICORE_INS_MADDMS,
+	TRICORE_INS_MADDM_H,
+	TRICORE_INS_MADDM_Q,
+	TRICORE_INS_MADDM_U,
+	TRICORE_INS_MADDM,
+	TRICORE_INS_MADDRS_H,
+	TRICORE_INS_MADDRS_Q,
+	TRICORE_INS_MADDR_H,
+	TRICORE_INS_MADDR_Q,
+	TRICORE_INS_MADDSUMS_H,
+	TRICORE_INS_MADDSUM_H,
+	TRICORE_INS_MADDSURS_H,
+	TRICORE_INS_MADDSUR_H,
+	TRICORE_INS_MADDSUS_H,
+	TRICORE_INS_MADDSU_H,
+	TRICORE_INS_MADDS_H,
+	TRICORE_INS_MADDS_Q,
+	TRICORE_INS_MADDS_U,
+	TRICORE_INS_MADDS,
+	TRICORE_INS_MADD_F,
+	TRICORE_INS_MADD_H,
+	TRICORE_INS_MADD_Q,
+	TRICORE_INS_MADD_U,
+	TRICORE_INS_MADD,
+	TRICORE_INS_MAX_B,
+	TRICORE_INS_MAX_BU,
+	TRICORE_INS_MAX_H,
+	TRICORE_INS_MAX_HU,
+	TRICORE_INS_MAX_U,
+	TRICORE_INS_MAX,
+	TRICORE_INS_MFCR,
+	TRICORE_INS_MIN_B,
+	TRICORE_INS_MIN_BU,
+	TRICORE_INS_MIN_H,
+	TRICORE_INS_MIN_HU,
+	TRICORE_INS_MIN_U,
+	TRICORE_INS_MIN,
+	TRICORE_INS_MOVH_A,
+	TRICORE_INS_MOVH,
+	TRICORE_INS_MOVZ_A,
+	TRICORE_INS_MOV_AA,
+	TRICORE_INS_MOV_A,
+	TRICORE_INS_MOV_D,
+	TRICORE_INS_MOV_U,
+	TRICORE_INS_MOV,
+	TRICORE_INS_MSUBADMS_H,
+	TRICORE_INS_MSUBADM_H,
+	TRICORE_INS_MSUBADRS_H,
+	TRICORE_INS_MSUBADR_H,
+	TRICORE_INS_MSUBADS_H,
+	TRICORE_INS_MSUBAD_H,
+	TRICORE_INS_MSUBMS_H,
+	TRICORE_INS_MSUBMS_U,
+	TRICORE_INS_MSUBMS,
+	TRICORE_INS_MSUBM_H,
+	TRICORE_INS_MSUBM_Q,
+	TRICORE_INS_MSUBM_U,
+	TRICORE_INS_MSUBM,
+	TRICORE_INS_MSUBRS_H,
+	TRICORE_INS_MSUBRS_Q,
+	TRICORE_INS_MSUBR_H,
+	TRICORE_INS_MSUBR_Q,
+	TRICORE_INS_MSUBS_H,
+	TRICORE_INS_MSUBS_Q,
+	TRICORE_INS_MSUBS_U,
+	TRICORE_INS_MSUBS,
+	TRICORE_INS_MSUB_F,
+	TRICORE_INS_MSUB_H,
+	TRICORE_INS_MSUB_Q,
+	TRICORE_INS_MSUB_U,
+	TRICORE_INS_MSUB,
+	TRICORE_INS_MTCR,
+	TRICORE_INS_MULMS_H,
+	TRICORE_INS_MULM_H,
+	TRICORE_INS_MULM_U,
+	TRICORE_INS_MULM,
+	TRICORE_INS_MULR_H,
+	TRICORE_INS_MULR_Q,
+	TRICORE_INS_MULS_U,
+	TRICORE_INS_MULS,
+	TRICORE_INS_MUL_F,
+	TRICORE_INS_MUL_H,
+	TRICORE_INS_MUL_Q,
+	TRICORE_INS_MUL_U,
+	TRICORE_INS_MUL,
+	TRICORE_INS_NAND_T,
+	TRICORE_INS_NAND,
+	TRICORE_INS_NEZ_A,
+	TRICORE_INS_NE_A,
+	TRICORE_INS_NE,
+	TRICORE_INS_NOP,
+	TRICORE_INS_NOR_T,
+	TRICORE_INS_NOR,
+	TRICORE_INS_NOT,
+	TRICORE_INS_ORN_T,
+	TRICORE_INS_ORN,
+	TRICORE_INS_OR_ANDN_T,
+	TRICORE_INS_OR_AND_T,
+	TRICORE_INS_OR_EQ,
+	TRICORE_INS_OR_GE_U,
+	TRICORE_INS_OR_GE,
+	TRICORE_INS_OR_LT_U,
+	TRICORE_INS_OR_LT,
+	TRICORE_INS_OR_NE,
+	TRICORE_INS_OR_NOR_T,
+	TRICORE_INS_OR_OR_T,
+	TRICORE_INS_OR_T,
+	TRICORE_INS_OR,
+	TRICORE_INS_PACK,
+	TRICORE_INS_PARITY,
+	TRICORE_INS_POPCNT_W,
+	TRICORE_INS_Q31TOF,
+	TRICORE_INS_QSEED_F,
+	TRICORE_INS_RESTORE,
+	TRICORE_INS_RET,
+	TRICORE_INS_RFE,
+	TRICORE_INS_RFM,
+	TRICORE_INS_RSLCX,
+	TRICORE_INS_RSTV,
+	TRICORE_INS_RSUBS_U,
+	TRICORE_INS_RSUBS,
+	TRICORE_INS_RSUB,
+	TRICORE_INS_SAT_BU,
+	TRICORE_INS_SAT_B,
+	TRICORE_INS_SAT_HU,
+	TRICORE_INS_SAT_H,
+	TRICORE_INS_SELN_A,
+	TRICORE_INS_SELN,
+	TRICORE_INS_SEL_A,
+	TRICORE_INS_SEL,
+	TRICORE_INS_SHAS,
+	TRICORE_INS_SHA_B,
+	TRICORE_INS_SHA_H,
+	TRICORE_INS_SHA,
+	TRICORE_INS_SHUFFLE,
+	TRICORE_INS_SH_ANDN_T,
+	TRICORE_INS_SH_AND_T,
+	TRICORE_INS_SH_B,
+	TRICORE_INS_SH_EQ,
+	TRICORE_INS_SH_GE_U,
+	TRICORE_INS_SH_GE,
+	TRICORE_INS_SH_H,
+	TRICORE_INS_SH_LT_U,
+	TRICORE_INS_SH_LT,
+	TRICORE_INS_SH_NAND_T,
+	TRICORE_INS_SH_NE,
+	TRICORE_INS_SH_NOR_T,
+	TRICORE_INS_SH_ORN_T,
+	TRICORE_INS_SH_OR_T,
+	TRICORE_INS_SH_XNOR_T,
+	TRICORE_INS_SH_XOR_T,
+	TRICORE_INS_SH,
+	TRICORE_INS_STLCX,
+	TRICORE_INS_STUCX,
+	TRICORE_INS_ST_A,
+	TRICORE_INS_ST_B,
+	TRICORE_INS_ST_DA,
+	TRICORE_INS_ST_D,
+	TRICORE_INS_ST_H,
+	TRICORE_INS_ST_Q,
+	TRICORE_INS_ST_T,
+	TRICORE_INS_ST_W,
+	TRICORE_INS_SUBC,
+	TRICORE_INS_SUBSC_A,
+	TRICORE_INS_SUBS_BU,
+	TRICORE_INS_SUBS_B,
+	TRICORE_INS_SUBS_HU,
+	TRICORE_INS_SUBS_H,
+	TRICORE_INS_SUBS_U,
+	TRICORE_INS_SUBS,
+	TRICORE_INS_SUBX,
+	TRICORE_INS_SUB_A,
+	TRICORE_INS_SUB_B,
+	TRICORE_INS_SUB_F,
+	TRICORE_INS_SUB_H,
+	TRICORE_INS_SUB,
+	TRICORE_INS_SVLCX,
+	TRICORE_INS_SWAPMSK_W,
+	TRICORE_INS_SWAP_A,
+	TRICORE_INS_SWAP_W,
+	TRICORE_INS_SYSCALL,
+	TRICORE_INS_TLBDEMAP,
+	TRICORE_INS_TLBFLUSH_A,
+	TRICORE_INS_TLBFLUSH_B,
+	TRICORE_INS_TLBMAP,
+	TRICORE_INS_TLBPROBE_A,
+	TRICORE_INS_TLBPROBE_I,
+	TRICORE_INS_TRAPSV,
+	TRICORE_INS_TRAPV,
+	TRICORE_INS_UNPACK,
+	TRICORE_INS_UPDFL,
+	TRICORE_INS_UTOF,
+	TRICORE_INS_WAIT,
+	TRICORE_INS_XNOR_T,
+	TRICORE_INS_XNOR,
+	TRICORE_INS_XOR_EQ,
+	TRICORE_INS_XOR_GE_U,
+	TRICORE_INS_XOR_GE,
+	TRICORE_INS_XOR_LT_U,
+	TRICORE_INS_XOR_LT,
+	TRICORE_INS_XOR_NE,
+	TRICORE_INS_XOR,
+
+	// clang-format on
+	// generate content <TriCoreGenCSInsnEnum.inc> end
+	TRICORE_INS_ENDING, // <-- mark the end of the list of instructions
+} tricore_insn;
+
+/// Group of TriCore instructions
+typedef enum tricore_insn_group {
+	TRICORE_GRP_INVALID, ///< = CS_GRP_INVALID
+	/// Generic groups
+	TRICORE_GRP_CALL,   ///< = CS_GRP_CALL
+	TRICORE_GRP_JUMP,   ///< = CS_GRP_JUMP
+	TRICORE_GRP_ENDING, ///< mark the end of the list of groups
+} tricore_insn_group;
+
+typedef enum tricore_feature_t {
+	TRICORE_FEATURE_INVALID = 0,
+	// generate content <TriCoreGenCSFeatureEnum.inc> begin
+	// clang-format off
+
+	TRICORE_FEATURE_HasV110 = 128,
+	TRICORE_FEATURE_HasV120_UP,
+	TRICORE_FEATURE_HasV130_UP,
+	TRICORE_FEATURE_HasV161,
+	TRICORE_FEATURE_HasV160_UP,
+	TRICORE_FEATURE_HasV131_UP,
+	TRICORE_FEATURE_HasV161_UP,
+	TRICORE_FEATURE_HasV162,
+	TRICORE_FEATURE_HasV162_UP,
+
+	// clang-format on
+	// generate content <TriCoreGenCSFeatureEnum.inc> end
+	TRICORE_FEATURE_ENDING, ///< mark the end of the list of features
+} tricore_feature;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

.tools/python-revlibs/capstone/include/capstone/wasm.h

@@ -0,0 +1,250 @@
+/* Capstone Disassembly Engine */
+/* By Spike <spikeinhouse@gmail.com>, xwings 2019 */
+
+#ifndef CAPSTONE_WASM_H
+#define CAPSTONE_WASM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+typedef enum wasm_op_type {
+	WASM_OP_INVALID = 0,
+	WASM_OP_NONE,
+	WASM_OP_INT7,
+	WASM_OP_VARUINT32,
+	WASM_OP_VARUINT64,
+	WASM_OP_UINT32,
+	WASM_OP_UINT64,
+	WASM_OP_IMM,
+	WASM_OP_BRTABLE,
+} wasm_op_type;
+
+typedef struct cs_wasm_brtable {
+	uint32_t length;
+	uint64_t address;
+	uint32_t default_target;
+} cs_wasm_brtable;
+
+typedef struct cs_wasm_op {
+	wasm_op_type type;
+	uint32_t size;
+	union {
+		int8_t int7;
+		uint32_t varuint32;
+		uint64_t varuint64;
+		uint32_t uint32;
+		uint64_t uint64;
+		uint32_t immediate[2];
+		cs_wasm_brtable brtable;
+	};
+} cs_wasm_op;
+
+/// Instruction structure
+typedef struct cs_wasm {
+	uint8_t op_count;
+	cs_wasm_op operands[2];
+} cs_wasm;
+
+/// WASM instruction
+typedef enum wasm_insn {
+	WASM_INS_UNREACHABLE = 0x0,
+	WASM_INS_NOP = 0x1,
+	WASM_INS_BLOCK = 0x2,
+	WASM_INS_LOOP = 0x3,
+	WASM_INS_IF = 0x4,
+	WASM_INS_ELSE = 0x5,
+	WASM_INS_END = 0xb,
+	WASM_INS_BR = 0xc,
+	WASM_INS_BR_IF = 0xd,
+	WASM_INS_BR_TABLE = 0xe,
+	WASM_INS_RETURN = 0xf,
+	WASM_INS_CALL = 0x10,
+	WASM_INS_CALL_INDIRECT = 0x11,
+	WASM_INS_DROP = 0x1a,
+	WASM_INS_SELECT = 0x1b,
+	WASM_INS_GET_LOCAL = 0x20,
+	WASM_INS_SET_LOCAL = 0x21,
+	WASM_INS_TEE_LOCAL = 0x22,
+	WASM_INS_GET_GLOBAL = 0x23,
+	WASM_INS_SET_GLOBAL = 0x24,
+	WASM_INS_I32_LOAD = 0x28,
+	WASM_INS_I64_LOAD = 0x29,
+	WASM_INS_F32_LOAD = 0x2a,
+	WASM_INS_F64_LOAD = 0x2b,
+	WASM_INS_I32_LOAD8_S = 0x2c,
+	WASM_INS_I32_LOAD8_U = 0x2d,
+	WASM_INS_I32_LOAD16_S = 0x2e,
+	WASM_INS_I32_LOAD16_U = 0x2f,
+	WASM_INS_I64_LOAD8_S = 0x30,
+	WASM_INS_I64_LOAD8_U = 0x31,
+	WASM_INS_I64_LOAD16_S = 0x32,
+	WASM_INS_I64_LOAD16_U = 0x33,
+	WASM_INS_I64_LOAD32_S = 0x34,
+	WASM_INS_I64_LOAD32_U = 0x35,
+	WASM_INS_I32_STORE = 0x36,
+	WASM_INS_I64_STORE = 0x37,
+	WASM_INS_F32_STORE = 0x38,
+	WASM_INS_F64_STORE = 0x39,
+	WASM_INS_I32_STORE8 = 0x3a,
+	WASM_INS_I32_STORE16 = 0x3b,
+	WASM_INS_I64_STORE8 = 0x3c,
+	WASM_INS_I64_STORE16 = 0x3d,
+	WASM_INS_I64_STORE32 = 0x3e,
+	WASM_INS_CURRENT_MEMORY = 0x3f,
+	WASM_INS_GROW_MEMORY = 0x40,
+	WASM_INS_I32_CONST = 0x41,
+	WASM_INS_I64_CONST = 0x42,
+	WASM_INS_F32_CONST = 0x43,
+	WASM_INS_F64_CONST = 0x44,
+	WASM_INS_I32_EQZ = 0x45,
+	WASM_INS_I32_EQ = 0x46,
+	WASM_INS_I32_NE = 0x47,
+	WASM_INS_I32_LT_S = 0x48,
+	WASM_INS_I32_LT_U = 0x49,
+	WASM_INS_I32_GT_S = 0x4a,
+	WASM_INS_I32_GT_U = 0x4b,
+	WASM_INS_I32_LE_S = 0x4c,
+	WASM_INS_I32_LE_U = 0x4d,
+	WASM_INS_I32_GE_S = 0x4e,
+	WASM_INS_I32_GE_U = 0x4f,
+	WASM_INS_I64_EQZ = 0x50,
+	WASM_INS_I64_EQ = 0x51,
+	WASM_INS_I64_NE = 0x52,
+	WASM_INS_I64_LT_S = 0x53,
+	WASM_INS_I64_LT_U = 0x54,
+	WASN_INS_I64_GT_S = 0x55,
+	WASM_INS_I64_GT_U = 0x56,
+	WASM_INS_I64_LE_S = 0x57,
+	WASM_INS_I64_LE_U = 0x58,
+	WASM_INS_I64_GE_S = 0x59,
+	WASM_INS_I64_GE_U = 0x5a,
+	WASM_INS_F32_EQ = 0x5b,
+	WASM_INS_F32_NE = 0x5c,
+	WASM_INS_F32_LT = 0x5d,
+	WASM_INS_F32_GT = 0x5e,
+	WASM_INS_F32_LE = 0x5f,
+	WASM_INS_F32_GE = 0x60,
+	WASM_INS_F64_EQ = 0x61,
+	WASM_INS_F64_NE = 0x62,
+	WASM_INS_F64_LT = 0x63,
+	WASM_INS_F64_GT = 0x64,
+	WASM_INS_F64_LE = 0x65,
+	WASM_INS_F64_GE = 0x66,
+	WASM_INS_I32_CLZ = 0x67,
+	WASM_INS_I32_CTZ = 0x68,
+	WASM_INS_I32_POPCNT = 0x69,
+	WASM_INS_I32_ADD = 0x6a,
+	WASM_INS_I32_SUB = 0x6b,
+	WASM_INS_I32_MUL = 0x6c,
+	WASM_INS_I32_DIV_S = 0x6d,
+	WASM_INS_I32_DIV_U = 0x6e,
+	WASM_INS_I32_REM_S = 0x6f,
+	WASM_INS_I32_REM_U = 0x70,
+	WASM_INS_I32_AND = 0x71,
+	WASM_INS_I32_OR = 0x72,
+	WASM_INS_I32_XOR = 0x73,
+	WASM_INS_I32_SHL = 0x74,
+	WASM_INS_I32_SHR_S = 0x75,
+	WASM_INS_I32_SHR_U = 0x76,
+	WASM_INS_I32_ROTL = 0x77,
+	WASM_INS_I32_ROTR = 0x78,
+	WASM_INS_I64_CLZ = 0x79,
+	WASM_INS_I64_CTZ = 0x7a,
+	WASM_INS_I64_POPCNT = 0x7b,
+	WASM_INS_I64_ADD = 0x7c,
+	WASM_INS_I64_SUB = 0x7d,
+	WASM_INS_I64_MUL = 0x7e,
+	WASM_INS_I64_DIV_S = 0x7f,
+	WASM_INS_I64_DIV_U = 0x80,
+	WASM_INS_I64_REM_S = 0x81,
+	WASM_INS_I64_REM_U = 0x82,
+	WASM_INS_I64_AND = 0x83,
+	WASM_INS_I64_OR = 0x84,
+	WASM_INS_I64_XOR = 0x85,
+	WASM_INS_I64_SHL = 0x86,
+	WASM_INS_I64_SHR_S = 0x87,
+	WASM_INS_I64_SHR_U = 0x88,
+	WASM_INS_I64_ROTL = 0x89,
+	WASM_INS_I64_ROTR = 0x8a,
+	WASM_INS_F32_ABS = 0x8b,
+	WASM_INS_F32_NEG = 0x8c,
+	WASM_INS_F32_CEIL = 0x8d,
+	WASM_INS_F32_FLOOR = 0x8e,
+	WASM_INS_F32_TRUNC = 0x8f,
+	WASM_INS_F32_NEAREST = 0x90,
+	WASM_INS_F32_SQRT = 0x91,
+	WASM_INS_F32_ADD = 0x92,
+	WASM_INS_F32_SUB = 0x93,
+	WASM_INS_F32_MUL = 0x94,
+	WASM_INS_F32_DIV = 0x95,
+	WASM_INS_F32_MIN = 0x96,
+	WASM_INS_F32_MAX = 0x97,
+	WASM_INS_F32_COPYSIGN = 0x98,
+	WASM_INS_F64_ABS = 0x99,
+	WASM_INS_F64_NEG = 0x9a,
+	WASM_INS_F64_CEIL = 0x9b,
+	WASM_INS_F64_FLOOR = 0x9c,
+	WASM_INS_F64_TRUNC = 0x9d,
+	WASM_INS_F64_NEAREST = 0x9e,
+	WASM_INS_F64_SQRT = 0x9f,
+	WASM_INS_F64_ADD = 0xa0,
+	WASM_INS_F64_SUB = 0xa1,
+	WASM_INS_F64_MUL = 0xa2,
+	WASM_INS_F64_DIV = 0xa3,
+	WASM_INS_F64_MIN = 0xa4,
+	WASM_INS_F64_MAX = 0xa5,
+	WASM_INS_F64_COPYSIGN = 0xa6,
+	WASM_INS_I32_WARP_I64 = 0xa7,
+	WASP_INS_I32_TRUNC_S_F32 = 0xa8,
+	WASM_INS_I32_TRUNC_U_F32 = 0xa9,
+	WASM_INS_I32_TRUNC_S_F64 = 0xaa,
+	WASM_INS_I32_TRUNC_U_F64 = 0xab,
+	WASM_INS_I64_EXTEND_S_I32 = 0xac,
+	WASM_INS_I64_EXTEND_U_I32 = 0xad,
+	WASM_INS_I64_TRUNC_S_F32 = 0xae,
+	WASM_INS_I64_TRUNC_U_F32 = 0xaf,
+	WASM_INS_I64_TRUNC_S_F64 = 0xb0,
+	WASM_INS_I64_TRUNC_U_F64 = 0xb1,
+	WASM_INS_F32_CONVERT_S_I32 = 0xb2,
+	WASM_INS_F32_CONVERT_U_I32 = 0xb3,
+	WASM_INS_F32_CONVERT_S_I64 = 0xb4,
+	WASM_INS_F32_CONVERT_U_I64 = 0xb5,
+	WASM_INS_F32_DEMOTE_F64 = 0xb6,
+	WASM_INS_F64_CONVERT_S_I32 = 0xb7,
+	WASM_INS_F64_CONVERT_U_I32 = 0xb8,
+	WASM_INS_F64_CONVERT_S_I64 = 0xb9,
+	WASM_INS_F64_CONVERT_U_I64 = 0xba,
+	WASM_INS_F64_PROMOTE_F32 = 0xbb,
+	WASM_INS_I32_REINTERPRET_F32 = 0xbc,
+	WASM_INS_I64_REINTERPRET_F64 = 0xbd,
+	WASM_INS_F32_REINTERPRET_I32 = 0xbe,
+	WASM_INS_F64_REINTERPRET_I64 = 0xbf,
+	WASM_INS_INVALID = 512,
+	WASM_INS_ENDING,
+} wasm_insn;
+
+/// Group of WASM instructions
+typedef enum wasm_insn_group {
+	WASM_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+	WASM_GRP_NUMBERIC = 8,
+	WASM_GRP_PARAMETRIC,
+	WASM_GRP_VARIABLE,
+	WASM_GRP_MEMORY,
+	WASM_GRP_CONTROL,
+
+	WASM_GRP_ENDING,   ///< <-- mark the end of the list of groups
+} wasm_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

.tools/python-revlibs/capstone/include/capstone/xcore.h

@@ -0,0 +1,235 @@
+#ifndef CAPSTONE_XCORE_H
+#define CAPSTONE_XCORE_H
+
+/* Capstone Disassembly Engine */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014-2015 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "platform.h"
+
+#ifdef _MSC_VER
+#pragma warning(disable:4201)
+#endif
+
+/// Operand type for instruction's operands
+typedef enum xcore_op_type {
+	XCORE_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
+	XCORE_OP_REG, ///< = CS_OP_REG (Register operand).
+	XCORE_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
+	XCORE_OP_MEM, ///< = CS_OP_MEM (Memory operand).
+} xcore_op_type;
+
+/// XCore registers
+typedef enum xcore_reg {
+	XCORE_REG_INVALID = 0,
+
+	XCORE_REG_CP,
+	XCORE_REG_DP,
+	XCORE_REG_LR,
+	XCORE_REG_SP,
+	XCORE_REG_R0,
+	XCORE_REG_R1,
+	XCORE_REG_R2,
+	XCORE_REG_R3,
+	XCORE_REG_R4,
+	XCORE_REG_R5,
+	XCORE_REG_R6,
+	XCORE_REG_R7,
+	XCORE_REG_R8,
+	XCORE_REG_R9,
+	XCORE_REG_R10,
+	XCORE_REG_R11,
+
+	// pseudo registers
+	XCORE_REG_PC,	///< pc
+
+	// internal thread registers
+	// see The-XMOS-XS1-Architecture(X7879A).pdf
+	XCORE_REG_SCP,	///< save pc
+	XCORE_REG_SSR,	//< save status
+	XCORE_REG_ET,	//< exception type
+	XCORE_REG_ED,	//< exception data
+	XCORE_REG_SED,	//< save exception data
+	XCORE_REG_KEP,	//< kernel entry pointer
+	XCORE_REG_KSP,	//< kernel stack pointer
+	XCORE_REG_ID,	//< thread ID
+
+	XCORE_REG_ENDING,	// <-- mark the end of the list of registers
+} xcore_reg;
+
+/// Instruction's operand referring to memory
+/// This is associated with XCORE_OP_MEM operand type above
+typedef struct xcore_op_mem {
+	uint8_t base;		///< base register, can be safely interpreted as
+				///< a value of type `xcore_reg`, but it is only
+				///< one byte wide
+	uint8_t index;		///< index register, same conditions apply here
+	int32_t disp;	///< displacement/offset value
+	int     direct;	///< +1: forward, -1: backward
+} xcore_op_mem;
+
+/// Instruction operand
+typedef struct cs_xcore_op {
+	xcore_op_type type;	///< operand type
+	union {
+		xcore_reg reg;	///< register value for REG operand
+		int32_t imm;		///< immediate value for IMM operand
+		xcore_op_mem mem;		///< base/disp value for MEM operand
+	};
+} cs_xcore_op;
+
+/// Instruction structure
+typedef struct cs_xcore {
+	/// Number of operands of this instruction,
+	/// or 0 when instruction has no operand.
+	uint8_t op_count;
+	cs_xcore_op operands[8]; ///< operands for this instruction.
+} cs_xcore;
+
+/// XCore instruction
+typedef enum xcore_insn {
+	XCORE_INS_INVALID = 0,
+
+	XCORE_INS_ADD,
+	XCORE_INS_ANDNOT,
+	XCORE_INS_AND,
+	XCORE_INS_ASHR,
+	XCORE_INS_BAU,
+	XCORE_INS_BITREV,
+	XCORE_INS_BLA,
+	XCORE_INS_BLAT,
+	XCORE_INS_BL,
+	XCORE_INS_BF,
+	XCORE_INS_BT,
+	XCORE_INS_BU,
+	XCORE_INS_BRU,
+	XCORE_INS_BYTEREV,
+	XCORE_INS_CHKCT,
+	XCORE_INS_CLRE,
+	XCORE_INS_CLRPT,
+	XCORE_INS_CLRSR,
+	XCORE_INS_CLZ,
+	XCORE_INS_CRC8,
+	XCORE_INS_CRC32,
+	XCORE_INS_DCALL,
+	XCORE_INS_DENTSP,
+	XCORE_INS_DGETREG,
+	XCORE_INS_DIVS,
+	XCORE_INS_DIVU,
+	XCORE_INS_DRESTSP,
+	XCORE_INS_DRET,
+	XCORE_INS_ECALLF,
+	XCORE_INS_ECALLT,
+	XCORE_INS_EDU,
+	XCORE_INS_EEF,
+	XCORE_INS_EET,
+	XCORE_INS_EEU,
+	XCORE_INS_ENDIN,
+	XCORE_INS_ENTSP,
+	XCORE_INS_EQ,
+	XCORE_INS_EXTDP,
+	XCORE_INS_EXTSP,
+	XCORE_INS_FREER,
+	XCORE_INS_FREET,
+	XCORE_INS_GETD,
+	XCORE_INS_GET,
+	XCORE_INS_GETN,
+	XCORE_INS_GETR,
+	XCORE_INS_GETSR,
+	XCORE_INS_GETST,
+	XCORE_INS_GETTS,
+	XCORE_INS_INCT,
+	XCORE_INS_INIT,
+	XCORE_INS_INPW,
+	XCORE_INS_INSHR,
+	XCORE_INS_INT,
+	XCORE_INS_IN,
+	XCORE_INS_KCALL,
+	XCORE_INS_KENTSP,
+	XCORE_INS_KRESTSP,
+	XCORE_INS_KRET,
+	XCORE_INS_LADD,
+	XCORE_INS_LD16S,
+	XCORE_INS_LD8U,
+	XCORE_INS_LDA16,
+	XCORE_INS_LDAP,
+	XCORE_INS_LDAW,
+	XCORE_INS_LDC,
+	XCORE_INS_LDW,
+	XCORE_INS_LDIVU,
+	XCORE_INS_LMUL,
+	XCORE_INS_LSS,
+	XCORE_INS_LSUB,
+	XCORE_INS_LSU,
+	XCORE_INS_MACCS,
+	XCORE_INS_MACCU,
+	XCORE_INS_MJOIN,
+	XCORE_INS_MKMSK,
+	XCORE_INS_MSYNC,
+	XCORE_INS_MUL,
+	XCORE_INS_NEG,
+	XCORE_INS_NOT,
+	XCORE_INS_OR,
+	XCORE_INS_OUTCT,
+	XCORE_INS_OUTPW,
+	XCORE_INS_OUTSHR,
+	XCORE_INS_OUTT,
+	XCORE_INS_OUT,
+	XCORE_INS_PEEK,
+	XCORE_INS_REMS,
+	XCORE_INS_REMU,
+	XCORE_INS_RETSP,
+	XCORE_INS_SETCLK,
+	XCORE_INS_SET,
+	XCORE_INS_SETC,
+	XCORE_INS_SETD,
+	XCORE_INS_SETEV,
+	XCORE_INS_SETN,
+	XCORE_INS_SETPSC,
+	XCORE_INS_SETPT,
+	XCORE_INS_SETRDY,
+	XCORE_INS_SETSR,
+	XCORE_INS_SETTW,
+	XCORE_INS_SETV,
+	XCORE_INS_SEXT,
+	XCORE_INS_SHL,
+	XCORE_INS_SHR,
+	XCORE_INS_SSYNC,
+	XCORE_INS_ST16,
+	XCORE_INS_ST8,
+	XCORE_INS_STW,
+	XCORE_INS_SUB,
+	XCORE_INS_SYNCR,
+	XCORE_INS_TESTCT,
+	XCORE_INS_TESTLCL,
+	XCORE_INS_TESTWCT,
+	XCORE_INS_TSETMR,
+	XCORE_INS_START,
+	XCORE_INS_WAITEF,
+	XCORE_INS_WAITET,
+	XCORE_INS_WAITEU,
+	XCORE_INS_XOR,
+	XCORE_INS_ZEXT,
+
+	XCORE_INS_ENDING,   // <-- mark the end of the list of instructions
+} xcore_insn;
+
+/// Group of XCore instructions
+typedef enum xcore_insn_group {
+	XCORE_GRP_INVALID = 0, ///< = CS_GRP_INVALID
+
+	// Generic groups
+	// all jump instructions (conditional+direct+indirect jumps)
+	XCORE_GRP_JUMP,	///< = CS_GRP_JUMP
+
+	XCORE_GRP_ENDING,   // <-- mark the end of the list of groups
+} xcore_insn_group;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

.tools/python-revlibs/capstone/m680x.py

@@ -0,0 +1,88 @@
+# Capstone Python bindings, by Wolfgang Schwotzer <wolfgang.schwotzer@gmx.net>
+
+import ctypes
+from . import copy_ctypes_list
+from .m680x_const import *
+
+# define the API
+class M680xOpIdx(ctypes.Structure):
+    _fields_ = (
+        ('base_reg', ctypes.c_uint),
+        ('offset_reg', ctypes.c_uint),
+        ('offset', ctypes.c_int16),
+        ('offset_addr', ctypes.c_uint16),
+        ('offset_bits', ctypes.c_uint8),
+        ('inc_dec', ctypes.c_int8),
+        ('flags', ctypes.c_uint8),
+    )
+
+class M680xOpRel(ctypes.Structure):
+    _fields_ = (
+        ('address', ctypes.c_uint16),
+        ('offset', ctypes.c_int16),
+    )
+
+class M680xOpExt(ctypes.Structure):
+    _fields_ = (
+        ('address', ctypes.c_uint16),
+        ('indirect', ctypes.c_bool),
+    )
+
+class M680xOpValue(ctypes.Union):
+    _fields_ = (
+        ('imm', ctypes.c_int32),
+        ('reg', ctypes.c_uint),
+        ('idx', M680xOpIdx),
+        ('rel', M680xOpRel),
+        ('ext', M680xOpExt),
+        ('direct_addr', ctypes.c_uint8),
+        ('const_val', ctypes.c_uint8),
+    )
+
+class M680xOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', M680xOpValue),
+        ('size', ctypes.c_uint8),
+        ('access', ctypes.c_uint8),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def idx(self):
+        return self.value.idx
+
+    @property
+    def rel(self):
+        return self.value.rel
+
+    @property
+    def ext(self):
+        return self.value.ext
+
+    @property
+    def direct_addr(self):
+        return self.value.direct_addr
+
+    @property
+    def const_val(self):
+        return self.value.const_val
+
+
+class CsM680x(ctypes.Structure):
+    _fields_ = (
+        ('flags', ctypes.c_uint8),
+        ('op_count', ctypes.c_uint8),
+        ('operands', M680xOp * 9),
+    )
+
+def get_arch_info(a):
+    return (a.flags, copy_ctypes_list(a.operands[:a.op_count]))
+

.tools/python-revlibs/capstone/m680x_const.py

@@ -0,0 +1,416 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m680x_const.py]
+M680X_OPERAND_COUNT = 9
+
+M680X_REG_INVALID = 0
+M680X_REG_A = 1
+M680X_REG_B = 2
+M680X_REG_E = 3
+M680X_REG_F = 4
+M680X_REG_0 = 5
+M680X_REG_D = 6
+M680X_REG_W = 7
+M680X_REG_CC = 8
+M680X_REG_DP = 9
+M680X_REG_MD = 10
+M680X_REG_HX = 11
+M680X_REG_H = 12
+M680X_REG_X = 13
+M680X_REG_Y = 14
+M680X_REG_S = 15
+M680X_REG_U = 16
+M680X_REG_V = 17
+M680X_REG_Q = 18
+M680X_REG_PC = 19
+M680X_REG_TMP2 = 20
+M680X_REG_TMP3 = 21
+M680X_REG_ENDING = 22
+
+M680X_OP_INVALID = 0
+M680X_OP_REGISTER = 1
+M680X_OP_IMMEDIATE = 2
+M680X_OP_INDEXED = 3
+M680X_OP_EXTENDED = 4
+M680X_OP_DIRECT = 5
+M680X_OP_RELATIVE = 6
+M680X_OP_CONSTANT = 7
+
+M680X_OFFSET_NONE = 0
+M680X_OFFSET_BITS_5 = 5
+M680X_OFFSET_BITS_8 = 8
+M680X_OFFSET_BITS_9 = 9
+M680X_OFFSET_BITS_16 = 16
+M680X_IDX_INDIRECT = 1
+M680X_IDX_NO_COMMA = 2
+M680X_IDX_POST_INC_DEC = 4
+
+M680X_GRP_INVALID = 0
+M680X_GRP_JUMP = 1
+M680X_GRP_CALL = 2
+M680X_GRP_RET = 3
+M680X_GRP_INT = 4
+M680X_GRP_IRET = 5
+M680X_GRP_PRIV = 6
+M680X_GRP_BRAREL = 7
+M680X_GRP_ENDING = 8
+M680X_FIRST_OP_IN_MNEM = 1
+M680X_SECOND_OP_IN_MNEM = 2
+
+M680X_INS_INVLD = 0
+M680X_INS_ABA = 1
+M680X_INS_ABX = 2
+M680X_INS_ABY = 3
+M680X_INS_ADC = 4
+M680X_INS_ADCA = 5
+M680X_INS_ADCB = 6
+M680X_INS_ADCD = 7
+M680X_INS_ADCR = 8
+M680X_INS_ADD = 9
+M680X_INS_ADDA = 10
+M680X_INS_ADDB = 11
+M680X_INS_ADDD = 12
+M680X_INS_ADDE = 13
+M680X_INS_ADDF = 14
+M680X_INS_ADDR = 15
+M680X_INS_ADDW = 16
+M680X_INS_AIM = 17
+M680X_INS_AIS = 18
+M680X_INS_AIX = 19
+M680X_INS_AND = 20
+M680X_INS_ANDA = 21
+M680X_INS_ANDB = 22
+M680X_INS_ANDCC = 23
+M680X_INS_ANDD = 24
+M680X_INS_ANDR = 25
+M680X_INS_ASL = 26
+M680X_INS_ASLA = 27
+M680X_INS_ASLB = 28
+M680X_INS_ASLD = 29
+M680X_INS_ASR = 30
+M680X_INS_ASRA = 31
+M680X_INS_ASRB = 32
+M680X_INS_ASRD = 33
+M680X_INS_ASRX = 34
+M680X_INS_BAND = 35
+M680X_INS_BCC = 36
+M680X_INS_BCLR = 37
+M680X_INS_BCS = 38
+M680X_INS_BEOR = 39
+M680X_INS_BEQ = 40
+M680X_INS_BGE = 41
+M680X_INS_BGND = 42
+M680X_INS_BGT = 43
+M680X_INS_BHCC = 44
+M680X_INS_BHCS = 45
+M680X_INS_BHI = 46
+M680X_INS_BIAND = 47
+M680X_INS_BIEOR = 48
+M680X_INS_BIH = 49
+M680X_INS_BIL = 50
+M680X_INS_BIOR = 51
+M680X_INS_BIT = 52
+M680X_INS_BITA = 53
+M680X_INS_BITB = 54
+M680X_INS_BITD = 55
+M680X_INS_BITMD = 56
+M680X_INS_BLE = 57
+M680X_INS_BLS = 58
+M680X_INS_BLT = 59
+M680X_INS_BMC = 60
+M680X_INS_BMI = 61
+M680X_INS_BMS = 62
+M680X_INS_BNE = 63
+M680X_INS_BOR = 64
+M680X_INS_BPL = 65
+M680X_INS_BRCLR = 66
+M680X_INS_BRSET = 67
+M680X_INS_BRA = 68
+M680X_INS_BRN = 69
+M680X_INS_BSET = 70
+M680X_INS_BSR = 71
+M680X_INS_BVC = 72
+M680X_INS_BVS = 73
+M680X_INS_CALL = 74
+M680X_INS_CBA = 75
+M680X_INS_CBEQ = 76
+M680X_INS_CBEQA = 77
+M680X_INS_CBEQX = 78
+M680X_INS_CLC = 79
+M680X_INS_CLI = 80
+M680X_INS_CLR = 81
+M680X_INS_CLRA = 82
+M680X_INS_CLRB = 83
+M680X_INS_CLRD = 84
+M680X_INS_CLRE = 85
+M680X_INS_CLRF = 86
+M680X_INS_CLRH = 87
+M680X_INS_CLRW = 88
+M680X_INS_CLRX = 89
+M680X_INS_CLV = 90
+M680X_INS_CMP = 91
+M680X_INS_CMPA = 92
+M680X_INS_CMPB = 93
+M680X_INS_CMPD = 94
+M680X_INS_CMPE = 95
+M680X_INS_CMPF = 96
+M680X_INS_CMPR = 97
+M680X_INS_CMPS = 98
+M680X_INS_CMPU = 99
+M680X_INS_CMPW = 100
+M680X_INS_CMPX = 101
+M680X_INS_CMPY = 102
+M680X_INS_COM = 103
+M680X_INS_COMA = 104
+M680X_INS_COMB = 105
+M680X_INS_COMD = 106
+M680X_INS_COME = 107
+M680X_INS_COMF = 108
+M680X_INS_COMW = 109
+M680X_INS_COMX = 110
+M680X_INS_CPD = 111
+M680X_INS_CPHX = 112
+M680X_INS_CPS = 113
+M680X_INS_CPX = 114
+M680X_INS_CPY = 115
+M680X_INS_CWAI = 116
+M680X_INS_DAA = 117
+M680X_INS_DBEQ = 118
+M680X_INS_DBNE = 119
+M680X_INS_DBNZ = 120
+M680X_INS_DBNZA = 121
+M680X_INS_DBNZX = 122
+M680X_INS_DEC = 123
+M680X_INS_DECA = 124
+M680X_INS_DECB = 125
+M680X_INS_DECD = 126
+M680X_INS_DECE = 127
+M680X_INS_DECF = 128
+M680X_INS_DECW = 129
+M680X_INS_DECX = 130
+M680X_INS_DES = 131
+M680X_INS_DEX = 132
+M680X_INS_DEY = 133
+M680X_INS_DIV = 134
+M680X_INS_DIVD = 135
+M680X_INS_DIVQ = 136
+M680X_INS_EDIV = 137
+M680X_INS_EDIVS = 138
+M680X_INS_EIM = 139
+M680X_INS_EMACS = 140
+M680X_INS_EMAXD = 141
+M680X_INS_EMAXM = 142
+M680X_INS_EMIND = 143
+M680X_INS_EMINM = 144
+M680X_INS_EMUL = 145
+M680X_INS_EMULS = 146
+M680X_INS_EOR = 147
+M680X_INS_EORA = 148
+M680X_INS_EORB = 149
+M680X_INS_EORD = 150
+M680X_INS_EORR = 151
+M680X_INS_ETBL = 152
+M680X_INS_EXG = 153
+M680X_INS_FDIV = 154
+M680X_INS_IBEQ = 155
+M680X_INS_IBNE = 156
+M680X_INS_IDIV = 157
+M680X_INS_IDIVS = 158
+M680X_INS_ILLGL = 159
+M680X_INS_INC = 160
+M680X_INS_INCA = 161
+M680X_INS_INCB = 162
+M680X_INS_INCD = 163
+M680X_INS_INCE = 164
+M680X_INS_INCF = 165
+M680X_INS_INCW = 166
+M680X_INS_INCX = 167
+M680X_INS_INS = 168
+M680X_INS_INX = 169
+M680X_INS_INY = 170
+M680X_INS_JMP = 171
+M680X_INS_JSR = 172
+M680X_INS_LBCC = 173
+M680X_INS_LBCS = 174
+M680X_INS_LBEQ = 175
+M680X_INS_LBGE = 176
+M680X_INS_LBGT = 177
+M680X_INS_LBHI = 178
+M680X_INS_LBLE = 179
+M680X_INS_LBLS = 180
+M680X_INS_LBLT = 181
+M680X_INS_LBMI = 182
+M680X_INS_LBNE = 183
+M680X_INS_LBPL = 184
+M680X_INS_LBRA = 185
+M680X_INS_LBRN = 186
+M680X_INS_LBSR = 187
+M680X_INS_LBVC = 188
+M680X_INS_LBVS = 189
+M680X_INS_LDA = 190
+M680X_INS_LDAA = 191
+M680X_INS_LDAB = 192
+M680X_INS_LDB = 193
+M680X_INS_LDBT = 194
+M680X_INS_LDD = 195
+M680X_INS_LDE = 196
+M680X_INS_LDF = 197
+M680X_INS_LDHX = 198
+M680X_INS_LDMD = 199
+M680X_INS_LDQ = 200
+M680X_INS_LDS = 201
+M680X_INS_LDU = 202
+M680X_INS_LDW = 203
+M680X_INS_LDX = 204
+M680X_INS_LDY = 205
+M680X_INS_LEAS = 206
+M680X_INS_LEAU = 207
+M680X_INS_LEAX = 208
+M680X_INS_LEAY = 209
+M680X_INS_LSL = 210
+M680X_INS_LSLA = 211
+M680X_INS_LSLB = 212
+M680X_INS_LSLD = 213
+M680X_INS_LSLX = 214
+M680X_INS_LSR = 215
+M680X_INS_LSRA = 216
+M680X_INS_LSRB = 217
+M680X_INS_LSRD = 218
+M680X_INS_LSRW = 219
+M680X_INS_LSRX = 220
+M680X_INS_MAXA = 221
+M680X_INS_MAXM = 222
+M680X_INS_MEM = 223
+M680X_INS_MINA = 224
+M680X_INS_MINM = 225
+M680X_INS_MOV = 226
+M680X_INS_MOVB = 227
+M680X_INS_MOVW = 228
+M680X_INS_MUL = 229
+M680X_INS_MULD = 230
+M680X_INS_NEG = 231
+M680X_INS_NEGA = 232
+M680X_INS_NEGB = 233
+M680X_INS_NEGD = 234
+M680X_INS_NEGX = 235
+M680X_INS_NOP = 236
+M680X_INS_NSA = 237
+M680X_INS_OIM = 238
+M680X_INS_ORA = 239
+M680X_INS_ORAA = 240
+M680X_INS_ORAB = 241
+M680X_INS_ORB = 242
+M680X_INS_ORCC = 243
+M680X_INS_ORD = 244
+M680X_INS_ORR = 245
+M680X_INS_PSHA = 246
+M680X_INS_PSHB = 247
+M680X_INS_PSHC = 248
+M680X_INS_PSHD = 249
+M680X_INS_PSHH = 250
+M680X_INS_PSHS = 251
+M680X_INS_PSHSW = 252
+M680X_INS_PSHU = 253
+M680X_INS_PSHUW = 254
+M680X_INS_PSHX = 255
+M680X_INS_PSHY = 256
+M680X_INS_PULA = 257
+M680X_INS_PULB = 258
+M680X_INS_PULC = 259
+M680X_INS_PULD = 260
+M680X_INS_PULH = 261
+M680X_INS_PULS = 262
+M680X_INS_PULSW = 263
+M680X_INS_PULU = 264
+M680X_INS_PULUW = 265
+M680X_INS_PULX = 266
+M680X_INS_PULY = 267
+M680X_INS_REV = 268
+M680X_INS_REVW = 269
+M680X_INS_ROL = 270
+M680X_INS_ROLA = 271
+M680X_INS_ROLB = 272
+M680X_INS_ROLD = 273
+M680X_INS_ROLW = 274
+M680X_INS_ROLX = 275
+M680X_INS_ROR = 276
+M680X_INS_RORA = 277
+M680X_INS_RORB = 278
+M680X_INS_RORD = 279
+M680X_INS_RORW = 280
+M680X_INS_RORX = 281
+M680X_INS_RSP = 282
+M680X_INS_RTC = 283
+M680X_INS_RTI = 284
+M680X_INS_RTS = 285
+M680X_INS_SBA = 286
+M680X_INS_SBC = 287
+M680X_INS_SBCA = 288
+M680X_INS_SBCB = 289
+M680X_INS_SBCD = 290
+M680X_INS_SBCR = 291
+M680X_INS_SEC = 292
+M680X_INS_SEI = 293
+M680X_INS_SEV = 294
+M680X_INS_SEX = 295
+M680X_INS_SEXW = 296
+M680X_INS_SLP = 297
+M680X_INS_STA = 298
+M680X_INS_STAA = 299
+M680X_INS_STAB = 300
+M680X_INS_STB = 301
+M680X_INS_STBT = 302
+M680X_INS_STD = 303
+M680X_INS_STE = 304
+M680X_INS_STF = 305
+M680X_INS_STOP = 306
+M680X_INS_STHX = 307
+M680X_INS_STQ = 308
+M680X_INS_STS = 309
+M680X_INS_STU = 310
+M680X_INS_STW = 311
+M680X_INS_STX = 312
+M680X_INS_STY = 313
+M680X_INS_SUB = 314
+M680X_INS_SUBA = 315
+M680X_INS_SUBB = 316
+M680X_INS_SUBD = 317
+M680X_INS_SUBE = 318
+M680X_INS_SUBF = 319
+M680X_INS_SUBR = 320
+M680X_INS_SUBW = 321
+M680X_INS_SWI = 322
+M680X_INS_SWI2 = 323
+M680X_INS_SWI3 = 324
+M680X_INS_SYNC = 325
+M680X_INS_TAB = 326
+M680X_INS_TAP = 327
+M680X_INS_TAX = 328
+M680X_INS_TBA = 329
+M680X_INS_TBEQ = 330
+M680X_INS_TBL = 331
+M680X_INS_TBNE = 332
+M680X_INS_TEST = 333
+M680X_INS_TFM = 334
+M680X_INS_TFR = 335
+M680X_INS_TIM = 336
+M680X_INS_TPA = 337
+M680X_INS_TST = 338
+M680X_INS_TSTA = 339
+M680X_INS_TSTB = 340
+M680X_INS_TSTD = 341
+M680X_INS_TSTE = 342
+M680X_INS_TSTF = 343
+M680X_INS_TSTW = 344
+M680X_INS_TSTX = 345
+M680X_INS_TSX = 346
+M680X_INS_TSY = 347
+M680X_INS_TXA = 348
+M680X_INS_TXS = 349
+M680X_INS_TYS = 350
+M680X_INS_WAI = 351
+M680X_INS_WAIT = 352
+M680X_INS_WAV = 353
+M680X_INS_WAVR = 354
+M680X_INS_XGDX = 355
+M680X_INS_XGDY = 356
+M680X_INS_ENDING = 357

.tools/python-revlibs/capstone/m68k.py

@@ -0,0 +1,100 @@
+# Capstone Python bindings, by Nicolas PLANEL <nplanel@gmail.com>
+
+import ctypes
+from . import copy_ctypes_list
+from .m68k_const import *
+
+# define the API
+class M68KOpMem(ctypes.Structure):
+    _fields_ = (
+        ('base_reg', ctypes.c_uint),
+        ('index_reg', ctypes.c_uint),
+        ('in_base_reg', ctypes.c_uint),
+        ('in_disp', ctypes.c_uint),
+        ('out_disp', ctypes.c_uint),
+        ('disp', ctypes.c_short),
+        ('scale', ctypes.c_ubyte),
+        ('bitfield', ctypes.c_ubyte),
+        ('width', ctypes.c_ubyte),
+        ('offset', ctypes.c_ubyte),
+        ('index_size', ctypes.c_ubyte),
+    )
+
+class M68KOpRegPair(ctypes.Structure):
+    _fields_ = (
+        ('reg_0', ctypes.c_uint),
+        ('reg_1', ctypes.c_uint),
+    )
+
+class M68KOpValue(ctypes.Union):
+    _fields_ = (
+        ('imm', ctypes.c_int64),
+        ('dimm', ctypes.c_double),
+        ('simm', ctypes.c_float),
+        ('reg', ctypes.c_uint),
+        ('reg_pair', M68KOpRegPair),
+    )
+
+class M68KOpBrDisp(ctypes.Structure):
+    _fields_ = (
+        ('disp', ctypes.c_int),
+        ('disp_size', ctypes.c_ubyte),
+    )
+    
+class M68KOp(ctypes.Structure):
+    _fields_ = (
+        ('value', M68KOpValue),
+        ('mem', M68KOpMem),
+        ('br_disp', M68KOpBrDisp),
+        ('register_bits', ctypes.c_uint),
+        ('type', ctypes.c_uint),
+        ('address_mode', ctypes.c_uint),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def dimm(self):
+        return self.value.dimm
+
+    @property
+    def simm(self):
+        return self.value.simm
+
+    @property
+    def reg(self):
+        return self.value.reg
+    
+    @property
+    def reg_pair(self):
+        return self.value.reg_pair
+
+    @property
+    def mem(self):
+        return self.mem
+
+    @property
+    def register_bits(self):
+        return self.register_bits
+
+class M68KOpSize(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('size', ctypes.c_uint),
+    )
+
+    def get(a):
+        return copy_ctypes_list(type, size)
+
+class CsM68K(ctypes.Structure):
+    M68K_OPERAND_COUNT = 4
+    _fields_ = (
+        ('operands', M68KOp * M68K_OPERAND_COUNT),
+        ('op_size', M68KOpSize),
+        ('op_count', ctypes.c_uint8),
+    )
+
+def get_arch_info(a):
+    return (copy_ctypes_list(a.operands[:a.op_count]), a.op_size)

.tools/python-revlibs/capstone/m68k_const.py

@@ -0,0 +1,486 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [m68k_const.py]
+M68K_OPERAND_COUNT = 4
+
+M68K_REG_INVALID = 0
+M68K_REG_D0 = 1
+M68K_REG_D1 = 2
+M68K_REG_D2 = 3
+M68K_REG_D3 = 4
+M68K_REG_D4 = 5
+M68K_REG_D5 = 6
+M68K_REG_D6 = 7
+M68K_REG_D7 = 8
+M68K_REG_A0 = 9
+M68K_REG_A1 = 10
+M68K_REG_A2 = 11
+M68K_REG_A3 = 12
+M68K_REG_A4 = 13
+M68K_REG_A5 = 14
+M68K_REG_A6 = 15
+M68K_REG_A7 = 16
+M68K_REG_FP0 = 17
+M68K_REG_FP1 = 18
+M68K_REG_FP2 = 19
+M68K_REG_FP3 = 20
+M68K_REG_FP4 = 21
+M68K_REG_FP5 = 22
+M68K_REG_FP6 = 23
+M68K_REG_FP7 = 24
+M68K_REG_PC = 25
+M68K_REG_SR = 26
+M68K_REG_CCR = 27
+M68K_REG_SFC = 28
+M68K_REG_DFC = 29
+M68K_REG_USP = 30
+M68K_REG_VBR = 31
+M68K_REG_CACR = 32
+M68K_REG_CAAR = 33
+M68K_REG_MSP = 34
+M68K_REG_ISP = 35
+M68K_REG_TC = 36
+M68K_REG_ITT0 = 37
+M68K_REG_ITT1 = 38
+M68K_REG_DTT0 = 39
+M68K_REG_DTT1 = 40
+M68K_REG_MMUSR = 41
+M68K_REG_URP = 42
+M68K_REG_SRP = 43
+M68K_REG_FPCR = 44
+M68K_REG_FPSR = 45
+M68K_REG_FPIAR = 46
+M68K_REG_ENDING = 47
+
+M68K_AM_NONE = 0
+M68K_AM_REG_DIRECT_DATA = 1
+M68K_AM_REG_DIRECT_ADDR = 2
+M68K_AM_REGI_ADDR = 3
+M68K_AM_REGI_ADDR_POST_INC = 4
+M68K_AM_REGI_ADDR_PRE_DEC = 5
+M68K_AM_REGI_ADDR_DISP = 6
+M68K_AM_AREGI_INDEX_8_BIT_DISP = 7
+M68K_AM_AREGI_INDEX_BASE_DISP = 8
+M68K_AM_MEMI_POST_INDEX = 9
+M68K_AM_MEMI_PRE_INDEX = 10
+M68K_AM_PCI_DISP = 11
+M68K_AM_PCI_INDEX_8_BIT_DISP = 12
+M68K_AM_PCI_INDEX_BASE_DISP = 13
+M68K_AM_PC_MEMI_POST_INDEX = 14
+M68K_AM_PC_MEMI_PRE_INDEX = 15
+M68K_AM_ABSOLUTE_DATA_SHORT = 16
+M68K_AM_ABSOLUTE_DATA_LONG = 17
+M68K_AM_IMMEDIATE = 18
+M68K_AM_BRANCH_DISPLACEMENT = 19
+
+M68K_OP_INVALID = 0
+M68K_OP_REG = 1
+M68K_OP_IMM = 2
+M68K_OP_MEM = 3
+M68K_OP_FP_SINGLE = 4
+M68K_OP_FP_DOUBLE = 5
+M68K_OP_REG_BITS = 6
+M68K_OP_REG_PAIR = 7
+M68K_OP_BR_DISP = 8
+
+M68K_OP_BR_DISP_SIZE_INVALID = 0
+M68K_OP_BR_DISP_SIZE_BYTE = 1
+M68K_OP_BR_DISP_SIZE_WORD = 2
+M68K_OP_BR_DISP_SIZE_LONG = 4
+
+M68K_CPU_SIZE_NONE = 0
+M68K_CPU_SIZE_BYTE = 1
+M68K_CPU_SIZE_WORD = 2
+M68K_CPU_SIZE_LONG = 4
+
+M68K_FPU_SIZE_NONE = 0
+M68K_FPU_SIZE_SINGLE = 4
+M68K_FPU_SIZE_DOUBLE = 8
+M68K_FPU_SIZE_EXTENDED = 12
+
+M68K_SIZE_TYPE_INVALID = 0
+M68K_SIZE_TYPE_CPU = 1
+M68K_SIZE_TYPE_FPU = 2
+
+M68K_INS_INVALID = 0
+M68K_INS_ABCD = 1
+M68K_INS_ADD = 2
+M68K_INS_ADDA = 3
+M68K_INS_ADDI = 4
+M68K_INS_ADDQ = 5
+M68K_INS_ADDX = 6
+M68K_INS_AND = 7
+M68K_INS_ANDI = 8
+M68K_INS_ASL = 9
+M68K_INS_ASR = 10
+M68K_INS_BHS = 11
+M68K_INS_BLO = 12
+M68K_INS_BHI = 13
+M68K_INS_BLS = 14
+M68K_INS_BCC = 15
+M68K_INS_BCS = 16
+M68K_INS_BNE = 17
+M68K_INS_BEQ = 18
+M68K_INS_BVC = 19
+M68K_INS_BVS = 20
+M68K_INS_BPL = 21
+M68K_INS_BMI = 22
+M68K_INS_BGE = 23
+M68K_INS_BLT = 24
+M68K_INS_BGT = 25
+M68K_INS_BLE = 26
+M68K_INS_BRA = 27
+M68K_INS_BSR = 28
+M68K_INS_BCHG = 29
+M68K_INS_BCLR = 30
+M68K_INS_BSET = 31
+M68K_INS_BTST = 32
+M68K_INS_BFCHG = 33
+M68K_INS_BFCLR = 34
+M68K_INS_BFEXTS = 35
+M68K_INS_BFEXTU = 36
+M68K_INS_BFFFO = 37
+M68K_INS_BFINS = 38
+M68K_INS_BFSET = 39
+M68K_INS_BFTST = 40
+M68K_INS_BKPT = 41
+M68K_INS_CALLM = 42
+M68K_INS_CAS = 43
+M68K_INS_CAS2 = 44
+M68K_INS_CHK = 45
+M68K_INS_CHK2 = 46
+M68K_INS_CLR = 47
+M68K_INS_CMP = 48
+M68K_INS_CMPA = 49
+M68K_INS_CMPI = 50
+M68K_INS_CMPM = 51
+M68K_INS_CMP2 = 52
+M68K_INS_CINVL = 53
+M68K_INS_CINVP = 54
+M68K_INS_CINVA = 55
+M68K_INS_CPUSHL = 56
+M68K_INS_CPUSHP = 57
+M68K_INS_CPUSHA = 58
+M68K_INS_DBT = 59
+M68K_INS_DBF = 60
+M68K_INS_DBHI = 61
+M68K_INS_DBLS = 62
+M68K_INS_DBCC = 63
+M68K_INS_DBCS = 64
+M68K_INS_DBNE = 65
+M68K_INS_DBEQ = 66
+M68K_INS_DBVC = 67
+M68K_INS_DBVS = 68
+M68K_INS_DBPL = 69
+M68K_INS_DBMI = 70
+M68K_INS_DBGE = 71
+M68K_INS_DBLT = 72
+M68K_INS_DBGT = 73
+M68K_INS_DBLE = 74
+M68K_INS_DBRA = 75
+M68K_INS_DIVS = 76
+M68K_INS_DIVSL = 77
+M68K_INS_DIVU = 78
+M68K_INS_DIVUL = 79
+M68K_INS_EOR = 80
+M68K_INS_EORI = 81
+M68K_INS_EXG = 82
+M68K_INS_EXT = 83
+M68K_INS_EXTB = 84
+M68K_INS_FABS = 85
+M68K_INS_FSABS = 86
+M68K_INS_FDABS = 87
+M68K_INS_FACOS = 88
+M68K_INS_FADD = 89
+M68K_INS_FSADD = 90
+M68K_INS_FDADD = 91
+M68K_INS_FASIN = 92
+M68K_INS_FATAN = 93
+M68K_INS_FATANH = 94
+M68K_INS_FBF = 95
+M68K_INS_FBEQ = 96
+M68K_INS_FBOGT = 97
+M68K_INS_FBOGE = 98
+M68K_INS_FBOLT = 99
+M68K_INS_FBOLE = 100
+M68K_INS_FBOGL = 101
+M68K_INS_FBOR = 102
+M68K_INS_FBUN = 103
+M68K_INS_FBUEQ = 104
+M68K_INS_FBUGT = 105
+M68K_INS_FBUGE = 106
+M68K_INS_FBULT = 107
+M68K_INS_FBULE = 108
+M68K_INS_FBNE = 109
+M68K_INS_FBT = 110
+M68K_INS_FBSF = 111
+M68K_INS_FBSEQ = 112
+M68K_INS_FBGT = 113
+M68K_INS_FBGE = 114
+M68K_INS_FBLT = 115
+M68K_INS_FBLE = 116
+M68K_INS_FBGL = 117
+M68K_INS_FBGLE = 118
+M68K_INS_FBNGLE = 119
+M68K_INS_FBNGL = 120
+M68K_INS_FBNLE = 121
+M68K_INS_FBNLT = 122
+M68K_INS_FBNGE = 123
+M68K_INS_FBNGT = 124
+M68K_INS_FBSNE = 125
+M68K_INS_FBST = 126
+M68K_INS_FCMP = 127
+M68K_INS_FCOS = 128
+M68K_INS_FCOSH = 129
+M68K_INS_FDBF = 130
+M68K_INS_FDBEQ = 131
+M68K_INS_FDBOGT = 132
+M68K_INS_FDBOGE = 133
+M68K_INS_FDBOLT = 134
+M68K_INS_FDBOLE = 135
+M68K_INS_FDBOGL = 136
+M68K_INS_FDBOR = 137
+M68K_INS_FDBUN = 138
+M68K_INS_FDBUEQ = 139
+M68K_INS_FDBUGT = 140
+M68K_INS_FDBUGE = 141
+M68K_INS_FDBULT = 142
+M68K_INS_FDBULE = 143
+M68K_INS_FDBNE = 144
+M68K_INS_FDBT = 145
+M68K_INS_FDBSF = 146
+M68K_INS_FDBSEQ = 147
+M68K_INS_FDBGT = 148
+M68K_INS_FDBGE = 149
+M68K_INS_FDBLT = 150
+M68K_INS_FDBLE = 151
+M68K_INS_FDBGL = 152
+M68K_INS_FDBGLE = 153
+M68K_INS_FDBNGLE = 154
+M68K_INS_FDBNGL = 155
+M68K_INS_FDBNLE = 156
+M68K_INS_FDBNLT = 157
+M68K_INS_FDBNGE = 158
+M68K_INS_FDBNGT = 159
+M68K_INS_FDBSNE = 160
+M68K_INS_FDBST = 161
+M68K_INS_FDIV = 162
+M68K_INS_FSDIV = 163
+M68K_INS_FDDIV = 164
+M68K_INS_FETOX = 165
+M68K_INS_FETOXM1 = 166
+M68K_INS_FGETEXP = 167
+M68K_INS_FGETMAN = 168
+M68K_INS_FINT = 169
+M68K_INS_FINTRZ = 170
+M68K_INS_FLOG10 = 171
+M68K_INS_FLOG2 = 172
+M68K_INS_FLOGN = 173
+M68K_INS_FLOGNP1 = 174
+M68K_INS_FMOD = 175
+M68K_INS_FMOVE = 176
+M68K_INS_FSMOVE = 177
+M68K_INS_FDMOVE = 178
+M68K_INS_FMOVECR = 179
+M68K_INS_FMOVEM = 180
+M68K_INS_FMUL = 181
+M68K_INS_FSMUL = 182
+M68K_INS_FDMUL = 183
+M68K_INS_FNEG = 184
+M68K_INS_FSNEG = 185
+M68K_INS_FDNEG = 186
+M68K_INS_FNOP = 187
+M68K_INS_FREM = 188
+M68K_INS_FRESTORE = 189
+M68K_INS_FSAVE = 190
+M68K_INS_FSCALE = 191
+M68K_INS_FSGLDIV = 192
+M68K_INS_FSGLMUL = 193
+M68K_INS_FSIN = 194
+M68K_INS_FSINCOS = 195
+M68K_INS_FSINH = 196
+M68K_INS_FSQRT = 197
+M68K_INS_FSSQRT = 198
+M68K_INS_FDSQRT = 199
+M68K_INS_FSF = 200
+M68K_INS_FSBEQ = 201
+M68K_INS_FSOGT = 202
+M68K_INS_FSOGE = 203
+M68K_INS_FSOLT = 204
+M68K_INS_FSOLE = 205
+M68K_INS_FSOGL = 206
+M68K_INS_FSOR = 207
+M68K_INS_FSUN = 208
+M68K_INS_FSUEQ = 209
+M68K_INS_FSUGT = 210
+M68K_INS_FSUGE = 211
+M68K_INS_FSULT = 212
+M68K_INS_FSULE = 213
+M68K_INS_FSNE = 214
+M68K_INS_FST = 215
+M68K_INS_FSSF = 216
+M68K_INS_FSSEQ = 217
+M68K_INS_FSGT = 218
+M68K_INS_FSGE = 219
+M68K_INS_FSLT = 220
+M68K_INS_FSLE = 221
+M68K_INS_FSGL = 222
+M68K_INS_FSGLE = 223
+M68K_INS_FSNGLE = 224
+M68K_INS_FSNGL = 225
+M68K_INS_FSNLE = 226
+M68K_INS_FSNLT = 227
+M68K_INS_FSNGE = 228
+M68K_INS_FSNGT = 229
+M68K_INS_FSSNE = 230
+M68K_INS_FSST = 231
+M68K_INS_FSUB = 232
+M68K_INS_FSSUB = 233
+M68K_INS_FDSUB = 234
+M68K_INS_FTAN = 235
+M68K_INS_FTANH = 236
+M68K_INS_FTENTOX = 237
+M68K_INS_FTRAPF = 238
+M68K_INS_FTRAPEQ = 239
+M68K_INS_FTRAPOGT = 240
+M68K_INS_FTRAPOGE = 241
+M68K_INS_FTRAPOLT = 242
+M68K_INS_FTRAPOLE = 243
+M68K_INS_FTRAPOGL = 244
+M68K_INS_FTRAPOR = 245
+M68K_INS_FTRAPUN = 246
+M68K_INS_FTRAPUEQ = 247
+M68K_INS_FTRAPUGT = 248
+M68K_INS_FTRAPUGE = 249
+M68K_INS_FTRAPULT = 250
+M68K_INS_FTRAPULE = 251
+M68K_INS_FTRAPNE = 252
+M68K_INS_FTRAPT = 253
+M68K_INS_FTRAPSF = 254
+M68K_INS_FTRAPSEQ = 255
+M68K_INS_FTRAPGT = 256
+M68K_INS_FTRAPGE = 257
+M68K_INS_FTRAPLT = 258
+M68K_INS_FTRAPLE = 259
+M68K_INS_FTRAPGL = 260
+M68K_INS_FTRAPGLE = 261
+M68K_INS_FTRAPNGLE = 262
+M68K_INS_FTRAPNGL = 263
+M68K_INS_FTRAPNLE = 264
+M68K_INS_FTRAPNLT = 265
+M68K_INS_FTRAPNGE = 266
+M68K_INS_FTRAPNGT = 267
+M68K_INS_FTRAPSNE = 268
+M68K_INS_FTRAPST = 269
+M68K_INS_FTST = 270
+M68K_INS_FTWOTOX = 271
+M68K_INS_HALT = 272
+M68K_INS_ILLEGAL = 273
+M68K_INS_JMP = 274
+M68K_INS_JSR = 275
+M68K_INS_LEA = 276
+M68K_INS_LINK = 277
+M68K_INS_LPSTOP = 278
+M68K_INS_LSL = 279
+M68K_INS_LSR = 280
+M68K_INS_MOVE = 281
+M68K_INS_MOVEA = 282
+M68K_INS_MOVEC = 283
+M68K_INS_MOVEM = 284
+M68K_INS_MOVEP = 285
+M68K_INS_MOVEQ = 286
+M68K_INS_MOVES = 287
+M68K_INS_MOVE16 = 288
+M68K_INS_MULS = 289
+M68K_INS_MULU = 290
+M68K_INS_NBCD = 291
+M68K_INS_NEG = 292
+M68K_INS_NEGX = 293
+M68K_INS_NOP = 294
+M68K_INS_NOT = 295
+M68K_INS_OR = 296
+M68K_INS_ORI = 297
+M68K_INS_PACK = 298
+M68K_INS_PEA = 299
+M68K_INS_PFLUSH = 300
+M68K_INS_PFLUSHA = 301
+M68K_INS_PFLUSHAN = 302
+M68K_INS_PFLUSHN = 303
+M68K_INS_PLOADR = 304
+M68K_INS_PLOADW = 305
+M68K_INS_PLPAR = 306
+M68K_INS_PLPAW = 307
+M68K_INS_PMOVE = 308
+M68K_INS_PMOVEFD = 309
+M68K_INS_PTESTR = 310
+M68K_INS_PTESTW = 311
+M68K_INS_PULSE = 312
+M68K_INS_REMS = 313
+M68K_INS_REMU = 314
+M68K_INS_RESET = 315
+M68K_INS_ROL = 316
+M68K_INS_ROR = 317
+M68K_INS_ROXL = 318
+M68K_INS_ROXR = 319
+M68K_INS_RTD = 320
+M68K_INS_RTE = 321
+M68K_INS_RTM = 322
+M68K_INS_RTR = 323
+M68K_INS_RTS = 324
+M68K_INS_SBCD = 325
+M68K_INS_ST = 326
+M68K_INS_SF = 327
+M68K_INS_SHI = 328
+M68K_INS_SLS = 329
+M68K_INS_SCC = 330
+M68K_INS_SHS = 331
+M68K_INS_SCS = 332
+M68K_INS_SLO = 333
+M68K_INS_SNE = 334
+M68K_INS_SEQ = 335
+M68K_INS_SVC = 336
+M68K_INS_SVS = 337
+M68K_INS_SPL = 338
+M68K_INS_SMI = 339
+M68K_INS_SGE = 340
+M68K_INS_SLT = 341
+M68K_INS_SGT = 342
+M68K_INS_SLE = 343
+M68K_INS_STOP = 344
+M68K_INS_SUB = 345
+M68K_INS_SUBA = 346
+M68K_INS_SUBI = 347
+M68K_INS_SUBQ = 348
+M68K_INS_SUBX = 349
+M68K_INS_SWAP = 350
+M68K_INS_TAS = 351
+M68K_INS_TRAP = 352
+M68K_INS_TRAPV = 353
+M68K_INS_TRAPT = 354
+M68K_INS_TRAPF = 355
+M68K_INS_TRAPHI = 356
+M68K_INS_TRAPLS = 357
+M68K_INS_TRAPCC = 358
+M68K_INS_TRAPHS = 359
+M68K_INS_TRAPCS = 360
+M68K_INS_TRAPLO = 361
+M68K_INS_TRAPNE = 362
+M68K_INS_TRAPEQ = 363
+M68K_INS_TRAPVC = 364
+M68K_INS_TRAPVS = 365
+M68K_INS_TRAPPL = 366
+M68K_INS_TRAPMI = 367
+M68K_INS_TRAPGE = 368
+M68K_INS_TRAPLT = 369
+M68K_INS_TRAPGT = 370
+M68K_INS_TRAPLE = 371
+M68K_INS_TST = 372
+M68K_INS_UNLK = 373
+M68K_INS_UNPK = 374
+M68K_INS_ENDING = 375
+
+M68K_GRP_INVALID = 0
+M68K_GRP_JUMP = 1
+M68K_GRP_RET = 3
+M68K_GRP_IRET = 5
+M68K_GRP_BRANCH_RELATIVE = 7
+M68K_GRP_ENDING = 8

.tools/python-revlibs/capstone/mips.py

@@ -0,0 +1,48 @@
+# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
+
+import ctypes
+from . import copy_ctypes_list
+from .mips_const import *
+
+# define the API
+class MipsOpMem(ctypes.Structure):
+    _fields_ = (
+        ('base', ctypes.c_uint),
+        ('disp', ctypes.c_int64),
+    )
+
+class MipsOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_int64),
+        ('mem', MipsOpMem),
+    )
+
+class MipsOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', MipsOpValue),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+
+class CsMips(ctypes.Structure):
+    _fields_ = (
+        ('op_count', ctypes.c_uint8),
+        ('operands', MipsOp * 10),
+    )
+
+def get_arch_info(a):
+    return copy_ctypes_list(a.operands[:a.op_count])
+

.tools/python-revlibs/capstone/mips_const.py

@@ -0,0 +1,862 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.py]
+
+MIPS_OP_INVALID = 0
+MIPS_OP_REG = 1
+MIPS_OP_IMM = 2
+MIPS_OP_MEM = 3
+
+MIPS_REG_INVALID = 0
+MIPS_REG_PC = 1
+MIPS_REG_0 = 2
+MIPS_REG_1 = 3
+MIPS_REG_2 = 4
+MIPS_REG_3 = 5
+MIPS_REG_4 = 6
+MIPS_REG_5 = 7
+MIPS_REG_6 = 8
+MIPS_REG_7 = 9
+MIPS_REG_8 = 10
+MIPS_REG_9 = 11
+MIPS_REG_10 = 12
+MIPS_REG_11 = 13
+MIPS_REG_12 = 14
+MIPS_REG_13 = 15
+MIPS_REG_14 = 16
+MIPS_REG_15 = 17
+MIPS_REG_16 = 18
+MIPS_REG_17 = 19
+MIPS_REG_18 = 20
+MIPS_REG_19 = 21
+MIPS_REG_20 = 22
+MIPS_REG_21 = 23
+MIPS_REG_22 = 24
+MIPS_REG_23 = 25
+MIPS_REG_24 = 26
+MIPS_REG_25 = 27
+MIPS_REG_26 = 28
+MIPS_REG_27 = 29
+MIPS_REG_28 = 30
+MIPS_REG_29 = 31
+MIPS_REG_30 = 32
+MIPS_REG_31 = 33
+MIPS_REG_DSPCCOND = 34
+MIPS_REG_DSPCARRY = 35
+MIPS_REG_DSPEFI = 36
+MIPS_REG_DSPOUTFLAG = 37
+MIPS_REG_DSPOUTFLAG16_19 = 38
+MIPS_REG_DSPOUTFLAG20 = 39
+MIPS_REG_DSPOUTFLAG21 = 40
+MIPS_REG_DSPOUTFLAG22 = 41
+MIPS_REG_DSPOUTFLAG23 = 42
+MIPS_REG_DSPPOS = 43
+MIPS_REG_DSPSCOUNT = 44
+MIPS_REG_AC0 = 45
+MIPS_REG_AC1 = 46
+MIPS_REG_AC2 = 47
+MIPS_REG_AC3 = 48
+MIPS_REG_CC0 = 49
+MIPS_REG_CC1 = 50
+MIPS_REG_CC2 = 51
+MIPS_REG_CC3 = 52
+MIPS_REG_CC4 = 53
+MIPS_REG_CC5 = 54
+MIPS_REG_CC6 = 55
+MIPS_REG_CC7 = 56
+MIPS_REG_F0 = 57
+MIPS_REG_F1 = 58
+MIPS_REG_F2 = 59
+MIPS_REG_F3 = 60
+MIPS_REG_F4 = 61
+MIPS_REG_F5 = 62
+MIPS_REG_F6 = 63
+MIPS_REG_F7 = 64
+MIPS_REG_F8 = 65
+MIPS_REG_F9 = 66
+MIPS_REG_F10 = 67
+MIPS_REG_F11 = 68
+MIPS_REG_F12 = 69
+MIPS_REG_F13 = 70
+MIPS_REG_F14 = 71
+MIPS_REG_F15 = 72
+MIPS_REG_F16 = 73
+MIPS_REG_F17 = 74
+MIPS_REG_F18 = 75
+MIPS_REG_F19 = 76
+MIPS_REG_F20 = 77
+MIPS_REG_F21 = 78
+MIPS_REG_F22 = 79
+MIPS_REG_F23 = 80
+MIPS_REG_F24 = 81
+MIPS_REG_F25 = 82
+MIPS_REG_F26 = 83
+MIPS_REG_F27 = 84
+MIPS_REG_F28 = 85
+MIPS_REG_F29 = 86
+MIPS_REG_F30 = 87
+MIPS_REG_F31 = 88
+MIPS_REG_FCC0 = 89
+MIPS_REG_FCC1 = 90
+MIPS_REG_FCC2 = 91
+MIPS_REG_FCC3 = 92
+MIPS_REG_FCC4 = 93
+MIPS_REG_FCC5 = 94
+MIPS_REG_FCC6 = 95
+MIPS_REG_FCC7 = 96
+MIPS_REG_W0 = 97
+MIPS_REG_W1 = 98
+MIPS_REG_W2 = 99
+MIPS_REG_W3 = 100
+MIPS_REG_W4 = 101
+MIPS_REG_W5 = 102
+MIPS_REG_W6 = 103
+MIPS_REG_W7 = 104
+MIPS_REG_W8 = 105
+MIPS_REG_W9 = 106
+MIPS_REG_W10 = 107
+MIPS_REG_W11 = 108
+MIPS_REG_W12 = 109
+MIPS_REG_W13 = 110
+MIPS_REG_W14 = 111
+MIPS_REG_W15 = 112
+MIPS_REG_W16 = 113
+MIPS_REG_W17 = 114
+MIPS_REG_W18 = 115
+MIPS_REG_W19 = 116
+MIPS_REG_W20 = 117
+MIPS_REG_W21 = 118
+MIPS_REG_W22 = 119
+MIPS_REG_W23 = 120
+MIPS_REG_W24 = 121
+MIPS_REG_W25 = 122
+MIPS_REG_W26 = 123
+MIPS_REG_W27 = 124
+MIPS_REG_W28 = 125
+MIPS_REG_W29 = 126
+MIPS_REG_W30 = 127
+MIPS_REG_W31 = 128
+MIPS_REG_HI = 129
+MIPS_REG_LO = 130
+MIPS_REG_P0 = 131
+MIPS_REG_P1 = 132
+MIPS_REG_P2 = 133
+MIPS_REG_MPL0 = 134
+MIPS_REG_MPL1 = 135
+MIPS_REG_MPL2 = 136
+MIPS_REG_ENDING = 137
+MIPS_REG_ZERO = MIPS_REG_0
+MIPS_REG_AT = MIPS_REG_1
+MIPS_REG_V0 = MIPS_REG_2
+MIPS_REG_V1 = MIPS_REG_3
+MIPS_REG_A0 = MIPS_REG_4
+MIPS_REG_A1 = MIPS_REG_5
+MIPS_REG_A2 = MIPS_REG_6
+MIPS_REG_A3 = MIPS_REG_7
+MIPS_REG_T0 = MIPS_REG_8
+MIPS_REG_T1 = MIPS_REG_9
+MIPS_REG_T2 = MIPS_REG_10
+MIPS_REG_T3 = MIPS_REG_11
+MIPS_REG_T4 = MIPS_REG_12
+MIPS_REG_T5 = MIPS_REG_13
+MIPS_REG_T6 = MIPS_REG_14
+MIPS_REG_T7 = MIPS_REG_15
+MIPS_REG_S0 = MIPS_REG_16
+MIPS_REG_S1 = MIPS_REG_17
+MIPS_REG_S2 = MIPS_REG_18
+MIPS_REG_S3 = MIPS_REG_19
+MIPS_REG_S4 = MIPS_REG_20
+MIPS_REG_S5 = MIPS_REG_21
+MIPS_REG_S6 = MIPS_REG_22
+MIPS_REG_S7 = MIPS_REG_23
+MIPS_REG_T8 = MIPS_REG_24
+MIPS_REG_T9 = MIPS_REG_25
+MIPS_REG_K0 = MIPS_REG_26
+MIPS_REG_K1 = MIPS_REG_27
+MIPS_REG_GP = MIPS_REG_28
+MIPS_REG_SP = MIPS_REG_29
+MIPS_REG_FP = MIPS_REG_30
+MIPS_REG_S8 = MIPS_REG_30
+MIPS_REG_RA = MIPS_REG_31
+MIPS_REG_HI0 = MIPS_REG_AC0
+MIPS_REG_HI1 = MIPS_REG_AC1
+MIPS_REG_HI2 = MIPS_REG_AC2
+MIPS_REG_HI3 = MIPS_REG_AC3
+MIPS_REG_LO0 = MIPS_REG_HI0
+MIPS_REG_LO1 = MIPS_REG_HI1
+MIPS_REG_LO2 = MIPS_REG_HI2
+MIPS_REG_LO3 = MIPS_REG_HI3
+
+MIPS_INS_INVALID = 0
+MIPS_INS_ABSQ_S = 1
+MIPS_INS_ADD = 2
+MIPS_INS_ADDIUPC = 3
+MIPS_INS_ADDIUR1SP = 4
+MIPS_INS_ADDIUR2 = 5
+MIPS_INS_ADDIUS5 = 6
+MIPS_INS_ADDIUSP = 7
+MIPS_INS_ADDQH = 8
+MIPS_INS_ADDQH_R = 9
+MIPS_INS_ADDQ = 10
+MIPS_INS_ADDQ_S = 11
+MIPS_INS_ADDSC = 12
+MIPS_INS_ADDS_A = 13
+MIPS_INS_ADDS_S = 14
+MIPS_INS_ADDS_U = 15
+MIPS_INS_ADDU16 = 16
+MIPS_INS_ADDUH = 17
+MIPS_INS_ADDUH_R = 18
+MIPS_INS_ADDU = 19
+MIPS_INS_ADDU_S = 20
+MIPS_INS_ADDVI = 21
+MIPS_INS_ADDV = 22
+MIPS_INS_ADDWC = 23
+MIPS_INS_ADD_A = 24
+MIPS_INS_ADDI = 25
+MIPS_INS_ADDIU = 26
+MIPS_INS_ALIGN = 27
+MIPS_INS_ALUIPC = 28
+MIPS_INS_AND = 29
+MIPS_INS_AND16 = 30
+MIPS_INS_ANDI16 = 31
+MIPS_INS_ANDI = 32
+MIPS_INS_APPEND = 33
+MIPS_INS_ASUB_S = 34
+MIPS_INS_ASUB_U = 35
+MIPS_INS_AUI = 36
+MIPS_INS_AUIPC = 37
+MIPS_INS_AVER_S = 38
+MIPS_INS_AVER_U = 39
+MIPS_INS_AVE_S = 40
+MIPS_INS_AVE_U = 41
+MIPS_INS_B16 = 42
+MIPS_INS_BADDU = 43
+MIPS_INS_BAL = 44
+MIPS_INS_BALC = 45
+MIPS_INS_BALIGN = 46
+MIPS_INS_BBIT0 = 47
+MIPS_INS_BBIT032 = 48
+MIPS_INS_BBIT1 = 49
+MIPS_INS_BBIT132 = 50
+MIPS_INS_BC = 51
+MIPS_INS_BC0F = 52
+MIPS_INS_BC0FL = 53
+MIPS_INS_BC0T = 54
+MIPS_INS_BC0TL = 55
+MIPS_INS_BC1EQZ = 56
+MIPS_INS_BC1F = 57
+MIPS_INS_BC1FL = 58
+MIPS_INS_BC1NEZ = 59
+MIPS_INS_BC1T = 60
+MIPS_INS_BC1TL = 61
+MIPS_INS_BC2EQZ = 62
+MIPS_INS_BC2F = 63
+MIPS_INS_BC2FL = 64
+MIPS_INS_BC2NEZ = 65
+MIPS_INS_BC2T = 66
+MIPS_INS_BC2TL = 67
+MIPS_INS_BC3F = 68
+MIPS_INS_BC3FL = 69
+MIPS_INS_BC3T = 70
+MIPS_INS_BC3TL = 71
+MIPS_INS_BCLRI = 72
+MIPS_INS_BCLR = 73
+MIPS_INS_BEQ = 74
+MIPS_INS_BEQC = 75
+MIPS_INS_BEQL = 76
+MIPS_INS_BEQZ16 = 77
+MIPS_INS_BEQZALC = 78
+MIPS_INS_BEQZC = 79
+MIPS_INS_BGEC = 80
+MIPS_INS_BGEUC = 81
+MIPS_INS_BGEZ = 82
+MIPS_INS_BGEZAL = 83
+MIPS_INS_BGEZALC = 84
+MIPS_INS_BGEZALL = 85
+MIPS_INS_BGEZALS = 86
+MIPS_INS_BGEZC = 87
+MIPS_INS_BGEZL = 88
+MIPS_INS_BGTZ = 89
+MIPS_INS_BGTZALC = 90
+MIPS_INS_BGTZC = 91
+MIPS_INS_BGTZL = 92
+MIPS_INS_BINSLI = 93
+MIPS_INS_BINSL = 94
+MIPS_INS_BINSRI = 95
+MIPS_INS_BINSR = 96
+MIPS_INS_BITREV = 97
+MIPS_INS_BITSWAP = 98
+MIPS_INS_BLEZ = 99
+MIPS_INS_BLEZALC = 100
+MIPS_INS_BLEZC = 101
+MIPS_INS_BLEZL = 102
+MIPS_INS_BLTC = 103
+MIPS_INS_BLTUC = 104
+MIPS_INS_BLTZ = 105
+MIPS_INS_BLTZAL = 106
+MIPS_INS_BLTZALC = 107
+MIPS_INS_BLTZALL = 108
+MIPS_INS_BLTZALS = 109
+MIPS_INS_BLTZC = 110
+MIPS_INS_BLTZL = 111
+MIPS_INS_BMNZI = 112
+MIPS_INS_BMNZ = 113
+MIPS_INS_BMZI = 114
+MIPS_INS_BMZ = 115
+MIPS_INS_BNE = 116
+MIPS_INS_BNEC = 117
+MIPS_INS_BNEGI = 118
+MIPS_INS_BNEG = 119
+MIPS_INS_BNEL = 120
+MIPS_INS_BNEZ16 = 121
+MIPS_INS_BNEZALC = 122
+MIPS_INS_BNEZC = 123
+MIPS_INS_BNVC = 124
+MIPS_INS_BNZ = 125
+MIPS_INS_BOVC = 126
+MIPS_INS_BPOSGE32 = 127
+MIPS_INS_BREAK = 128
+MIPS_INS_BREAK16 = 129
+MIPS_INS_BSELI = 130
+MIPS_INS_BSEL = 131
+MIPS_INS_BSETI = 132
+MIPS_INS_BSET = 133
+MIPS_INS_BZ = 134
+MIPS_INS_BEQZ = 135
+MIPS_INS_B = 136
+MIPS_INS_BNEZ = 137
+MIPS_INS_BTEQZ = 138
+MIPS_INS_BTNEZ = 139
+MIPS_INS_CACHE = 140
+MIPS_INS_CEIL = 141
+MIPS_INS_CEQI = 142
+MIPS_INS_CEQ = 143
+MIPS_INS_CFC1 = 144
+MIPS_INS_CFCMSA = 145
+MIPS_INS_CINS = 146
+MIPS_INS_CINS32 = 147
+MIPS_INS_CLASS = 148
+MIPS_INS_CLEI_S = 149
+MIPS_INS_CLEI_U = 150
+MIPS_INS_CLE_S = 151
+MIPS_INS_CLE_U = 152
+MIPS_INS_CLO = 153
+MIPS_INS_CLTI_S = 154
+MIPS_INS_CLTI_U = 155
+MIPS_INS_CLT_S = 156
+MIPS_INS_CLT_U = 157
+MIPS_INS_CLZ = 158
+MIPS_INS_CMPGDU = 159
+MIPS_INS_CMPGU = 160
+MIPS_INS_CMPU = 161
+MIPS_INS_CMP = 162
+MIPS_INS_COPY_S = 163
+MIPS_INS_COPY_U = 164
+MIPS_INS_CTC1 = 165
+MIPS_INS_CTCMSA = 166
+MIPS_INS_CVT = 167
+MIPS_INS_C = 168
+MIPS_INS_CMPI = 169
+MIPS_INS_DADD = 170
+MIPS_INS_DADDI = 171
+MIPS_INS_DADDIU = 172
+MIPS_INS_DADDU = 173
+MIPS_INS_DAHI = 174
+MIPS_INS_DALIGN = 175
+MIPS_INS_DATI = 176
+MIPS_INS_DAUI = 177
+MIPS_INS_DBITSWAP = 178
+MIPS_INS_DCLO = 179
+MIPS_INS_DCLZ = 180
+MIPS_INS_DDIV = 181
+MIPS_INS_DDIVU = 182
+MIPS_INS_DERET = 183
+MIPS_INS_DEXT = 184
+MIPS_INS_DEXTM = 185
+MIPS_INS_DEXTU = 186
+MIPS_INS_DI = 187
+MIPS_INS_DINS = 188
+MIPS_INS_DINSM = 189
+MIPS_INS_DINSU = 190
+MIPS_INS_DIV = 191
+MIPS_INS_DIVU = 192
+MIPS_INS_DIV_S = 193
+MIPS_INS_DIV_U = 194
+MIPS_INS_DLSA = 195
+MIPS_INS_DMFC0 = 196
+MIPS_INS_DMFC1 = 197
+MIPS_INS_DMFC2 = 198
+MIPS_INS_DMOD = 199
+MIPS_INS_DMODU = 200
+MIPS_INS_DMTC0 = 201
+MIPS_INS_DMTC1 = 202
+MIPS_INS_DMTC2 = 203
+MIPS_INS_DMUH = 204
+MIPS_INS_DMUHU = 205
+MIPS_INS_DMUL = 206
+MIPS_INS_DMULT = 207
+MIPS_INS_DMULTU = 208
+MIPS_INS_DMULU = 209
+MIPS_INS_DOTP_S = 210
+MIPS_INS_DOTP_U = 211
+MIPS_INS_DPADD_S = 212
+MIPS_INS_DPADD_U = 213
+MIPS_INS_DPAQX_SA = 214
+MIPS_INS_DPAQX_S = 215
+MIPS_INS_DPAQ_SA = 216
+MIPS_INS_DPAQ_S = 217
+MIPS_INS_DPAU = 218
+MIPS_INS_DPAX = 219
+MIPS_INS_DPA = 220
+MIPS_INS_DPOP = 221
+MIPS_INS_DPSQX_SA = 222
+MIPS_INS_DPSQX_S = 223
+MIPS_INS_DPSQ_SA = 224
+MIPS_INS_DPSQ_S = 225
+MIPS_INS_DPSUB_S = 226
+MIPS_INS_DPSUB_U = 227
+MIPS_INS_DPSU = 228
+MIPS_INS_DPSX = 229
+MIPS_INS_DPS = 230
+MIPS_INS_DROTR = 231
+MIPS_INS_DROTR32 = 232
+MIPS_INS_DROTRV = 233
+MIPS_INS_DSBH = 234
+MIPS_INS_DSHD = 235
+MIPS_INS_DSLL = 236
+MIPS_INS_DSLL32 = 237
+MIPS_INS_DSLLV = 238
+MIPS_INS_DSRA = 239
+MIPS_INS_DSRA32 = 240
+MIPS_INS_DSRAV = 241
+MIPS_INS_DSRL = 242
+MIPS_INS_DSRL32 = 243
+MIPS_INS_DSRLV = 244
+MIPS_INS_DSUB = 245
+MIPS_INS_DSUBU = 246
+MIPS_INS_EHB = 247
+MIPS_INS_EI = 248
+MIPS_INS_ERET = 249
+MIPS_INS_EXT = 250
+MIPS_INS_EXTP = 251
+MIPS_INS_EXTPDP = 252
+MIPS_INS_EXTPDPV = 253
+MIPS_INS_EXTPV = 254
+MIPS_INS_EXTRV_RS = 255
+MIPS_INS_EXTRV_R = 256
+MIPS_INS_EXTRV_S = 257
+MIPS_INS_EXTRV = 258
+MIPS_INS_EXTR_RS = 259
+MIPS_INS_EXTR_R = 260
+MIPS_INS_EXTR_S = 261
+MIPS_INS_EXTR = 262
+MIPS_INS_EXTS = 263
+MIPS_INS_EXTS32 = 264
+MIPS_INS_ABS = 265
+MIPS_INS_FADD = 266
+MIPS_INS_FCAF = 267
+MIPS_INS_FCEQ = 268
+MIPS_INS_FCLASS = 269
+MIPS_INS_FCLE = 270
+MIPS_INS_FCLT = 271
+MIPS_INS_FCNE = 272
+MIPS_INS_FCOR = 273
+MIPS_INS_FCUEQ = 274
+MIPS_INS_FCULE = 275
+MIPS_INS_FCULT = 276
+MIPS_INS_FCUNE = 277
+MIPS_INS_FCUN = 278
+MIPS_INS_FDIV = 279
+MIPS_INS_FEXDO = 280
+MIPS_INS_FEXP2 = 281
+MIPS_INS_FEXUPL = 282
+MIPS_INS_FEXUPR = 283
+MIPS_INS_FFINT_S = 284
+MIPS_INS_FFINT_U = 285
+MIPS_INS_FFQL = 286
+MIPS_INS_FFQR = 287
+MIPS_INS_FILL = 288
+MIPS_INS_FLOG2 = 289
+MIPS_INS_FLOOR = 290
+MIPS_INS_FMADD = 291
+MIPS_INS_FMAX_A = 292
+MIPS_INS_FMAX = 293
+MIPS_INS_FMIN_A = 294
+MIPS_INS_FMIN = 295
+MIPS_INS_MOV = 296
+MIPS_INS_FMSUB = 297
+MIPS_INS_FMUL = 298
+MIPS_INS_MUL = 299
+MIPS_INS_NEG = 300
+MIPS_INS_FRCP = 301
+MIPS_INS_FRINT = 302
+MIPS_INS_FRSQRT = 303
+MIPS_INS_FSAF = 304
+MIPS_INS_FSEQ = 305
+MIPS_INS_FSLE = 306
+MIPS_INS_FSLT = 307
+MIPS_INS_FSNE = 308
+MIPS_INS_FSOR = 309
+MIPS_INS_FSQRT = 310
+MIPS_INS_SQRT = 311
+MIPS_INS_FSUB = 312
+MIPS_INS_SUB = 313
+MIPS_INS_FSUEQ = 314
+MIPS_INS_FSULE = 315
+MIPS_INS_FSULT = 316
+MIPS_INS_FSUNE = 317
+MIPS_INS_FSUN = 318
+MIPS_INS_FTINT_S = 319
+MIPS_INS_FTINT_U = 320
+MIPS_INS_FTQ = 321
+MIPS_INS_FTRUNC_S = 322
+MIPS_INS_FTRUNC_U = 323
+MIPS_INS_HADD_S = 324
+MIPS_INS_HADD_U = 325
+MIPS_INS_HSUB_S = 326
+MIPS_INS_HSUB_U = 327
+MIPS_INS_ILVEV = 328
+MIPS_INS_ILVL = 329
+MIPS_INS_ILVOD = 330
+MIPS_INS_ILVR = 331
+MIPS_INS_INS = 332
+MIPS_INS_INSERT = 333
+MIPS_INS_INSV = 334
+MIPS_INS_INSVE = 335
+MIPS_INS_J = 336
+MIPS_INS_JAL = 337
+MIPS_INS_JALR = 338
+MIPS_INS_JALRS16 = 339
+MIPS_INS_JALRS = 340
+MIPS_INS_JALS = 341
+MIPS_INS_JALX = 342
+MIPS_INS_JIALC = 343
+MIPS_INS_JIC = 344
+MIPS_INS_JR = 345
+MIPS_INS_JR16 = 346
+MIPS_INS_JRADDIUSP = 347
+MIPS_INS_JRC = 348
+MIPS_INS_JALRC = 349
+MIPS_INS_LB = 350
+MIPS_INS_LBU16 = 351
+MIPS_INS_LBUX = 352
+MIPS_INS_LBU = 353
+MIPS_INS_LD = 354
+MIPS_INS_LDC1 = 355
+MIPS_INS_LDC2 = 356
+MIPS_INS_LDC3 = 357
+MIPS_INS_LDI = 358
+MIPS_INS_LDL = 359
+MIPS_INS_LDPC = 360
+MIPS_INS_LDR = 361
+MIPS_INS_LDXC1 = 362
+MIPS_INS_LH = 363
+MIPS_INS_LHU16 = 364
+MIPS_INS_LHX = 365
+MIPS_INS_LHU = 366
+MIPS_INS_LI16 = 367
+MIPS_INS_LL = 368
+MIPS_INS_LLD = 369
+MIPS_INS_LSA = 370
+MIPS_INS_LUXC1 = 371
+MIPS_INS_LUI = 372
+MIPS_INS_LW = 373
+MIPS_INS_LW16 = 374
+MIPS_INS_LWC1 = 375
+MIPS_INS_LWC2 = 376
+MIPS_INS_LWC3 = 377
+MIPS_INS_LWL = 378
+MIPS_INS_LWM16 = 379
+MIPS_INS_LWM32 = 380
+MIPS_INS_LWPC = 381
+MIPS_INS_LWP = 382
+MIPS_INS_LWR = 383
+MIPS_INS_LWUPC = 384
+MIPS_INS_LWU = 385
+MIPS_INS_LWX = 386
+MIPS_INS_LWXC1 = 387
+MIPS_INS_LWXS = 388
+MIPS_INS_LI = 389
+MIPS_INS_MADD = 390
+MIPS_INS_MADDF = 391
+MIPS_INS_MADDR_Q = 392
+MIPS_INS_MADDU = 393
+MIPS_INS_MADDV = 394
+MIPS_INS_MADD_Q = 395
+MIPS_INS_MAQ_SA = 396
+MIPS_INS_MAQ_S = 397
+MIPS_INS_MAXA = 398
+MIPS_INS_MAXI_S = 399
+MIPS_INS_MAXI_U = 400
+MIPS_INS_MAX_A = 401
+MIPS_INS_MAX = 402
+MIPS_INS_MAX_S = 403
+MIPS_INS_MAX_U = 404
+MIPS_INS_MFC0 = 405
+MIPS_INS_MFC1 = 406
+MIPS_INS_MFC2 = 407
+MIPS_INS_MFHC1 = 408
+MIPS_INS_MFHI = 409
+MIPS_INS_MFLO = 410
+MIPS_INS_MINA = 411
+MIPS_INS_MINI_S = 412
+MIPS_INS_MINI_U = 413
+MIPS_INS_MIN_A = 414
+MIPS_INS_MIN = 415
+MIPS_INS_MIN_S = 416
+MIPS_INS_MIN_U = 417
+MIPS_INS_MOD = 418
+MIPS_INS_MODSUB = 419
+MIPS_INS_MODU = 420
+MIPS_INS_MOD_S = 421
+MIPS_INS_MOD_U = 422
+MIPS_INS_MOVE = 423
+MIPS_INS_MOVEP = 424
+MIPS_INS_MOVF = 425
+MIPS_INS_MOVN = 426
+MIPS_INS_MOVT = 427
+MIPS_INS_MOVZ = 428
+MIPS_INS_MSUB = 429
+MIPS_INS_MSUBF = 430
+MIPS_INS_MSUBR_Q = 431
+MIPS_INS_MSUBU = 432
+MIPS_INS_MSUBV = 433
+MIPS_INS_MSUB_Q = 434
+MIPS_INS_MTC0 = 435
+MIPS_INS_MTC1 = 436
+MIPS_INS_MTC2 = 437
+MIPS_INS_MTHC1 = 438
+MIPS_INS_MTHI = 439
+MIPS_INS_MTHLIP = 440
+MIPS_INS_MTLO = 441
+MIPS_INS_MTM0 = 442
+MIPS_INS_MTM1 = 443
+MIPS_INS_MTM2 = 444
+MIPS_INS_MTP0 = 445
+MIPS_INS_MTP1 = 446
+MIPS_INS_MTP2 = 447
+MIPS_INS_MUH = 448
+MIPS_INS_MUHU = 449
+MIPS_INS_MULEQ_S = 450
+MIPS_INS_MULEU_S = 451
+MIPS_INS_MULQ_RS = 452
+MIPS_INS_MULQ_S = 453
+MIPS_INS_MULR_Q = 454
+MIPS_INS_MULSAQ_S = 455
+MIPS_INS_MULSA = 456
+MIPS_INS_MULT = 457
+MIPS_INS_MULTU = 458
+MIPS_INS_MULU = 459
+MIPS_INS_MULV = 460
+MIPS_INS_MUL_Q = 461
+MIPS_INS_MUL_S = 462
+MIPS_INS_NLOC = 463
+MIPS_INS_NLZC = 464
+MIPS_INS_NMADD = 465
+MIPS_INS_NMSUB = 466
+MIPS_INS_NOR = 467
+MIPS_INS_NORI = 468
+MIPS_INS_NOT16 = 469
+MIPS_INS_NOT = 470
+MIPS_INS_OR = 471
+MIPS_INS_OR16 = 472
+MIPS_INS_ORI = 473
+MIPS_INS_PACKRL = 474
+MIPS_INS_PAUSE = 475
+MIPS_INS_PCKEV = 476
+MIPS_INS_PCKOD = 477
+MIPS_INS_PCNT = 478
+MIPS_INS_PICK = 479
+MIPS_INS_POP = 480
+MIPS_INS_PRECEQU = 481
+MIPS_INS_PRECEQ = 482
+MIPS_INS_PRECEU = 483
+MIPS_INS_PRECRQU_S = 484
+MIPS_INS_PRECRQ = 485
+MIPS_INS_PRECRQ_RS = 486
+MIPS_INS_PRECR = 487
+MIPS_INS_PRECR_SRA = 488
+MIPS_INS_PRECR_SRA_R = 489
+MIPS_INS_PREF = 490
+MIPS_INS_PREPEND = 491
+MIPS_INS_RADDU = 492
+MIPS_INS_RDDSP = 493
+MIPS_INS_RDHWR = 494
+MIPS_INS_REPLV = 495
+MIPS_INS_REPL = 496
+MIPS_INS_RINT = 497
+MIPS_INS_ROTR = 498
+MIPS_INS_ROTRV = 499
+MIPS_INS_ROUND = 500
+MIPS_INS_SAT_S = 501
+MIPS_INS_SAT_U = 502
+MIPS_INS_SB = 503
+MIPS_INS_SB16 = 504
+MIPS_INS_SC = 505
+MIPS_INS_SCD = 506
+MIPS_INS_SD = 507
+MIPS_INS_SDBBP = 508
+MIPS_INS_SDBBP16 = 509
+MIPS_INS_SDC1 = 510
+MIPS_INS_SDC2 = 511
+MIPS_INS_SDC3 = 512
+MIPS_INS_SDL = 513
+MIPS_INS_SDR = 514
+MIPS_INS_SDXC1 = 515
+MIPS_INS_SEB = 516
+MIPS_INS_SEH = 517
+MIPS_INS_SELEQZ = 518
+MIPS_INS_SELNEZ = 519
+MIPS_INS_SEL = 520
+MIPS_INS_SEQ = 521
+MIPS_INS_SEQI = 522
+MIPS_INS_SH = 523
+MIPS_INS_SH16 = 524
+MIPS_INS_SHF = 525
+MIPS_INS_SHILO = 526
+MIPS_INS_SHILOV = 527
+MIPS_INS_SHLLV = 528
+MIPS_INS_SHLLV_S = 529
+MIPS_INS_SHLL = 530
+MIPS_INS_SHLL_S = 531
+MIPS_INS_SHRAV = 532
+MIPS_INS_SHRAV_R = 533
+MIPS_INS_SHRA = 534
+MIPS_INS_SHRA_R = 535
+MIPS_INS_SHRLV = 536
+MIPS_INS_SHRL = 537
+MIPS_INS_SLDI = 538
+MIPS_INS_SLD = 539
+MIPS_INS_SLL = 540
+MIPS_INS_SLL16 = 541
+MIPS_INS_SLLI = 542
+MIPS_INS_SLLV = 543
+MIPS_INS_SLT = 544
+MIPS_INS_SLTI = 545
+MIPS_INS_SLTIU = 546
+MIPS_INS_SLTU = 547
+MIPS_INS_SNE = 548
+MIPS_INS_SNEI = 549
+MIPS_INS_SPLATI = 550
+MIPS_INS_SPLAT = 551
+MIPS_INS_SRA = 552
+MIPS_INS_SRAI = 553
+MIPS_INS_SRARI = 554
+MIPS_INS_SRAR = 555
+MIPS_INS_SRAV = 556
+MIPS_INS_SRL = 557
+MIPS_INS_SRL16 = 558
+MIPS_INS_SRLI = 559
+MIPS_INS_SRLRI = 560
+MIPS_INS_SRLR = 561
+MIPS_INS_SRLV = 562
+MIPS_INS_SSNOP = 563
+MIPS_INS_ST = 564
+MIPS_INS_SUBQH = 565
+MIPS_INS_SUBQH_R = 566
+MIPS_INS_SUBQ = 567
+MIPS_INS_SUBQ_S = 568
+MIPS_INS_SUBSUS_U = 569
+MIPS_INS_SUBSUU_S = 570
+MIPS_INS_SUBS_S = 571
+MIPS_INS_SUBS_U = 572
+MIPS_INS_SUBU16 = 573
+MIPS_INS_SUBUH = 574
+MIPS_INS_SUBUH_R = 575
+MIPS_INS_SUBU = 576
+MIPS_INS_SUBU_S = 577
+MIPS_INS_SUBVI = 578
+MIPS_INS_SUBV = 579
+MIPS_INS_SUXC1 = 580
+MIPS_INS_SW = 581
+MIPS_INS_SW16 = 582
+MIPS_INS_SWC1 = 583
+MIPS_INS_SWC2 = 584
+MIPS_INS_SWC3 = 585
+MIPS_INS_SWL = 586
+MIPS_INS_SWM16 = 587
+MIPS_INS_SWM32 = 588
+MIPS_INS_SWP = 589
+MIPS_INS_SWR = 590
+MIPS_INS_SWXC1 = 591
+MIPS_INS_SYNC = 592
+MIPS_INS_SYNCI = 593
+MIPS_INS_SYSCALL = 594
+MIPS_INS_TEQ = 595
+MIPS_INS_TEQI = 596
+MIPS_INS_TGE = 597
+MIPS_INS_TGEI = 598
+MIPS_INS_TGEIU = 599
+MIPS_INS_TGEU = 600
+MIPS_INS_TLBP = 601
+MIPS_INS_TLBR = 602
+MIPS_INS_TLBWI = 603
+MIPS_INS_TLBWR = 604
+MIPS_INS_TLT = 605
+MIPS_INS_TLTI = 606
+MIPS_INS_TLTIU = 607
+MIPS_INS_TLTU = 608
+MIPS_INS_TNE = 609
+MIPS_INS_TNEI = 610
+MIPS_INS_TRUNC = 611
+MIPS_INS_V3MULU = 612
+MIPS_INS_VMM0 = 613
+MIPS_INS_VMULU = 614
+MIPS_INS_VSHF = 615
+MIPS_INS_WAIT = 616
+MIPS_INS_WRDSP = 617
+MIPS_INS_WSBH = 618
+MIPS_INS_XOR = 619
+MIPS_INS_XOR16 = 620
+MIPS_INS_XORI = 621
+
+# some alias instructions
+MIPS_INS_NOP = 622
+MIPS_INS_NEGU = 623
+
+# special instructions
+MIPS_INS_JALR_HB = 624
+MIPS_INS_JR_HB = 625
+MIPS_INS_ENDING = 626
+
+MIPS_GRP_INVALID = 0
+MIPS_GRP_JUMP = 1
+MIPS_GRP_CALL = 2
+MIPS_GRP_RET = 3
+MIPS_GRP_INT = 4
+MIPS_GRP_IRET = 5
+MIPS_GRP_PRIVILEGE = 6
+MIPS_GRP_BRANCH_RELATIVE = 7
+MIPS_GRP_BITCOUNT = 128
+MIPS_GRP_DSP = 129
+MIPS_GRP_DSPR2 = 130
+MIPS_GRP_FPIDX = 131
+MIPS_GRP_MSA = 132
+MIPS_GRP_MIPS32R2 = 133
+MIPS_GRP_MIPS64 = 134
+MIPS_GRP_MIPS64R2 = 135
+MIPS_GRP_SEINREG = 136
+MIPS_GRP_STDENC = 137
+MIPS_GRP_SWAP = 138
+MIPS_GRP_MICROMIPS = 139
+MIPS_GRP_MIPS16MODE = 140
+MIPS_GRP_FP64BIT = 141
+MIPS_GRP_NONANSFPMATH = 142
+MIPS_GRP_NOTFP64BIT = 143
+MIPS_GRP_NOTINMICROMIPS = 144
+MIPS_GRP_NOTNACL = 145
+MIPS_GRP_NOTMIPS32R6 = 146
+MIPS_GRP_NOTMIPS64R6 = 147
+MIPS_GRP_CNMIPS = 148
+MIPS_GRP_MIPS32 = 149
+MIPS_GRP_MIPS32R6 = 150
+MIPS_GRP_MIPS64R6 = 151
+MIPS_GRP_MIPS2 = 152
+MIPS_GRP_MIPS3 = 153
+MIPS_GRP_MIPS3_32 = 154
+MIPS_GRP_MIPS3_32R2 = 155
+MIPS_GRP_MIPS4_32 = 156
+MIPS_GRP_MIPS4_32R2 = 157
+MIPS_GRP_MIPS5_32R2 = 158
+MIPS_GRP_GP32BIT = 159
+MIPS_GRP_GP64BIT = 160
+MIPS_GRP_ENDING = 161

.tools/python-revlibs/capstone/mos65xx.py

@@ -0,0 +1,45 @@
+# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
+
+import ctypes
+from . import copy_ctypes_list
+from .mos65xx_const import *
+
+# define the API
+class MOS65xxOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_uint16),
+        ('mem', ctypes.c_uint32),
+    )
+
+class MOS65xxOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', MOS65xxOpValue),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+
+class CsMOS65xx(ctypes.Structure):
+    _fields_ = (
+        ('am', ctypes.c_uint),
+        ('modifies_flags', ctypes.c_uint8),
+        ('op_count', ctypes.c_uint8),
+        ('operands', MOS65xxOp * 3),
+    )
+
+def get_arch_info(a):
+    return (a.am, a.modifies_flags, copy_ctypes_list(a.operands[:a.op_count]))
+
+

.tools/python-revlibs/capstone/mos65xx_const.py

@@ -0,0 +1,153 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mos65xx_const.py]
+
+MOS65XX_REG_INVALID = 0
+MOS65XX_REG_ACC = 1
+MOS65XX_REG_X = 2
+MOS65XX_REG_Y = 3
+MOS65XX_REG_P = 4
+MOS65XX_REG_SP = 5
+MOS65XX_REG_DP = 6
+MOS65XX_REG_B = 7
+MOS65XX_REG_K = 8
+MOS65XX_REG_ENDING = 9
+
+MOS65XX_AM_NONE = 0
+MOS65XX_AM_IMP = 1
+MOS65XX_AM_ACC = 2
+MOS65XX_AM_IMM = 3
+MOS65XX_AM_REL = 4
+MOS65XX_AM_INT = 5
+MOS65XX_AM_BLOCK = 6
+MOS65XX_AM_ZP = 7
+MOS65XX_AM_ZP_X = 8
+MOS65XX_AM_ZP_Y = 9
+MOS65XX_AM_ZP_REL = 10
+MOS65XX_AM_ZP_IND = 11
+MOS65XX_AM_ZP_X_IND = 12
+MOS65XX_AM_ZP_IND_Y = 13
+MOS65XX_AM_ZP_IND_LONG = 14
+MOS65XX_AM_ZP_IND_LONG_Y = 15
+MOS65XX_AM_ABS = 16
+MOS65XX_AM_ABS_X = 17
+MOS65XX_AM_ABS_Y = 18
+MOS65XX_AM_ABS_IND = 19
+MOS65XX_AM_ABS_X_IND = 20
+MOS65XX_AM_ABS_IND_LONG = 21
+MOS65XX_AM_ABS_LONG = 22
+MOS65XX_AM_ABS_LONG_X = 23
+MOS65XX_AM_SR = 24
+MOS65XX_AM_SR_IND_Y = 25
+
+MOS65XX_INS_INVALID = 0
+MOS65XX_INS_ADC = 1
+MOS65XX_INS_AND = 2
+MOS65XX_INS_ASL = 3
+MOS65XX_INS_BBR = 4
+MOS65XX_INS_BBS = 5
+MOS65XX_INS_BCC = 6
+MOS65XX_INS_BCS = 7
+MOS65XX_INS_BEQ = 8
+MOS65XX_INS_BIT = 9
+MOS65XX_INS_BMI = 10
+MOS65XX_INS_BNE = 11
+MOS65XX_INS_BPL = 12
+MOS65XX_INS_BRA = 13
+MOS65XX_INS_BRK = 14
+MOS65XX_INS_BRL = 15
+MOS65XX_INS_BVC = 16
+MOS65XX_INS_BVS = 17
+MOS65XX_INS_CLC = 18
+MOS65XX_INS_CLD = 19
+MOS65XX_INS_CLI = 20
+MOS65XX_INS_CLV = 21
+MOS65XX_INS_CMP = 22
+MOS65XX_INS_COP = 23
+MOS65XX_INS_CPX = 24
+MOS65XX_INS_CPY = 25
+MOS65XX_INS_DEC = 26
+MOS65XX_INS_DEX = 27
+MOS65XX_INS_DEY = 28
+MOS65XX_INS_EOR = 29
+MOS65XX_INS_INC = 30
+MOS65XX_INS_INX = 31
+MOS65XX_INS_INY = 32
+MOS65XX_INS_JML = 33
+MOS65XX_INS_JMP = 34
+MOS65XX_INS_JSL = 35
+MOS65XX_INS_JSR = 36
+MOS65XX_INS_LDA = 37
+MOS65XX_INS_LDX = 38
+MOS65XX_INS_LDY = 39
+MOS65XX_INS_LSR = 40
+MOS65XX_INS_MVN = 41
+MOS65XX_INS_MVP = 42
+MOS65XX_INS_NOP = 43
+MOS65XX_INS_ORA = 44
+MOS65XX_INS_PEA = 45
+MOS65XX_INS_PEI = 46
+MOS65XX_INS_PER = 47
+MOS65XX_INS_PHA = 48
+MOS65XX_INS_PHB = 49
+MOS65XX_INS_PHD = 50
+MOS65XX_INS_PHK = 51
+MOS65XX_INS_PHP = 52
+MOS65XX_INS_PHX = 53
+MOS65XX_INS_PHY = 54
+MOS65XX_INS_PLA = 55
+MOS65XX_INS_PLB = 56
+MOS65XX_INS_PLD = 57
+MOS65XX_INS_PLP = 58
+MOS65XX_INS_PLX = 59
+MOS65XX_INS_PLY = 60
+MOS65XX_INS_REP = 61
+MOS65XX_INS_RMB = 62
+MOS65XX_INS_ROL = 63
+MOS65XX_INS_ROR = 64
+MOS65XX_INS_RTI = 65
+MOS65XX_INS_RTL = 66
+MOS65XX_INS_RTS = 67
+MOS65XX_INS_SBC = 68
+MOS65XX_INS_SEC = 69
+MOS65XX_INS_SED = 70
+MOS65XX_INS_SEI = 71
+MOS65XX_INS_SEP = 72
+MOS65XX_INS_SMB = 73
+MOS65XX_INS_STA = 74
+MOS65XX_INS_STP = 75
+MOS65XX_INS_STX = 76
+MOS65XX_INS_STY = 77
+MOS65XX_INS_STZ = 78
+MOS65XX_INS_TAX = 79
+MOS65XX_INS_TAY = 80
+MOS65XX_INS_TCD = 81
+MOS65XX_INS_TCS = 82
+MOS65XX_INS_TDC = 83
+MOS65XX_INS_TRB = 84
+MOS65XX_INS_TSB = 85
+MOS65XX_INS_TSC = 86
+MOS65XX_INS_TSX = 87
+MOS65XX_INS_TXA = 88
+MOS65XX_INS_TXS = 89
+MOS65XX_INS_TXY = 90
+MOS65XX_INS_TYA = 91
+MOS65XX_INS_TYX = 92
+MOS65XX_INS_WAI = 93
+MOS65XX_INS_WDM = 94
+MOS65XX_INS_XBA = 95
+MOS65XX_INS_XCE = 96
+MOS65XX_INS_ENDING = 97
+
+MOS65XX_GRP_INVALID = 0
+MOS65XX_GRP_JUMP = 1
+MOS65XX_GRP_CALL = 2
+MOS65XX_GRP_RET = 3
+MOS65XX_GRP_INT = 4
+MOS65XX_GRP_IRET = 5
+MOS65XX_GRP_BRANCH_RELATIVE = 6
+MOS65XX_GRP_ENDING = 7
+
+MOS65XX_OP_INVALID = 0
+MOS65XX_OP_REG = 1
+MOS65XX_OP_IMM = 2
+MOS65XX_OP_MEM = 3

.tools/python-revlibs/capstone/ppc.py

@@ -0,0 +1,63 @@
+# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
+
+import ctypes
+from . import copy_ctypes_list
+from .ppc_const import *
+
+# define the API
+class PpcOpMem(ctypes.Structure):
+    _fields_ = (
+        ('base', ctypes.c_uint),
+        ('disp', ctypes.c_int32),
+    )
+
+class PpcOpCrx(ctypes.Structure):
+    _fields_ = (
+        ('scale', ctypes.c_uint),
+        ('reg', ctypes.c_uint),
+        ('cond', ctypes.c_uint),
+    )
+
+class PpcOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_int64),
+        ('mem', PpcOpMem),
+        ('crx', PpcOpCrx),
+    )
+
+class PpcOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', PpcOpValue),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+    @property
+    def crx(self):
+        return self.value.crx
+
+
+class CsPpc(ctypes.Structure):
+    _fields_ = (
+        ('bc', ctypes.c_uint),
+        ('bh', ctypes.c_uint),
+        ('update_cr0', ctypes.c_bool),
+        ('op_count', ctypes.c_uint8),
+        ('operands', PpcOp * 8),
+    )
+
+def get_arch_info(a):
+    return (a.bc, a.bh, a.update_cr0, copy_ctypes_list(a.operands[:a.op_count]))
+

.tools/python-revlibs/capstone/riscv.py

@@ -0,0 +1,49 @@
+# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
+
+import ctypes
+from . import copy_ctypes_list
+from .riscv_const import *
+
+# define the API
+class RISCVOpMem(ctypes.Structure):
+    _fields_ = (
+        ('base', ctypes.c_uint),
+        ('disp', ctypes.c_int64),
+    )
+
+class RISCVOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_int64),
+        ('mem', RISCVOpMem),
+    )
+
+class RISCVOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', RISCVOpValue),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+
+class CsRISCV(ctypes.Structure):
+    _fields_ = (
+        ('need_effective_addr', ctypes.c_bool),
+        ('op_count',            ctypes.c_uint8),
+        ('operands',            RISCVOp * 8),
+    )
+
+def get_arch_info(a):
+    return (a.need_effective_addr, copy_ctypes_list(a.operands[:a.op_count]))
+

.tools/python-revlibs/capstone/riscv_const.py

@@ -0,0 +1,456 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [riscv_const.py]
+
+# Operand type for instruction's operands
+
+RISCV_OP_INVALID = 0
+RISCV_OP_REG = 1
+RISCV_OP_IMM = 2
+RISCV_OP_MEM = 3
+
+# RISCV registers
+
+RISCV_REG_INVALID = 0
+
+# General purpose registers
+RISCV_REG_X0 = 1
+RISCV_REG_ZERO = RISCV_REG_X0
+RISCV_REG_X1 = 2
+RISCV_REG_RA = RISCV_REG_X1
+RISCV_REG_X2 = 3
+RISCV_REG_SP = RISCV_REG_X2
+RISCV_REG_X3 = 4
+RISCV_REG_GP = RISCV_REG_X3
+RISCV_REG_X4 = 5
+RISCV_REG_TP = RISCV_REG_X4
+RISCV_REG_X5 = 6
+RISCV_REG_T0 = RISCV_REG_X5
+RISCV_REG_X6 = 7
+RISCV_REG_T1 = RISCV_REG_X6
+RISCV_REG_X7 = 8
+RISCV_REG_T2 = RISCV_REG_X7
+RISCV_REG_X8 = 9
+RISCV_REG_S0 = RISCV_REG_X8
+RISCV_REG_FP = RISCV_REG_X8
+RISCV_REG_X9 = 10
+RISCV_REG_S1 = RISCV_REG_X9
+RISCV_REG_X10 = 11
+RISCV_REG_A0 = RISCV_REG_X10
+RISCV_REG_X11 = 12
+RISCV_REG_A1 = RISCV_REG_X11
+RISCV_REG_X12 = 13
+RISCV_REG_A2 = RISCV_REG_X12
+RISCV_REG_X13 = 14
+RISCV_REG_A3 = RISCV_REG_X13
+RISCV_REG_X14 = 15
+RISCV_REG_A4 = RISCV_REG_X14
+RISCV_REG_X15 = 16
+RISCV_REG_A5 = RISCV_REG_X15
+RISCV_REG_X16 = 17
+RISCV_REG_A6 = RISCV_REG_X16
+RISCV_REG_X17 = 18
+RISCV_REG_A7 = RISCV_REG_X17
+RISCV_REG_X18 = 19
+RISCV_REG_S2 = RISCV_REG_X18
+RISCV_REG_X19 = 20
+RISCV_REG_S3 = RISCV_REG_X19
+RISCV_REG_X20 = 21
+RISCV_REG_S4 = RISCV_REG_X20
+RISCV_REG_X21 = 22
+RISCV_REG_S5 = RISCV_REG_X21
+RISCV_REG_X22 = 23
+RISCV_REG_S6 = RISCV_REG_X22
+RISCV_REG_X23 = 24
+RISCV_REG_S7 = RISCV_REG_X23
+RISCV_REG_X24 = 25
+RISCV_REG_S8 = RISCV_REG_X24
+RISCV_REG_X25 = 26
+RISCV_REG_S9 = RISCV_REG_X25
+RISCV_REG_X26 = 27
+RISCV_REG_S10 = RISCV_REG_X26
+RISCV_REG_X27 = 28
+RISCV_REG_S11 = RISCV_REG_X27
+RISCV_REG_X28 = 29
+RISCV_REG_T3 = RISCV_REG_X28
+RISCV_REG_X29 = 30
+RISCV_REG_T4 = RISCV_REG_X29
+RISCV_REG_X30 = 31
+RISCV_REG_T5 = RISCV_REG_X30
+RISCV_REG_X31 = 32
+RISCV_REG_T6 = RISCV_REG_X31
+
+# Floating-point registers
+RISCV_REG_F0_32 = 33
+RISCV_REG_F0_64 = 34
+RISCV_REG_F1_32 = 35
+RISCV_REG_F1_64 = 36
+RISCV_REG_F2_32 = 37
+RISCV_REG_F2_64 = 38
+RISCV_REG_F3_32 = 39
+RISCV_REG_F3_64 = 40
+RISCV_REG_F4_32 = 41
+RISCV_REG_F4_64 = 42
+RISCV_REG_F5_32 = 43
+RISCV_REG_F5_64 = 44
+RISCV_REG_F6_32 = 45
+RISCV_REG_F6_64 = 46
+RISCV_REG_F7_32 = 47
+RISCV_REG_F7_64 = 48
+RISCV_REG_F8_32 = 49
+RISCV_REG_F8_64 = 50
+RISCV_REG_F9_32 = 51
+RISCV_REG_F9_64 = 52
+RISCV_REG_F10_32 = 53
+RISCV_REG_F10_64 = 54
+RISCV_REG_F11_32 = 55
+RISCV_REG_F11_64 = 56
+RISCV_REG_F12_32 = 57
+RISCV_REG_F12_64 = 58
+RISCV_REG_F13_32 = 59
+RISCV_REG_F13_64 = 60
+RISCV_REG_F14_32 = 61
+RISCV_REG_F14_64 = 62
+RISCV_REG_F15_32 = 63
+RISCV_REG_F15_64 = 64
+RISCV_REG_F16_32 = 65
+RISCV_REG_F16_64 = 66
+RISCV_REG_F17_32 = 67
+RISCV_REG_F17_64 = 68
+RISCV_REG_F18_32 = 69
+RISCV_REG_F18_64 = 70
+RISCV_REG_F19_32 = 71
+RISCV_REG_F19_64 = 72
+RISCV_REG_F20_32 = 73
+RISCV_REG_F20_64 = 74
+RISCV_REG_F21_32 = 75
+RISCV_REG_F21_64 = 76
+RISCV_REG_F22_32 = 77
+RISCV_REG_F22_64 = 78
+RISCV_REG_F23_32 = 79
+RISCV_REG_F23_64 = 80
+RISCV_REG_F24_32 = 81
+RISCV_REG_F24_64 = 82
+RISCV_REG_F25_32 = 83
+RISCV_REG_F25_64 = 84
+RISCV_REG_F26_32 = 85
+RISCV_REG_F26_64 = 86
+RISCV_REG_F27_32 = 87
+RISCV_REG_F27_64 = 88
+RISCV_REG_F28_32 = 89
+RISCV_REG_F28_64 = 90
+RISCV_REG_F29_32 = 91
+RISCV_REG_F29_64 = 92
+RISCV_REG_F30_32 = 93
+RISCV_REG_F30_64 = 94
+RISCV_REG_F31_32 = 95
+RISCV_REG_F31_64 = 96
+RISCV_REG_ENDING = 97
+
+# RISCV instruction
+
+RISCV_INS_INVALID = 0
+RISCV_INS_ADD = 1
+RISCV_INS_ADDI = 2
+RISCV_INS_ADDIW = 3
+RISCV_INS_ADDW = 4
+RISCV_INS_AMOADD_D = 5
+RISCV_INS_AMOADD_D_AQ = 6
+RISCV_INS_AMOADD_D_AQ_RL = 7
+RISCV_INS_AMOADD_D_RL = 8
+RISCV_INS_AMOADD_W = 9
+RISCV_INS_AMOADD_W_AQ = 10
+RISCV_INS_AMOADD_W_AQ_RL = 11
+RISCV_INS_AMOADD_W_RL = 12
+RISCV_INS_AMOAND_D = 13
+RISCV_INS_AMOAND_D_AQ = 14
+RISCV_INS_AMOAND_D_AQ_RL = 15
+RISCV_INS_AMOAND_D_RL = 16
+RISCV_INS_AMOAND_W = 17
+RISCV_INS_AMOAND_W_AQ = 18
+RISCV_INS_AMOAND_W_AQ_RL = 19
+RISCV_INS_AMOAND_W_RL = 20
+RISCV_INS_AMOMAXU_D = 21
+RISCV_INS_AMOMAXU_D_AQ = 22
+RISCV_INS_AMOMAXU_D_AQ_RL = 23
+RISCV_INS_AMOMAXU_D_RL = 24
+RISCV_INS_AMOMAXU_W = 25
+RISCV_INS_AMOMAXU_W_AQ = 26
+RISCV_INS_AMOMAXU_W_AQ_RL = 27
+RISCV_INS_AMOMAXU_W_RL = 28
+RISCV_INS_AMOMAX_D = 29
+RISCV_INS_AMOMAX_D_AQ = 30
+RISCV_INS_AMOMAX_D_AQ_RL = 31
+RISCV_INS_AMOMAX_D_RL = 32
+RISCV_INS_AMOMAX_W = 33
+RISCV_INS_AMOMAX_W_AQ = 34
+RISCV_INS_AMOMAX_W_AQ_RL = 35
+RISCV_INS_AMOMAX_W_RL = 36
+RISCV_INS_AMOMINU_D = 37
+RISCV_INS_AMOMINU_D_AQ = 38
+RISCV_INS_AMOMINU_D_AQ_RL = 39
+RISCV_INS_AMOMINU_D_RL = 40
+RISCV_INS_AMOMINU_W = 41
+RISCV_INS_AMOMINU_W_AQ = 42
+RISCV_INS_AMOMINU_W_AQ_RL = 43
+RISCV_INS_AMOMINU_W_RL = 44
+RISCV_INS_AMOMIN_D = 45
+RISCV_INS_AMOMIN_D_AQ = 46
+RISCV_INS_AMOMIN_D_AQ_RL = 47
+RISCV_INS_AMOMIN_D_RL = 48
+RISCV_INS_AMOMIN_W = 49
+RISCV_INS_AMOMIN_W_AQ = 50
+RISCV_INS_AMOMIN_W_AQ_RL = 51
+RISCV_INS_AMOMIN_W_RL = 52
+RISCV_INS_AMOOR_D = 53
+RISCV_INS_AMOOR_D_AQ = 54
+RISCV_INS_AMOOR_D_AQ_RL = 55
+RISCV_INS_AMOOR_D_RL = 56
+RISCV_INS_AMOOR_W = 57
+RISCV_INS_AMOOR_W_AQ = 58
+RISCV_INS_AMOOR_W_AQ_RL = 59
+RISCV_INS_AMOOR_W_RL = 60
+RISCV_INS_AMOSWAP_D = 61
+RISCV_INS_AMOSWAP_D_AQ = 62
+RISCV_INS_AMOSWAP_D_AQ_RL = 63
+RISCV_INS_AMOSWAP_D_RL = 64
+RISCV_INS_AMOSWAP_W = 65
+RISCV_INS_AMOSWAP_W_AQ = 66
+RISCV_INS_AMOSWAP_W_AQ_RL = 67
+RISCV_INS_AMOSWAP_W_RL = 68
+RISCV_INS_AMOXOR_D = 69
+RISCV_INS_AMOXOR_D_AQ = 70
+RISCV_INS_AMOXOR_D_AQ_RL = 71
+RISCV_INS_AMOXOR_D_RL = 72
+RISCV_INS_AMOXOR_W = 73
+RISCV_INS_AMOXOR_W_AQ = 74
+RISCV_INS_AMOXOR_W_AQ_RL = 75
+RISCV_INS_AMOXOR_W_RL = 76
+RISCV_INS_AND = 77
+RISCV_INS_ANDI = 78
+RISCV_INS_AUIPC = 79
+RISCV_INS_BEQ = 80
+RISCV_INS_BGE = 81
+RISCV_INS_BGEU = 82
+RISCV_INS_BLT = 83
+RISCV_INS_BLTU = 84
+RISCV_INS_BNE = 85
+RISCV_INS_CSRRC = 86
+RISCV_INS_CSRRCI = 87
+RISCV_INS_CSRRS = 88
+RISCV_INS_CSRRSI = 89
+RISCV_INS_CSRRW = 90
+RISCV_INS_CSRRWI = 91
+RISCV_INS_C_ADD = 92
+RISCV_INS_C_ADDI = 93
+RISCV_INS_C_ADDI16SP = 94
+RISCV_INS_C_ADDI4SPN = 95
+RISCV_INS_C_ADDIW = 96
+RISCV_INS_C_ADDW = 97
+RISCV_INS_C_AND = 98
+RISCV_INS_C_ANDI = 99
+RISCV_INS_C_BEQZ = 100
+RISCV_INS_C_BNEZ = 101
+RISCV_INS_C_EBREAK = 102
+RISCV_INS_C_FLD = 103
+RISCV_INS_C_FLDSP = 104
+RISCV_INS_C_FLW = 105
+RISCV_INS_C_FLWSP = 106
+RISCV_INS_C_FSD = 107
+RISCV_INS_C_FSDSP = 108
+RISCV_INS_C_FSW = 109
+RISCV_INS_C_FSWSP = 110
+RISCV_INS_C_J = 111
+RISCV_INS_C_JAL = 112
+RISCV_INS_C_JALR = 113
+RISCV_INS_C_JR = 114
+RISCV_INS_C_LD = 115
+RISCV_INS_C_LDSP = 116
+RISCV_INS_C_LI = 117
+RISCV_INS_C_LUI = 118
+RISCV_INS_C_LW = 119
+RISCV_INS_C_LWSP = 120
+RISCV_INS_C_MV = 121
+RISCV_INS_C_NOP = 122
+RISCV_INS_C_OR = 123
+RISCV_INS_C_SD = 124
+RISCV_INS_C_SDSP = 125
+RISCV_INS_C_SLLI = 126
+RISCV_INS_C_SRAI = 127
+RISCV_INS_C_SRLI = 128
+RISCV_INS_C_SUB = 129
+RISCV_INS_C_SUBW = 130
+RISCV_INS_C_SW = 131
+RISCV_INS_C_SWSP = 132
+RISCV_INS_C_UNIMP = 133
+RISCV_INS_C_XOR = 134
+RISCV_INS_DIV = 135
+RISCV_INS_DIVU = 136
+RISCV_INS_DIVUW = 137
+RISCV_INS_DIVW = 138
+RISCV_INS_EBREAK = 139
+RISCV_INS_ECALL = 140
+RISCV_INS_FADD_D = 141
+RISCV_INS_FADD_S = 142
+RISCV_INS_FCLASS_D = 143
+RISCV_INS_FCLASS_S = 144
+RISCV_INS_FCVT_D_L = 145
+RISCV_INS_FCVT_D_LU = 146
+RISCV_INS_FCVT_D_S = 147
+RISCV_INS_FCVT_D_W = 148
+RISCV_INS_FCVT_D_WU = 149
+RISCV_INS_FCVT_LU_D = 150
+RISCV_INS_FCVT_LU_S = 151
+RISCV_INS_FCVT_L_D = 152
+RISCV_INS_FCVT_L_S = 153
+RISCV_INS_FCVT_S_D = 154
+RISCV_INS_FCVT_S_L = 155
+RISCV_INS_FCVT_S_LU = 156
+RISCV_INS_FCVT_S_W = 157
+RISCV_INS_FCVT_S_WU = 158
+RISCV_INS_FCVT_WU_D = 159
+RISCV_INS_FCVT_WU_S = 160
+RISCV_INS_FCVT_W_D = 161
+RISCV_INS_FCVT_W_S = 162
+RISCV_INS_FDIV_D = 163
+RISCV_INS_FDIV_S = 164
+RISCV_INS_FENCE = 165
+RISCV_INS_FENCE_I = 166
+RISCV_INS_FENCE_TSO = 167
+RISCV_INS_FEQ_D = 168
+RISCV_INS_FEQ_S = 169
+RISCV_INS_FLD = 170
+RISCV_INS_FLE_D = 171
+RISCV_INS_FLE_S = 172
+RISCV_INS_FLT_D = 173
+RISCV_INS_FLT_S = 174
+RISCV_INS_FLW = 175
+RISCV_INS_FMADD_D = 176
+RISCV_INS_FMADD_S = 177
+RISCV_INS_FMAX_D = 178
+RISCV_INS_FMAX_S = 179
+RISCV_INS_FMIN_D = 180
+RISCV_INS_FMIN_S = 181
+RISCV_INS_FMSUB_D = 182
+RISCV_INS_FMSUB_S = 183
+RISCV_INS_FMUL_D = 184
+RISCV_INS_FMUL_S = 185
+RISCV_INS_FMV_D_X = 186
+RISCV_INS_FMV_W_X = 187
+RISCV_INS_FMV_X_D = 188
+RISCV_INS_FMV_X_W = 189
+RISCV_INS_FNMADD_D = 190
+RISCV_INS_FNMADD_S = 191
+RISCV_INS_FNMSUB_D = 192
+RISCV_INS_FNMSUB_S = 193
+RISCV_INS_FSD = 194
+RISCV_INS_FSGNJN_D = 195
+RISCV_INS_FSGNJN_S = 196
+RISCV_INS_FSGNJX_D = 197
+RISCV_INS_FSGNJX_S = 198
+RISCV_INS_FSGNJ_D = 199
+RISCV_INS_FSGNJ_S = 200
+RISCV_INS_FSQRT_D = 201
+RISCV_INS_FSQRT_S = 202
+RISCV_INS_FSUB_D = 203
+RISCV_INS_FSUB_S = 204
+RISCV_INS_FSW = 205
+RISCV_INS_JAL = 206
+RISCV_INS_JALR = 207
+RISCV_INS_LB = 208
+RISCV_INS_LBU = 209
+RISCV_INS_LD = 210
+RISCV_INS_LH = 211
+RISCV_INS_LHU = 212
+RISCV_INS_LR_D = 213
+RISCV_INS_LR_D_AQ = 214
+RISCV_INS_LR_D_AQ_RL = 215
+RISCV_INS_LR_D_RL = 216
+RISCV_INS_LR_W = 217
+RISCV_INS_LR_W_AQ = 218
+RISCV_INS_LR_W_AQ_RL = 219
+RISCV_INS_LR_W_RL = 220
+RISCV_INS_LUI = 221
+RISCV_INS_LW = 222
+RISCV_INS_LWU = 223
+RISCV_INS_MRET = 224
+RISCV_INS_MUL = 225
+RISCV_INS_MULH = 226
+RISCV_INS_MULHSU = 227
+RISCV_INS_MULHU = 228
+RISCV_INS_MULW = 229
+RISCV_INS_OR = 230
+RISCV_INS_ORI = 231
+RISCV_INS_REM = 232
+RISCV_INS_REMU = 233
+RISCV_INS_REMUW = 234
+RISCV_INS_REMW = 235
+RISCV_INS_SB = 236
+RISCV_INS_SC_D = 237
+RISCV_INS_SC_D_AQ = 238
+RISCV_INS_SC_D_AQ_RL = 239
+RISCV_INS_SC_D_RL = 240
+RISCV_INS_SC_W = 241
+RISCV_INS_SC_W_AQ = 242
+RISCV_INS_SC_W_AQ_RL = 243
+RISCV_INS_SC_W_RL = 244
+RISCV_INS_SD = 245
+RISCV_INS_SFENCE_VMA = 246
+RISCV_INS_SH = 247
+RISCV_INS_SLL = 248
+RISCV_INS_SLLI = 249
+RISCV_INS_SLLIW = 250
+RISCV_INS_SLLW = 251
+RISCV_INS_SLT = 252
+RISCV_INS_SLTI = 253
+RISCV_INS_SLTIU = 254
+RISCV_INS_SLTU = 255
+RISCV_INS_SRA = 256
+RISCV_INS_SRAI = 257
+RISCV_INS_SRAIW = 258
+RISCV_INS_SRAW = 259
+RISCV_INS_SRET = 260
+RISCV_INS_SRL = 261
+RISCV_INS_SRLI = 262
+RISCV_INS_SRLIW = 263
+RISCV_INS_SRLW = 264
+RISCV_INS_SUB = 265
+RISCV_INS_SUBW = 266
+RISCV_INS_SW = 267
+RISCV_INS_UNIMP = 268
+RISCV_INS_URET = 269
+RISCV_INS_WFI = 270
+RISCV_INS_XOR = 271
+RISCV_INS_XORI = 272
+RISCV_INS_ENDING = 273
+
+# Group of RISCV instructions
+
+RISCV_GRP_INVALID = 0
+RISCV_GRP_JUMP = 1
+RISCV_GRP_CALL = 2
+RISCV_GRP_RET = 3
+RISCV_GRP_INT = 4
+RISCV_GRP_IRET = 5
+RISCV_GRP_PRIVILEGE = 6
+RISCV_GRP_BRANCH_RELATIVE = 7
+RISCV_GRP_ISRV32 = 128
+RISCV_GRP_ISRV64 = 129
+RISCV_GRP_HASSTDEXTA = 130
+RISCV_GRP_HASSTDEXTC = 131
+RISCV_GRP_HASSTDEXTD = 132
+RISCV_GRP_HASSTDEXTF = 133
+RISCV_GRP_HASSTDEXTM = 134
+RISCV_GRP_ISRVA = 135
+RISCV_GRP_ISRVC = 136
+RISCV_GRP_ISRVD = 137
+RISCV_GRP_ISRVCD = 138
+RISCV_GRP_ISRVF = 139
+RISCV_GRP_ISRV32C = 140
+RISCV_GRP_ISRV32CF = 141
+RISCV_GRP_ISRVM = 142
+RISCV_GRP_ISRV64A = 143
+RISCV_GRP_ISRV64C = 144
+RISCV_GRP_ISRV64D = 145
+RISCV_GRP_ISRV64F = 146
+RISCV_GRP_ISRV64M = 147
+RISCV_GRP_ENDING = 148

.tools/python-revlibs/capstone/sh.py

@@ -0,0 +1,66 @@
+# Capstone Python bindings, by Peace-Maker <peacemakerctf@gmail.com>
+
+import ctypes
+from . import copy_ctypes_list
+from .sh_const import *
+
+# define the API
+class SHOpMem(ctypes.Structure):
+    _fields_ = (
+        ('address', ctypes.c_uint),
+        ('reg', ctypes.c_uint),
+        ('disp', ctypes.c_uint32),
+    )
+
+class SHOpDsp(ctypes.Structure):
+    _fields_ = (
+        ('insn', ctypes.c_uint),
+        ('operand', ctypes.c_uint * 2),
+        ('r', ctypes.c_uint * 6),
+        ('cc', ctypes.c_uint),
+        ('imm', ctypes.c_uint8),
+        ('size', ctypes.c_int),
+    )
+
+class SHOpValue(ctypes.Union):
+    _fields_ = (
+        ('imm', ctypes.c_int64),
+        ('reg', ctypes.c_uint),
+        ('mem', SHOpMem),
+        ('dsp', SHOpDsp),
+    )
+
+class SHOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', SHOpValue),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def mem(self):
+        return self.value.mem
+    
+    @property
+    def dsp(self):
+        return self.value.dsp
+
+
+class CsSH(ctypes.Structure):
+    _fields_ = (
+        ('insn', ctypes.c_uint),
+        ('size', ctypes.c_uint8),
+        ('op_count', ctypes.c_uint8),
+        ('operands', SHOp * 3),
+    )
+
+def get_arch_info(a):
+    return (a.insn, a.size, copy_ctypes_list(a.operands[:a.op_count]))
+

.tools/python-revlibs/capstone/sh_const.py

@@ -0,0 +1,367 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sh_const.py]
+
+SH_REG_INVALID = 0
+SH_REG_R0 = 1
+SH_REG_R1 = 2
+SH_REG_R2 = 3
+SH_REG_R3 = 4
+SH_REG_R4 = 5
+SH_REG_R5 = 6
+SH_REG_R6 = 7
+SH_REG_R7 = 8
+SH_REG_R8 = 9
+SH_REG_R9 = 10
+SH_REG_R10 = 11
+SH_REG_R11 = 12
+SH_REG_R12 = 13
+SH_REG_R13 = 14
+SH_REG_R14 = 15
+SH_REG_R15 = 16
+SH_REG_R0_BANK = 17
+SH_REG_R1_BANK = 18
+SH_REG_R2_BANK = 19
+SH_REG_R3_BANK = 20
+SH_REG_R4_BANK = 21
+SH_REG_R5_BANK = 22
+SH_REG_R6_BANK = 23
+SH_REG_R7_BANK = 24
+SH_REG_FR0 = 25
+SH_REG_FR1 = 26
+SH_REG_FR2 = 27
+SH_REG_FR3 = 28
+SH_REG_FR4 = 29
+SH_REG_FR5 = 30
+SH_REG_FR6 = 31
+SH_REG_FR7 = 32
+SH_REG_FR8 = 33
+SH_REG_FR9 = 34
+SH_REG_FR10 = 35
+SH_REG_FR11 = 36
+SH_REG_FR12 = 37
+SH_REG_FR13 = 38
+SH_REG_FR14 = 39
+SH_REG_FR15 = 40
+SH_REG_DR0 = 41
+SH_REG_DR2 = 42
+SH_REG_DR4 = 43
+SH_REG_DR6 = 44
+SH_REG_DR8 = 45
+SH_REG_DR10 = 46
+SH_REG_DR12 = 47
+SH_REG_DR14 = 48
+SH_REG_XD0 = 49
+SH_REG_XD2 = 50
+SH_REG_XD4 = 51
+SH_REG_XD6 = 52
+SH_REG_XD8 = 53
+SH_REG_XD10 = 54
+SH_REG_XD12 = 55
+SH_REG_XD14 = 56
+SH_REG_XF0 = 57
+SH_REG_XF1 = 58
+SH_REG_XF2 = 59
+SH_REG_XF3 = 60
+SH_REG_XF4 = 61
+SH_REG_XF5 = 62
+SH_REG_XF6 = 63
+SH_REG_XF7 = 64
+SH_REG_XF8 = 65
+SH_REG_XF9 = 66
+SH_REG_XF10 = 67
+SH_REG_XF11 = 68
+SH_REG_XF12 = 69
+SH_REG_XF13 = 70
+SH_REG_XF14 = 71
+SH_REG_XF15 = 72
+SH_REG_FV0 = 73
+SH_REG_FV4 = 74
+SH_REG_FV8 = 75
+SH_REG_FV12 = 76
+SH_REG_XMATRX = 77
+SH_REG_PC = 78
+SH_REG_PR = 79
+SH_REG_MACH = 80
+SH_REG_MACL = 81
+SH_REG_SR = 82
+SH_REG_GBR = 83
+SH_REG_SSR = 84
+SH_REG_SPC = 85
+SH_REG_SGR = 86
+SH_REG_DBR = 87
+SH_REG_VBR = 88
+SH_REG_TBR = 89
+SH_REG_RS = 90
+SH_REG_RE = 91
+SH_REG_MOD = 92
+SH_REG_FPUL = 93
+SH_REG_FPSCR = 94
+SH_REG_DSP_X0 = 95
+SH_REG_DSP_X1 = 96
+SH_REG_DSP_Y0 = 97
+SH_REG_DSP_Y1 = 98
+SH_REG_DSP_A0 = 99
+SH_REG_DSP_A1 = 100
+SH_REG_DSP_A0G = 101
+SH_REG_DSP_A1G = 102
+SH_REG_DSP_M0 = 103
+SH_REG_DSP_M1 = 104
+SH_REG_DSP_DSR = 105
+SH_REG_DSP_RSV0 = 106
+SH_REG_DSP_RSV1 = 107
+SH_REG_DSP_RSV2 = 108
+SH_REG_DSP_RSV3 = 109
+SH_REG_DSP_RSV4 = 110
+SH_REG_DSP_RSV5 = 111
+SH_REG_DSP_RSV6 = 112
+SH_REG_DSP_RSV7 = 113
+SH_REG_DSP_RSV8 = 114
+SH_REG_DSP_RSV9 = 115
+SH_REG_DSP_RSVA = 116
+SH_REG_DSP_RSVB = 117
+SH_REG_DSP_RSVC = 118
+SH_REG_DSP_RSVD = 119
+SH_REG_DSP_RSVE = 120
+SH_REG_DSP_RSVF = 121
+SH_REG_ENDING = 122
+
+SH_OP_INVALID = 0
+SH_OP_REG = 1
+SH_OP_IMM = 2
+SH_OP_MEM = 3
+
+SH_OP_MEM_INVALID = 0
+SH_OP_MEM_REG_IND = 1
+SH_OP_MEM_REG_POST = 2
+SH_OP_MEM_REG_PRE = 3
+SH_OP_MEM_REG_DISP = 4
+SH_OP_MEM_REG_R0 = 5
+SH_OP_MEM_GBR_DISP = 6
+SH_OP_MEM_GBR_R0 = 7
+SH_OP_MEM_PCR = 8
+SH_OP_MEM_TBR_DISP = 9
+SH_INS_DSP_INVALID = 10
+SH_INS_DSP_DOUBLE = 11
+SH_INS_DSP_SINGLE = 12
+SH_INS_DSP_PARALLEL = 13
+SH_INS_DSP_NOP = 1
+SH_INS_DSP_MOV = 2
+SH_INS_DSP_PSHL = 3
+SH_INS_DSP_PSHA = 4
+SH_INS_DSP_PMULS = 5
+SH_INS_DSP_PCLR_PMULS = 6
+SH_INS_DSP_PSUB_PMULS = 7
+SH_INS_DSP_PADD_PMULS = 8
+SH_INS_DSP_PSUBC = 9
+SH_INS_DSP_PADDC = 10
+SH_INS_DSP_PCMP = 11
+SH_INS_DSP_PABS = 12
+SH_INS_DSP_PRND = 13
+SH_INS_DSP_PSUB = 14
+SH_INS_DSP_PSUBr = 15
+SH_INS_DSP_PADD = 16
+SH_INS_DSP_PAND = 17
+SH_INS_DSP_PXOR = 18
+SH_INS_DSP_POR = 19
+SH_INS_DSP_PDEC = 20
+SH_INS_DSP_PINC = 21
+SH_INS_DSP_PCLR = 22
+SH_INS_DSP_PDMSB = 23
+SH_INS_DSP_PNEG = 24
+SH_INS_DSP_PCOPY = 25
+SH_INS_DSP_PSTS = 26
+SH_INS_DSP_PLDS = 27
+SH_INS_DSP_PSWAP = 28
+SH_INS_DSP_PWAD = 29
+SH_INS_DSP_PWSB = 30
+SH_OP_DSP_INVALID = 31
+SH_OP_DSP_REG_PRE = 32
+SH_OP_DSP_REG_IND = 33
+SH_OP_DSP_REG_POST = 34
+SH_OP_DSP_REG_INDEX = 35
+SH_OP_DSP_REG = 36
+SH_OP_DSP_IMM = 37
+SH_DSP_CC_INVALID = 38
+SH_DSP_CC_NONE = 39
+SH_DSP_CC_DCT = 40
+SH_DSP_CC_DCF = 41
+SH_INS_INVALID = 42
+SH_INS_ADD_r = 43
+SH_INS_ADD = 44
+SH_INS_ADDC = 45
+SH_INS_ADDV = 46
+SH_INS_AND = 47
+SH_INS_BAND = 48
+SH_INS_BANDNOT = 49
+SH_INS_BCLR = 50
+SH_INS_BF = 51
+SH_INS_BF_S = 52
+SH_INS_BLD = 53
+SH_INS_BLDNOT = 54
+SH_INS_BOR = 55
+SH_INS_BORNOT = 56
+SH_INS_BRA = 57
+SH_INS_BRAF = 58
+SH_INS_BSET = 59
+SH_INS_BSR = 60
+SH_INS_BSRF = 61
+SH_INS_BST = 62
+SH_INS_BT = 63
+SH_INS_BT_S = 64
+SH_INS_BXOR = 65
+SH_INS_CLIPS = 66
+SH_INS_CLIPU = 67
+SH_INS_CLRDMXY = 68
+SH_INS_CLRMAC = 69
+SH_INS_CLRS = 70
+SH_INS_CLRT = 71
+SH_INS_CMP_EQ = 72
+SH_INS_CMP_GE = 73
+SH_INS_CMP_GT = 74
+SH_INS_CMP_HI = 75
+SH_INS_CMP_HS = 76
+SH_INS_CMP_PL = 77
+SH_INS_CMP_PZ = 78
+SH_INS_CMP_STR = 79
+SH_INS_DIV0S = 80
+SH_INS_DIV0U = 81
+SH_INS_DIV1 = 82
+SH_INS_DIVS = 83
+SH_INS_DIVU = 84
+SH_INS_DMULS_L = 85
+SH_INS_DMULU_L = 86
+SH_INS_DT = 87
+SH_INS_EXTS_B = 88
+SH_INS_EXTS_W = 89
+SH_INS_EXTU_B = 90
+SH_INS_EXTU_W = 91
+SH_INS_FABS = 92
+SH_INS_FADD = 93
+SH_INS_FCMP_EQ = 94
+SH_INS_FCMP_GT = 95
+SH_INS_FCNVDS = 96
+SH_INS_FCNVSD = 97
+SH_INS_FDIV = 98
+SH_INS_FIPR = 99
+SH_INS_FLDI0 = 100
+SH_INS_FLDI1 = 101
+SH_INS_FLDS = 102
+SH_INS_FLOAT = 103
+SH_INS_FMAC = 104
+SH_INS_FMOV = 105
+SH_INS_FMUL = 106
+SH_INS_FNEG = 107
+SH_INS_FPCHG = 108
+SH_INS_FRCHG = 109
+SH_INS_FSCA = 110
+SH_INS_FSCHG = 111
+SH_INS_FSQRT = 112
+SH_INS_FSRRA = 113
+SH_INS_FSTS = 114
+SH_INS_FSUB = 115
+SH_INS_FTRC = 116
+SH_INS_FTRV = 117
+SH_INS_ICBI = 118
+SH_INS_JMP = 119
+SH_INS_JSR = 120
+SH_INS_JSR_N = 121
+SH_INS_LDBANK = 122
+SH_INS_LDC = 123
+SH_INS_LDRC = 124
+SH_INS_LDRE = 125
+SH_INS_LDRS = 126
+SH_INS_LDS = 127
+SH_INS_LDTLB = 128
+SH_INS_MAC_L = 129
+SH_INS_MAC_W = 130
+SH_INS_MOV = 131
+SH_INS_MOVA = 132
+SH_INS_MOVCA = 133
+SH_INS_MOVCO = 134
+SH_INS_MOVI20 = 135
+SH_INS_MOVI20S = 136
+SH_INS_MOVLI = 137
+SH_INS_MOVML = 138
+SH_INS_MOVMU = 139
+SH_INS_MOVRT = 140
+SH_INS_MOVT = 141
+SH_INS_MOVU = 142
+SH_INS_MOVUA = 143
+SH_INS_MUL_L = 144
+SH_INS_MULR = 145
+SH_INS_MULS_W = 146
+SH_INS_MULU_W = 147
+SH_INS_NEG = 148
+SH_INS_NEGC = 149
+SH_INS_NOP = 150
+SH_INS_NOT = 151
+SH_INS_NOTT = 152
+SH_INS_OCBI = 153
+SH_INS_OCBP = 154
+SH_INS_OCBWB = 155
+SH_INS_OR = 156
+SH_INS_PREF = 157
+SH_INS_PREFI = 158
+SH_INS_RESBANK = 159
+SH_INS_ROTCL = 160
+SH_INS_ROTCR = 161
+SH_INS_ROTL = 162
+SH_INS_ROTR = 163
+SH_INS_RTE = 164
+SH_INS_RTS = 165
+SH_INS_RTS_N = 166
+SH_INS_RTV_N = 167
+SH_INS_SETDMX = 168
+SH_INS_SETDMY = 169
+SH_INS_SETRC = 170
+SH_INS_SETS = 171
+SH_INS_SETT = 172
+SH_INS_SHAD = 173
+SH_INS_SHAL = 174
+SH_INS_SHAR = 175
+SH_INS_SHLD = 176
+SH_INS_SHLL = 177
+SH_INS_SHLL16 = 178
+SH_INS_SHLL2 = 179
+SH_INS_SHLL8 = 180
+SH_INS_SHLR = 181
+SH_INS_SHLR16 = 182
+SH_INS_SHLR2 = 183
+SH_INS_SHLR8 = 184
+SH_INS_SLEEP = 185
+SH_INS_STBANK = 186
+SH_INS_STC = 187
+SH_INS_STS = 188
+SH_INS_SUB = 189
+SH_INS_SUBC = 190
+SH_INS_SUBV = 191
+SH_INS_SWAP_B = 192
+SH_INS_SWAP_W = 193
+SH_INS_SYNCO = 194
+SH_INS_TAS = 195
+SH_INS_TRAPA = 196
+SH_INS_TST = 197
+SH_INS_XOR = 198
+SH_INS_XTRCT = 199
+SH_INS_DSP = 200
+SH_INS_ENDING = 201
+
+SH_GRP_INVALID = 0
+SH_GRP_JUMP = 1
+SH_GRP_CALL = 2
+SH_GRP_INT = 3
+SH_GRP_RET = 4
+SH_GRP_IRET = 5
+SH_GRP_PRIVILEGE = 6
+SH_GRP_BRANCH_RELATIVE = 7
+SH_GRP_SH1 = 8
+SH_GRP_SH2 = 9
+SH_GRP_SH2E = 10
+SH_GRP_SH2DSP = 11
+SH_GRP_SH2A = 12
+SH_GRP_SH2AFPU = 13
+SH_GRP_SH3 = 14
+SH_GRP_SH3DSP = 15
+SH_GRP_SH4 = 16
+SH_GRP_SH4A = 17
+SH_GRP_ENDING = 18

.tools/python-revlibs/capstone/sparc.py

@@ -0,0 +1,51 @@
+# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
+
+import ctypes
+from . import copy_ctypes_list
+from .sparc_const import *
+
+# define the API
+class SparcOpMem(ctypes.Structure):
+    _fields_ = (
+        ('base', ctypes.c_uint8),
+        ('index', ctypes.c_uint8),
+        ('disp', ctypes.c_int32),
+    )
+
+class SparcOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_int64),
+        ('mem', SparcOpMem),
+    )
+
+class SparcOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', SparcOpValue),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+
+class CsSparc(ctypes.Structure):
+    _fields_ = (
+        ('cc', ctypes.c_uint),
+        ('hint', ctypes.c_uint),
+        ('op_count', ctypes.c_uint8),
+        ('operands', SparcOp * 4),
+    )
+
+def get_arch_info(a):
+    return (a.cc, a.hint, copy_ctypes_list(a.operands[:a.op_count]))
+

.tools/python-revlibs/capstone/sparc_const.py

@@ -0,0 +1,430 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [sparc_const.py]
+
+SPARC_CC_INVALID = 0
+SPARC_CC_ICC_A = 8+256
+SPARC_CC_ICC_N = 0+256
+SPARC_CC_ICC_NE = 9+256
+SPARC_CC_ICC_E = 1+256
+SPARC_CC_ICC_G = 10+256
+SPARC_CC_ICC_LE = 2+256
+SPARC_CC_ICC_GE = 11+256
+SPARC_CC_ICC_L = 3+256
+SPARC_CC_ICC_GU = 12+256
+SPARC_CC_ICC_LEU = 4+256
+SPARC_CC_ICC_CC = 13+256
+SPARC_CC_ICC_CS = 5+256
+SPARC_CC_ICC_POS = 14+256
+SPARC_CC_ICC_NEG = 6+256
+SPARC_CC_ICC_VC = 15+256
+SPARC_CC_ICC_VS = 7+256
+SPARC_CC_FCC_A = 8+16+256
+SPARC_CC_FCC_N = 0+16+256
+SPARC_CC_FCC_U = 7+16+256
+SPARC_CC_FCC_G = 6+16+256
+SPARC_CC_FCC_UG = 5+16+256
+SPARC_CC_FCC_L = 4+16+256
+SPARC_CC_FCC_UL = 3+16+256
+SPARC_CC_FCC_LG = 2+16+256
+SPARC_CC_FCC_NE = 1+16+256
+SPARC_CC_FCC_E = 9+16+256
+SPARC_CC_FCC_UE = 10+16+256
+SPARC_CC_FCC_GE = 11+16+256
+SPARC_CC_FCC_UGE = 12+16+256
+SPARC_CC_FCC_LE = 13+16+256
+SPARC_CC_FCC_ULE = 14+16+256
+SPARC_CC_FCC_O = 15+16+256
+
+SPARC_HINT_INVALID = 0
+SPARC_HINT_A = 1<<0
+SPARC_HINT_PT = 1<<1
+SPARC_HINT_PN = 1<<2
+
+SPARC_OP_INVALID = 0
+SPARC_OP_REG = 1
+SPARC_OP_IMM = 2
+SPARC_OP_MEM = 3
+
+SPARC_REG_INVALID = 0
+SPARC_REG_F0 = 1
+SPARC_REG_F1 = 2
+SPARC_REG_F2 = 3
+SPARC_REG_F3 = 4
+SPARC_REG_F4 = 5
+SPARC_REG_F5 = 6
+SPARC_REG_F6 = 7
+SPARC_REG_F7 = 8
+SPARC_REG_F8 = 9
+SPARC_REG_F9 = 10
+SPARC_REG_F10 = 11
+SPARC_REG_F11 = 12
+SPARC_REG_F12 = 13
+SPARC_REG_F13 = 14
+SPARC_REG_F14 = 15
+SPARC_REG_F15 = 16
+SPARC_REG_F16 = 17
+SPARC_REG_F17 = 18
+SPARC_REG_F18 = 19
+SPARC_REG_F19 = 20
+SPARC_REG_F20 = 21
+SPARC_REG_F21 = 22
+SPARC_REG_F22 = 23
+SPARC_REG_F23 = 24
+SPARC_REG_F24 = 25
+SPARC_REG_F25 = 26
+SPARC_REG_F26 = 27
+SPARC_REG_F27 = 28
+SPARC_REG_F28 = 29
+SPARC_REG_F29 = 30
+SPARC_REG_F30 = 31
+SPARC_REG_F31 = 32
+SPARC_REG_F32 = 33
+SPARC_REG_F34 = 34
+SPARC_REG_F36 = 35
+SPARC_REG_F38 = 36
+SPARC_REG_F40 = 37
+SPARC_REG_F42 = 38
+SPARC_REG_F44 = 39
+SPARC_REG_F46 = 40
+SPARC_REG_F48 = 41
+SPARC_REG_F50 = 42
+SPARC_REG_F52 = 43
+SPARC_REG_F54 = 44
+SPARC_REG_F56 = 45
+SPARC_REG_F58 = 46
+SPARC_REG_F60 = 47
+SPARC_REG_F62 = 48
+SPARC_REG_FCC0 = 49
+SPARC_REG_FCC1 = 50
+SPARC_REG_FCC2 = 51
+SPARC_REG_FCC3 = 52
+SPARC_REG_FP = 53
+SPARC_REG_G0 = 54
+SPARC_REG_G1 = 55
+SPARC_REG_G2 = 56
+SPARC_REG_G3 = 57
+SPARC_REG_G4 = 58
+SPARC_REG_G5 = 59
+SPARC_REG_G6 = 60
+SPARC_REG_G7 = 61
+SPARC_REG_I0 = 62
+SPARC_REG_I1 = 63
+SPARC_REG_I2 = 64
+SPARC_REG_I3 = 65
+SPARC_REG_I4 = 66
+SPARC_REG_I5 = 67
+SPARC_REG_I7 = 68
+SPARC_REG_ICC = 69
+SPARC_REG_L0 = 70
+SPARC_REG_L1 = 71
+SPARC_REG_L2 = 72
+SPARC_REG_L3 = 73
+SPARC_REG_L4 = 74
+SPARC_REG_L5 = 75
+SPARC_REG_L6 = 76
+SPARC_REG_L7 = 77
+SPARC_REG_O0 = 78
+SPARC_REG_O1 = 79
+SPARC_REG_O2 = 80
+SPARC_REG_O3 = 81
+SPARC_REG_O4 = 82
+SPARC_REG_O5 = 83
+SPARC_REG_O7 = 84
+SPARC_REG_SP = 85
+SPARC_REG_Y = 86
+SPARC_REG_XCC = 87
+SPARC_REG_ENDING = 88
+SPARC_REG_O6 = SPARC_REG_SP
+SPARC_REG_I6 = SPARC_REG_FP
+
+SPARC_INS_INVALID = 0
+SPARC_INS_ADDCC = 1
+SPARC_INS_ADDX = 2
+SPARC_INS_ADDXCC = 3
+SPARC_INS_ADDXC = 4
+SPARC_INS_ADDXCCC = 5
+SPARC_INS_ADD = 6
+SPARC_INS_ALIGNADDR = 7
+SPARC_INS_ALIGNADDRL = 8
+SPARC_INS_ANDCC = 9
+SPARC_INS_ANDNCC = 10
+SPARC_INS_ANDN = 11
+SPARC_INS_AND = 12
+SPARC_INS_ARRAY16 = 13
+SPARC_INS_ARRAY32 = 14
+SPARC_INS_ARRAY8 = 15
+SPARC_INS_B = 16
+SPARC_INS_JMP = 17
+SPARC_INS_BMASK = 18
+SPARC_INS_FB = 19
+SPARC_INS_BRGEZ = 20
+SPARC_INS_BRGZ = 21
+SPARC_INS_BRLEZ = 22
+SPARC_INS_BRLZ = 23
+SPARC_INS_BRNZ = 24
+SPARC_INS_BRZ = 25
+SPARC_INS_BSHUFFLE = 26
+SPARC_INS_CALL = 27
+SPARC_INS_CASX = 28
+SPARC_INS_CAS = 29
+SPARC_INS_CMASK16 = 30
+SPARC_INS_CMASK32 = 31
+SPARC_INS_CMASK8 = 32
+SPARC_INS_CMP = 33
+SPARC_INS_EDGE16 = 34
+SPARC_INS_EDGE16L = 35
+SPARC_INS_EDGE16LN = 36
+SPARC_INS_EDGE16N = 37
+SPARC_INS_EDGE32 = 38
+SPARC_INS_EDGE32L = 39
+SPARC_INS_EDGE32LN = 40
+SPARC_INS_EDGE32N = 41
+SPARC_INS_EDGE8 = 42
+SPARC_INS_EDGE8L = 43
+SPARC_INS_EDGE8LN = 44
+SPARC_INS_EDGE8N = 45
+SPARC_INS_FABSD = 46
+SPARC_INS_FABSQ = 47
+SPARC_INS_FABSS = 48
+SPARC_INS_FADDD = 49
+SPARC_INS_FADDQ = 50
+SPARC_INS_FADDS = 51
+SPARC_INS_FALIGNDATA = 52
+SPARC_INS_FAND = 53
+SPARC_INS_FANDNOT1 = 54
+SPARC_INS_FANDNOT1S = 55
+SPARC_INS_FANDNOT2 = 56
+SPARC_INS_FANDNOT2S = 57
+SPARC_INS_FANDS = 58
+SPARC_INS_FCHKSM16 = 59
+SPARC_INS_FCMPD = 60
+SPARC_INS_FCMPEQ16 = 61
+SPARC_INS_FCMPEQ32 = 62
+SPARC_INS_FCMPGT16 = 63
+SPARC_INS_FCMPGT32 = 64
+SPARC_INS_FCMPLE16 = 65
+SPARC_INS_FCMPLE32 = 66
+SPARC_INS_FCMPNE16 = 67
+SPARC_INS_FCMPNE32 = 68
+SPARC_INS_FCMPQ = 69
+SPARC_INS_FCMPS = 70
+SPARC_INS_FDIVD = 71
+SPARC_INS_FDIVQ = 72
+SPARC_INS_FDIVS = 73
+SPARC_INS_FDMULQ = 74
+SPARC_INS_FDTOI = 75
+SPARC_INS_FDTOQ = 76
+SPARC_INS_FDTOS = 77
+SPARC_INS_FDTOX = 78
+SPARC_INS_FEXPAND = 79
+SPARC_INS_FHADDD = 80
+SPARC_INS_FHADDS = 81
+SPARC_INS_FHSUBD = 82
+SPARC_INS_FHSUBS = 83
+SPARC_INS_FITOD = 84
+SPARC_INS_FITOQ = 85
+SPARC_INS_FITOS = 86
+SPARC_INS_FLCMPD = 87
+SPARC_INS_FLCMPS = 88
+SPARC_INS_FLUSHW = 89
+SPARC_INS_FMEAN16 = 90
+SPARC_INS_FMOVD = 91
+SPARC_INS_FMOVQ = 92
+SPARC_INS_FMOVRDGEZ = 93
+SPARC_INS_FMOVRQGEZ = 94
+SPARC_INS_FMOVRSGEZ = 95
+SPARC_INS_FMOVRDGZ = 96
+SPARC_INS_FMOVRQGZ = 97
+SPARC_INS_FMOVRSGZ = 98
+SPARC_INS_FMOVRDLEZ = 99
+SPARC_INS_FMOVRQLEZ = 100
+SPARC_INS_FMOVRSLEZ = 101
+SPARC_INS_FMOVRDLZ = 102
+SPARC_INS_FMOVRQLZ = 103
+SPARC_INS_FMOVRSLZ = 104
+SPARC_INS_FMOVRDNZ = 105
+SPARC_INS_FMOVRQNZ = 106
+SPARC_INS_FMOVRSNZ = 107
+SPARC_INS_FMOVRDZ = 108
+SPARC_INS_FMOVRQZ = 109
+SPARC_INS_FMOVRSZ = 110
+SPARC_INS_FMOVS = 111
+SPARC_INS_FMUL8SUX16 = 112
+SPARC_INS_FMUL8ULX16 = 113
+SPARC_INS_FMUL8X16 = 114
+SPARC_INS_FMUL8X16AL = 115
+SPARC_INS_FMUL8X16AU = 116
+SPARC_INS_FMULD = 117
+SPARC_INS_FMULD8SUX16 = 118
+SPARC_INS_FMULD8ULX16 = 119
+SPARC_INS_FMULQ = 120
+SPARC_INS_FMULS = 121
+SPARC_INS_FNADDD = 122
+SPARC_INS_FNADDS = 123
+SPARC_INS_FNAND = 124
+SPARC_INS_FNANDS = 125
+SPARC_INS_FNEGD = 126
+SPARC_INS_FNEGQ = 127
+SPARC_INS_FNEGS = 128
+SPARC_INS_FNHADDD = 129
+SPARC_INS_FNHADDS = 130
+SPARC_INS_FNOR = 131
+SPARC_INS_FNORS = 132
+SPARC_INS_FNOT1 = 133
+SPARC_INS_FNOT1S = 134
+SPARC_INS_FNOT2 = 135
+SPARC_INS_FNOT2S = 136
+SPARC_INS_FONE = 137
+SPARC_INS_FONES = 138
+SPARC_INS_FOR = 139
+SPARC_INS_FORNOT1 = 140
+SPARC_INS_FORNOT1S = 141
+SPARC_INS_FORNOT2 = 142
+SPARC_INS_FORNOT2S = 143
+SPARC_INS_FORS = 144
+SPARC_INS_FPACK16 = 145
+SPARC_INS_FPACK32 = 146
+SPARC_INS_FPACKFIX = 147
+SPARC_INS_FPADD16 = 148
+SPARC_INS_FPADD16S = 149
+SPARC_INS_FPADD32 = 150
+SPARC_INS_FPADD32S = 151
+SPARC_INS_FPADD64 = 152
+SPARC_INS_FPMERGE = 153
+SPARC_INS_FPSUB16 = 154
+SPARC_INS_FPSUB16S = 155
+SPARC_INS_FPSUB32 = 156
+SPARC_INS_FPSUB32S = 157
+SPARC_INS_FQTOD = 158
+SPARC_INS_FQTOI = 159
+SPARC_INS_FQTOS = 160
+SPARC_INS_FQTOX = 161
+SPARC_INS_FSLAS16 = 162
+SPARC_INS_FSLAS32 = 163
+SPARC_INS_FSLL16 = 164
+SPARC_INS_FSLL32 = 165
+SPARC_INS_FSMULD = 166
+SPARC_INS_FSQRTD = 167
+SPARC_INS_FSQRTQ = 168
+SPARC_INS_FSQRTS = 169
+SPARC_INS_FSRA16 = 170
+SPARC_INS_FSRA32 = 171
+SPARC_INS_FSRC1 = 172
+SPARC_INS_FSRC1S = 173
+SPARC_INS_FSRC2 = 174
+SPARC_INS_FSRC2S = 175
+SPARC_INS_FSRL16 = 176
+SPARC_INS_FSRL32 = 177
+SPARC_INS_FSTOD = 178
+SPARC_INS_FSTOI = 179
+SPARC_INS_FSTOQ = 180
+SPARC_INS_FSTOX = 181
+SPARC_INS_FSUBD = 182
+SPARC_INS_FSUBQ = 183
+SPARC_INS_FSUBS = 184
+SPARC_INS_FXNOR = 185
+SPARC_INS_FXNORS = 186
+SPARC_INS_FXOR = 187
+SPARC_INS_FXORS = 188
+SPARC_INS_FXTOD = 189
+SPARC_INS_FXTOQ = 190
+SPARC_INS_FXTOS = 191
+SPARC_INS_FZERO = 192
+SPARC_INS_FZEROS = 193
+SPARC_INS_JMPL = 194
+SPARC_INS_LDD = 195
+SPARC_INS_LD = 196
+SPARC_INS_LDQ = 197
+SPARC_INS_LDSB = 198
+SPARC_INS_LDSH = 199
+SPARC_INS_LDSW = 200
+SPARC_INS_LDUB = 201
+SPARC_INS_LDUH = 202
+SPARC_INS_LDX = 203
+SPARC_INS_LZCNT = 204
+SPARC_INS_MEMBAR = 205
+SPARC_INS_MOVDTOX = 206
+SPARC_INS_MOV = 207
+SPARC_INS_MOVRGEZ = 208
+SPARC_INS_MOVRGZ = 209
+SPARC_INS_MOVRLEZ = 210
+SPARC_INS_MOVRLZ = 211
+SPARC_INS_MOVRNZ = 212
+SPARC_INS_MOVRZ = 213
+SPARC_INS_MOVSTOSW = 214
+SPARC_INS_MOVSTOUW = 215
+SPARC_INS_MULX = 216
+SPARC_INS_NOP = 217
+SPARC_INS_ORCC = 218
+SPARC_INS_ORNCC = 219
+SPARC_INS_ORN = 220
+SPARC_INS_OR = 221
+SPARC_INS_PDIST = 222
+SPARC_INS_PDISTN = 223
+SPARC_INS_POPC = 224
+SPARC_INS_RD = 225
+SPARC_INS_RESTORE = 226
+SPARC_INS_RETT = 227
+SPARC_INS_SAVE = 228
+SPARC_INS_SDIVCC = 229
+SPARC_INS_SDIVX = 230
+SPARC_INS_SDIV = 231
+SPARC_INS_SETHI = 232
+SPARC_INS_SHUTDOWN = 233
+SPARC_INS_SIAM = 234
+SPARC_INS_SLLX = 235
+SPARC_INS_SLL = 236
+SPARC_INS_SMULCC = 237
+SPARC_INS_SMUL = 238
+SPARC_INS_SRAX = 239
+SPARC_INS_SRA = 240
+SPARC_INS_SRLX = 241
+SPARC_INS_SRL = 242
+SPARC_INS_STBAR = 243
+SPARC_INS_STB = 244
+SPARC_INS_STD = 245
+SPARC_INS_ST = 246
+SPARC_INS_STH = 247
+SPARC_INS_STQ = 248
+SPARC_INS_STX = 249
+SPARC_INS_SUBCC = 250
+SPARC_INS_SUBX = 251
+SPARC_INS_SUBXCC = 252
+SPARC_INS_SUB = 253
+SPARC_INS_SWAP = 254
+SPARC_INS_TADDCCTV = 255
+SPARC_INS_TADDCC = 256
+SPARC_INS_T = 257
+SPARC_INS_TSUBCCTV = 258
+SPARC_INS_TSUBCC = 259
+SPARC_INS_UDIVCC = 260
+SPARC_INS_UDIVX = 261
+SPARC_INS_UDIV = 262
+SPARC_INS_UMULCC = 263
+SPARC_INS_UMULXHI = 264
+SPARC_INS_UMUL = 265
+SPARC_INS_UNIMP = 266
+SPARC_INS_FCMPED = 267
+SPARC_INS_FCMPEQ = 268
+SPARC_INS_FCMPES = 269
+SPARC_INS_WR = 270
+SPARC_INS_XMULX = 271
+SPARC_INS_XMULXHI = 272
+SPARC_INS_XNORCC = 273
+SPARC_INS_XNOR = 274
+SPARC_INS_XORCC = 275
+SPARC_INS_XOR = 276
+SPARC_INS_RET = 277
+SPARC_INS_RETL = 278
+SPARC_INS_ENDING = 279
+
+SPARC_GRP_INVALID = 0
+SPARC_GRP_JUMP = 1
+SPARC_GRP_HARDQUAD = 128
+SPARC_GRP_V9 = 129
+SPARC_GRP_VIS = 130
+SPARC_GRP_VIS2 = 131
+SPARC_GRP_VIS3 = 132
+SPARC_GRP_32BIT = 133
+SPARC_GRP_64BIT = 134
+SPARC_GRP_ENDING = 135

.tools/python-revlibs/capstone/systemz.py

@@ -0,0 +1,51 @@
+# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
+
+import ctypes
+from . import copy_ctypes_list
+from .sysz_const import *
+
+# define the API
+class SyszOpMem(ctypes.Structure):
+    _fields_ = (
+        ('base', ctypes.c_uint8),
+        ('index', ctypes.c_uint8),
+        ('length', ctypes.c_uint64),
+        ('disp', ctypes.c_int64),
+    )
+
+class SyszOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_int64),
+        ('mem', SyszOpMem),
+    )
+
+class SyszOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', SyszOpValue),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+
+class CsSysz(ctypes.Structure):
+    _fields_ = (
+        ('cc', ctypes.c_uint),
+        ('op_count', ctypes.c_uint8),
+        ('operands', SyszOp * 6),
+    )
+
+def get_arch_info(a):
+    return (a.cc, copy_ctypes_list(a.operands[:a.op_count]))
+

.tools/python-revlibs/capstone/tms320c64x.py

@@ -0,0 +1,66 @@
+# Capstone Python bindings, by Fotis Loukos <me@fotisl.com>
+
+import ctypes, copy
+from .tms320c64x_const import *
+
+# define the API
+class TMS320C64xOpMem(ctypes.Structure):
+    _fields_ = (
+        ('base', ctypes.c_int),
+        ('disp', ctypes.c_int),
+        ('unit', ctypes.c_int),
+        ('scaled', ctypes.c_int),
+        ('disptype', ctypes.c_int),
+        ('direction', ctypes.c_int),
+        ('modify', ctypes.c_int),
+    )
+
+class TMS320C64xOpValue(ctypes.Union):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('imm', ctypes.c_int32),
+        ('mem', TMS320C64xOpMem),
+    )
+
+class TMS320C64xCondition(ctypes.Structure):
+    _fields_ = (
+        ('reg', ctypes.c_uint),
+        ('zero', ctypes.c_uint),
+    )
+
+class TMS320C64xFunctionalUnit(ctypes.Structure):
+    _fields_ = (
+        ('unit', ctypes.c_uint),
+        ('side', ctypes.c_uint),
+        ('crosspath', ctypes.c_uint),
+    )
+
+class TMS320C64xOp(ctypes.Structure):
+    _fields_ = (
+        ('type', ctypes.c_uint),
+        ('value', TMS320C64xOpValue),
+    )
+
+    @property
+    def imm(self):
+        return self.value.imm
+
+    @property
+    def reg(self):
+        return self.value.reg
+
+    @property
+    def mem(self):
+        return self.value.mem
+
+class CsTMS320C64x(ctypes.Structure):
+    _fields_ = (
+        ('op_count', ctypes.c_uint8),
+        ('operands', TMS320C64xOp * 8),
+        ('condition', TMS320C64xCondition),
+        ('funit', TMS320C64xFunctionalUnit),
+        ('parallel', ctypes.c_uint),
+    )
+
+def get_arch_info(a):
+    return (a.condition, a.funit, a.parallel, copy.deepcopy(a.operands[:a.op_count]))

.tools/python-revlibs/capstone/tms320c64x_const.py

@@ -0,0 +1,278 @@
+from . import CS_OP_INVALID, CS_OP_REG, CS_OP_IMM, CS_OP_MEM
+# For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [tms320c64x_const.py]
+
+TMS320C64X_OP_INVALID = 0
+TMS320C64X_OP_REG = 1
+TMS320C64X_OP_IMM = 2
+TMS320C64X_OP_MEM = 3
+TMS320C64X_OP_REGPAIR = 64
+
+TMS320C64X_MEM_DISP_INVALID = 0
+TMS320C64X_MEM_DISP_CONSTANT = 1
+TMS320C64X_MEM_DISP_REGISTER = 2
+
+TMS320C64X_MEM_DIR_INVALID = 0
+TMS320C64X_MEM_DIR_FW = 1
+TMS320C64X_MEM_DIR_BW = 2
+
+TMS320C64X_MEM_MOD_INVALID = 0
+TMS320C64X_MEM_MOD_NO = 1
+TMS320C64X_MEM_MOD_PRE = 2
+TMS320C64X_MEM_MOD_POST = 3
+
+TMS320C64X_REG_INVALID = 0
+TMS320C64X_REG_AMR = 1
+TMS320C64X_REG_CSR = 2
+TMS320C64X_REG_DIER = 3
+TMS320C64X_REG_DNUM = 4
+TMS320C64X_REG_ECR = 5
+TMS320C64X_REG_GFPGFR = 6
+TMS320C64X_REG_GPLYA = 7
+TMS320C64X_REG_GPLYB = 8
+TMS320C64X_REG_ICR = 9
+TMS320C64X_REG_IER = 10
+TMS320C64X_REG_IERR = 11
+TMS320C64X_REG_ILC = 12
+TMS320C64X_REG_IRP = 13
+TMS320C64X_REG_ISR = 14
+TMS320C64X_REG_ISTP = 15
+TMS320C64X_REG_ITSR = 16
+TMS320C64X_REG_NRP = 17
+TMS320C64X_REG_NTSR = 18
+TMS320C64X_REG_REP = 19
+TMS320C64X_REG_RILC = 20
+TMS320C64X_REG_SSR = 21
+TMS320C64X_REG_TSCH = 22
+TMS320C64X_REG_TSCL = 23
+TMS320C64X_REG_TSR = 24
+TMS320C64X_REG_A0 = 25
+TMS320C64X_REG_A1 = 26
+TMS320C64X_REG_A2 = 27
+TMS320C64X_REG_A3 = 28
+TMS320C64X_REG_A4 = 29
+TMS320C64X_REG_A5 = 30
+TMS320C64X_REG_A6 = 31
+TMS320C64X_REG_A7 = 32
+TMS320C64X_REG_A8 = 33
+TMS320C64X_REG_A9 = 34
+TMS320C64X_REG_A10 = 35
+TMS320C64X_REG_A11 = 36
+TMS320C64X_REG_A12 = 37
+TMS320C64X_REG_A13 = 38
+TMS320C64X_REG_A14 = 39
+TMS320C64X_REG_A15 = 40
+TMS320C64X_REG_A16 = 41
+TMS320C64X_REG_A17 = 42
+TMS320C64X_REG_A18 = 43
+TMS320C64X_REG_A19 = 44
+TMS320C64X_REG_A20 = 45
+TMS320C64X_REG_A21 = 46
+TMS320C64X_REG_A22 = 47
+TMS320C64X_REG_A23 = 48
+TMS320C64X_REG_A24 = 49
+TMS320C64X_REG_A25 = 50
+TMS320C64X_REG_A26 = 51
+TMS320C64X_REG_A27 = 52
+TMS320C64X_REG_A28 = 53
+TMS320C64X_REG_A29 = 54
+TMS320C64X_REG_A30 = 55
+TMS320C64X_REG_A31 = 56
+TMS320C64X_REG_B0 = 57
+TMS320C64X_REG_B1 = 58
+TMS320C64X_REG_B2 = 59
+TMS320C64X_REG_B3 = 60
+TMS320C64X_REG_B4 = 61
+TMS320C64X_REG_B5 = 62
+TMS320C64X_REG_B6 = 63
+TMS320C64X_REG_B7 = 64
+TMS320C64X_REG_B8 = 65
+TMS320C64X_REG_B9 = 66
+TMS320C64X_REG_B10 = 67
+TMS320C64X_REG_B11 = 68
+TMS320C64X_REG_B12 = 69
+TMS320C64X_REG_B13 = 70
+TMS320C64X_REG_B14 = 71
+TMS320C64X_REG_B15 = 72
+TMS320C64X_REG_B16 = 73
+TMS320C64X_REG_B17 = 74
+TMS320C64X_REG_B18 = 75
+TMS320C64X_REG_B19 = 76
+TMS320C64X_REG_B20 = 77
+TMS320C64X_REG_B21 = 78
+TMS320C64X_REG_B22 = 79
+TMS320C64X_REG_B23 = 80
+TMS320C64X_REG_B24 = 81
+TMS320C64X_REG_B25 = 82
+TMS320C64X_REG_B26 = 83
+TMS320C64X_REG_B27 = 84
+TMS320C64X_REG_B28 = 85
+TMS320C64X_REG_B29 = 86
+TMS320C64X_REG_B30 = 87
+TMS320C64X_REG_B31 = 88
+TMS320C64X_REG_PCE1 = 89
+TMS320C64X_REG_ENDING = 90
+TMS320C64X_REG_EFR = TMS320C64X_REG_ECR
+TMS320C64X_REG_IFR = TMS320C64X_REG_ISR
+
+TMS320C64X_INS_INVALID = 0
+TMS320C64X_INS_ABS = 1
+TMS320C64X_INS_ABS2 = 2
+TMS320C64X_INS_ADD = 3
+TMS320C64X_INS_ADD2 = 4
+TMS320C64X_INS_ADD4 = 5
+TMS320C64X_INS_ADDAB = 6
+TMS320C64X_INS_ADDAD = 7
+TMS320C64X_INS_ADDAH = 8
+TMS320C64X_INS_ADDAW = 9
+TMS320C64X_INS_ADDK = 10
+TMS320C64X_INS_ADDKPC = 11
+TMS320C64X_INS_ADDU = 12
+TMS320C64X_INS_AND = 13
+TMS320C64X_INS_ANDN = 14
+TMS320C64X_INS_AVG2 = 15
+TMS320C64X_INS_AVGU4 = 16
+TMS320C64X_INS_B = 17
+TMS320C64X_INS_BDEC = 18
+TMS320C64X_INS_BITC4 = 19
+TMS320C64X_INS_BNOP = 20
+TMS320C64X_INS_BPOS = 21
+TMS320C64X_INS_CLR = 22
+TMS320C64X_INS_CMPEQ = 23
+TMS320C64X_INS_CMPEQ2 = 24
+TMS320C64X_INS_CMPEQ4 = 25
+TMS320C64X_INS_CMPGT = 26
+TMS320C64X_INS_CMPGT2 = 27
+TMS320C64X_INS_CMPGTU4 = 28
+TMS320C64X_INS_CMPLT = 29
+TMS320C64X_INS_CMPLTU = 30
+TMS320C64X_INS_DEAL = 31
+TMS320C64X_INS_DOTP2 = 32
+TMS320C64X_INS_DOTPN2 = 33
+TMS320C64X_INS_DOTPNRSU2 = 34
+TMS320C64X_INS_DOTPRSU2 = 35
+TMS320C64X_INS_DOTPSU4 = 36
+TMS320C64X_INS_DOTPU4 = 37
+TMS320C64X_INS_EXT = 38
+TMS320C64X_INS_EXTU = 39
+TMS320C64X_INS_GMPGTU = 40
+TMS320C64X_INS_GMPY4 = 41
+TMS320C64X_INS_LDB = 42
+TMS320C64X_INS_LDBU = 43
+TMS320C64X_INS_LDDW = 44
+TMS320C64X_INS_LDH = 45
+TMS320C64X_INS_LDHU = 46
+TMS320C64X_INS_LDNDW = 47
+TMS320C64X_INS_LDNW = 48
+TMS320C64X_INS_LDW = 49
+TMS320C64X_INS_LMBD = 50
+TMS320C64X_INS_MAX2 = 51
+TMS320C64X_INS_MAXU4 = 52
+TMS320C64X_INS_MIN2 = 53
+TMS320C64X_INS_MINU4 = 54
+TMS320C64X_INS_MPY = 55
+TMS320C64X_INS_MPY2 = 56
+TMS320C64X_INS_MPYH = 57
+TMS320C64X_INS_MPYHI = 58
+TMS320C64X_INS_MPYHIR = 59
+TMS320C64X_INS_MPYHL = 60
+TMS320C64X_INS_MPYHLU = 61
+TMS320C64X_INS_MPYHSLU = 62
+TMS320C64X_INS_MPYHSU = 63
+TMS320C64X_INS_MPYHU = 64
+TMS320C64X_INS_MPYHULS = 65
+TMS320C64X_INS_MPYHUS = 66
+TMS320C64X_INS_MPYLH = 67
+TMS320C64X_INS_MPYLHU = 68
+TMS320C64X_INS_MPYLI = 69
+TMS320C64X_INS_MPYLIR = 70
+TMS320C64X_INS_MPYLSHU = 71
+TMS320C64X_INS_MPYLUHS = 72
+TMS320C64X_INS_MPYSU = 73
+TMS320C64X_INS_MPYSU4 = 74
+TMS320C64X_INS_MPYU = 75
+TMS320C64X_INS_MPYU4 = 76
+TMS320C64X_INS_MPYUS = 77
+TMS320C64X_INS_MVC = 78
+TMS320C64X_INS_MVD = 79
+TMS320C64X_INS_MVK = 80
+TMS320C64X_INS_MVKL = 81
+TMS320C64X_INS_MVKLH = 82
+TMS320C64X_INS_NOP = 83
+TMS320C64X_INS_NORM = 84
+TMS320C64X_INS_OR = 85
+TMS320C64X_INS_PACK2 = 86
+TMS320C64X_INS_PACKH2 = 87
+TMS320C64X_INS_PACKH4 = 88
+TMS320C64X_INS_PACKHL2 = 89
+TMS320C64X_INS_PACKL4 = 90
+TMS320C64X_INS_PACKLH2 = 91
+TMS320C64X_INS_ROTL = 92
+TMS320C64X_INS_SADD = 93
+TMS320C64X_INS_SADD2 = 94
+TMS320C64X_INS_SADDU4 = 95
+TMS320C64X_INS_SADDUS2 = 96
+TMS320C64X_INS_SAT = 97
+TMS320C64X_INS_SET = 98
+TMS320C64X_INS_SHFL = 99
+TMS320C64X_INS_SHL = 100
+TMS320C64X_INS_SHLMB = 101
+TMS320C64X_INS_SHR = 102
+TMS320C64X_INS_SHR2 = 103
+TMS320C64X_INS_SHRMB = 104
+TMS320C64X_INS_SHRU = 105
+TMS320C64X_INS_SHRU2 = 106
+TMS320C64X_INS_SMPY = 107
+TMS320C64X_INS_SMPY2 = 108
+TMS320C64X_INS_SMPYH = 109
+TMS320C64X_INS_SMPYHL = 110
+TMS320C64X_INS_SMPYLH = 111
+TMS320C64X_INS_SPACK2 = 112
+TMS320C64X_INS_SPACKU4 = 113
+TMS320C64X_INS_SSHL = 114
+TMS320C64X_INS_SSHVL = 115
+TMS320C64X_INS_SSHVR = 116
+TMS320C64X_INS_SSUB = 117
+TMS320C64X_INS_STB = 118
+TMS320C64X_INS_STDW = 119
+TMS320C64X_INS_STH = 120
+TMS320C64X_INS_STNDW = 121
+TMS320C64X_INS_STNW = 122
+TMS320C64X_INS_STW = 123
+TMS320C64X_INS_SUB = 124
+TMS320C64X_INS_SUB2 = 125
+TMS320C64X_INS_SUB4 = 126
+TMS320C64X_INS_SUBAB = 127
+TMS320C64X_INS_SUBABS4 = 128
+TMS320C64X_INS_SUBAH = 129
+TMS320C64X_INS_SUBAW = 130
+TMS320C64X_INS_SUBC = 131
+TMS320C64X_INS_SUBU = 132
+TMS320C64X_INS_SWAP4 = 133
+TMS320C64X_INS_UNPKHU4 = 134
+TMS320C64X_INS_UNPKLU4 = 135
+TMS320C64X_INS_XOR = 136
+TMS320C64X_INS_XPND2 = 137
+TMS320C64X_INS_XPND4 = 138
+TMS320C64X_INS_IDLE = 139
+TMS320C64X_INS_MV = 140
+TMS320C64X_INS_NEG = 141
+TMS320C64X_INS_NOT = 142
+TMS320C64X_INS_SWAP2 = 143
+TMS320C64X_INS_ZERO = 144
+TMS320C64X_INS_ENDING = 145
+
+TMS320C64X_GRP_INVALID = 0
+TMS320C64X_GRP_JUMP = 1
+TMS320C64X_GRP_FUNIT_D = 128
+TMS320C64X_GRP_FUNIT_L = 129
+TMS320C64X_GRP_FUNIT_M = 130
+TMS320C64X_GRP_FUNIT_S = 131
+TMS320C64X_GRP_FUNIT_NO = 132
+TMS320C64X_GRP_ENDING = 133
+
+TMS320C64X_FUNIT_INVALID = 0
+TMS320C64X_FUNIT_D = 1
+TMS320C64X_FUNIT_L = 2
+TMS320C64X_FUNIT_M = 3
+TMS320C64X_FUNIT_S = 4
+TMS320C64X_FUNIT_NO = 5