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ZXCLI
2026-06-12 16:22:17 +08:00
parent 205daf0cab
commit c0c195331c
693 changed files with 243421 additions and 1 deletions
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28379d_P_SFRA/device/driverlib/adc.c
+342
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//###########################################################################
//
// FILE: adc.c
//
// TITLE: C28x ADC driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "adc.h"
//*****************************************************************************
//
// Defines for locations of ADC calibration functions in OTP for use in
// ADC_setMode() ONLY. Not intended for use by application code.
//
//*****************************************************************************
//
// The following functions calibrate the ADC linearity. Use them in the
// ADC_setMode() function only.
//
#define ADC_calADCAINL 0x0703B4U
#define ADC_calADCBINL 0x0703B2U
#define ADC_calADCCINL 0x0703B0U
#define ADC_calADCDINL 0x0703AEU
//
// This function looks up the ADC offset trim for a given condition. Use this
// in the ADC_setMode() function only.
//
#define ADC_getOffsetTrim 0x0703ACU
//*****************************************************************************
//
// ADC_setMode
//
//*****************************************************************************
void
ADC_setMode(uint32_t base, ADC_Resolution resolution,
ADC_SignalMode signalMode)
{
//
// Check the arguments.
//
ASSERT(ADC_isBaseValid(base));
//
// Check for correct signal mode & resolution. In this device:
// Single ended signal conversions are supported in 12-bit mode only
// Differential signal conversions are supported in 16-bit mode only
//
if(signalMode == ADC_MODE_SINGLE_ENDED)
{
ASSERT(resolution == ADC_RESOLUTION_12BIT);
}
else
{
ASSERT(resolution == ADC_RESOLUTION_16BIT);
}
//
// Apply the resolution and signalMode to the specified ADC.
//
EALLOW;
HWREGH(base + ADC_O_CTL2) = (HWREGH(base + ADC_O_CTL2) &
~(ADC_CTL2_RESOLUTION | ADC_CTL2_SIGNALMODE)) |
((uint16_t)resolution | (uint16_t)signalMode);
EDIS;
//
// Apply INL and offset trims
//
ADC_setINLTrim(base);
ADC_setOffsetTrim(base);
}
//*****************************************************************************
//
// ADC_setINLTrim
//
//*****************************************************************************
void
ADC_setINLTrim(uint32_t base)
{
ADC_Resolution resolution;
//
// Check the arguments.
//
ASSERT(ADC_isBaseValid(base));
resolution = (ADC_Resolution)
(HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION);
EALLOW;
switch(base)
{
case ADCA_BASE:
if(HWREGH(ADC_calADCAINL) != 0xFFFFU)
{
//
// Trim function is programmed into OTP, so call it
//
(*((void (*)(void))ADC_calADCAINL))();
}
else
{
//
// Do nothing, no INL trim function populated
//
}
break;
case ADCB_BASE:
if(HWREGH(ADC_calADCBINL) != 0xFFFFU)
{
//
// Trim function is programmed into OTP, so call it
//
(*((void (*)(void))ADC_calADCBINL))();
}
else
{
//
// Do nothing, no INL trim function populated
//
}
break;
case ADCC_BASE:
if(HWREGH(ADC_calADCCINL) != 0xFFFFU)
{
//
// Trim function is programmed into OTP, so call it
//
(*((void (*)(void))ADC_calADCCINL))();
}
else
{
//
// Do nothing, no INL trim function populated
//
}
break;
case ADCD_BASE:
if(HWREGH(ADC_calADCDINL) != 0xFFFFU)
{
//
// Trim function is programmed into OTP, so call it
//
(*((void (*)(void))ADC_calADCDINL))();
}
else
{
//
// Do nothing, no INL trim function populated
//
}
break;
default:
//
// Invalid base address! Do nothing!
//
break;
}
//
// Apply linearity trim workaround for 12-bit resolution
//
if(resolution == ADC_RESOLUTION_12BIT)
{
//
// 12-bit linearity trim workaround
//
HWREG(base + ADC_O_INLTRIM1) &= 0xFFFF0000U;
HWREG(base + ADC_O_INLTRIM2) &= 0xFFFF0000U;
HWREG(base + ADC_O_INLTRIM4) &= 0xFFFF0000U;
HWREG(base + ADC_O_INLTRIM5) &= 0xFFFF0000U;
}
EDIS;
}
//*****************************************************************************
//
// ADC_setOffsetTrim
//
//*****************************************************************************
void
ADC_setOffsetTrim(uint32_t base)
{
uint16_t offsetIndex = 0U;
uint16_t offsetTrim = 0U;
ADC_Resolution resolution;
ADC_SignalMode signalMode;
//
// Check the arguments.
//
ASSERT(ADC_isBaseValid(base));
resolution = (ADC_Resolution)
(HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION);
signalMode = (ADC_SignalMode)
(HWREGH(base + ADC_O_CTL2) & ADC_CTL2_SIGNALMODE);
switch(base)
{
case ADCA_BASE:
offsetIndex = (uint16_t)(0U * 4U);
break;
case ADCB_BASE:
offsetIndex = (uint16_t)(1U * 4U);
break;
case ADCC_BASE:
offsetIndex = (uint16_t)(2U * 4U);
break;
case ADCD_BASE:
offsetIndex = (uint16_t)(3U * 4U);
break;
default:
//
// Invalid base address!
//
offsetIndex = 0U;
break;
}
//
// Offset trim function is programmed into OTP, so call it
//
if(HWREGH(ADC_getOffsetTrim) != 0xFFFFU)
{
//
// Calculate the index into OTP table of offset trims and call
// function to return the correct offset trim
//
offsetIndex += ((signalMode == ADC_MODE_DIFFERENTIAL) ? 1U : 0U) +
(2U * ((resolution == ADC_RESOLUTION_16BIT) ? 1U : 0U));
offsetTrim =
(*((uint16_t (*)(uint16_t index))ADC_getOffsetTrim))(offsetIndex);
}
else
{
//
// Offset trim function is not populated, so set offset trim to 0
//
offsetTrim = 0U;
}
//
// Apply the offset trim. Offset Trim is not updated here in case of TMX or
// untrimmed devices. The default trims for TMX devices should be handled in
// Device_init(). Refer to Device_init() and Device_configureTMXAnalogTrim()
// APIs for more details.
//
if(offsetTrim > 0x0U)
{
EALLOW;
HWREGH(base + ADC_O_OFFTRIM) = offsetTrim;
EDIS;
}
}
//*****************************************************************************
//
// ADC_setPPBTripLimits
//
//*****************************************************************************
void
ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber,
int32_t tripHiLimit, int32_t tripLoLimit)
{
uint32_t ppbHiOffset;
uint32_t ppbLoOffset;
//
// Check the arguments.
//
ASSERT(ADC_isBaseValid(base));
ASSERT((tripHiLimit <= 65535) && (tripHiLimit >= -65536));
ASSERT((tripLoLimit <= 65535) && (tripLoLimit >= -65536));
//
// Get the offset to the appropriate trip limit registers.
//
ppbHiOffset = (ADC_PPBxTRIPHI_STEP * (uint32_t)ppbNumber) +
ADC_O_PPB1TRIPHI;
ppbLoOffset = (ADC_PPBxTRIPLO_STEP * (uint32_t)ppbNumber) +
ADC_O_PPB1TRIPLO;
EALLOW;
//
// Set the trip high limit.
//
HWREG(base + ppbHiOffset) =
(HWREG(base + ppbHiOffset) & ~ADC_PPBTRIP_MASK) |
((uint32_t)tripHiLimit & ADC_PPBTRIP_MASK);
//
// Set the trip low limit.
//
HWREG(base + ppbLoOffset) =
(HWREG(base + ppbLoOffset) & ~ADC_PPBTRIP_MASK) |
((uint32_t)tripLoLimit & ADC_PPBTRIP_MASK);
EDIS;
}
28379d_P_SFRA/device/driverlib/adc.h
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28379d_P_SFRA/device/driverlib/asysctl.c
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//###########################################################################
//
// FILE: asysctl.c
//
// TITLE: C28x Driver for Analog System Control.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "asysctl.h"
28379d_P_SFRA/device/driverlib/asysctl.h
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//###########################################################################
//
// FILE: asysctl.h
//
// TITLE: C28x driver for Analog System Control.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef ASYSCTL_H
#define ASYSCTL_H
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup asysctl_api ASysCtl
//! @{
//
//*****************************************************************************
#include <stdint.h>
#include <stdbool.h>
#include "inc/hw_asysctl.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "debug.h"
#include "cpu.h"
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Enable temperature sensor.
//!
//! This function enables the temperature sensor output to the ADC.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ASysCtl_enableTemperatureSensor(void)
{
EALLOW;
//
// Set the temperature sensor enable bit.
//
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_TSNSCTL) |= ASYSCTL_TSNSCTL_ENABLE;
EDIS;
}
//*****************************************************************************
//
//! Disable temperature sensor.
//!
//! This function disables the temperature sensor output to the ADC.
//!
//! \return None.
//
//*****************************************************************************
static inline void
ASysCtl_disableTemperatureSensor(void)
{
EALLOW;
//
// Clear the temperature sensor enable bit.
//
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_TSNSCTL) &= ~(ASYSCTL_TSNSCTL_ENABLE);
EDIS;
}
//*****************************************************************************
//
//! Locks the temperature sensor control register.
//!
//! \return None.
//
//*****************************************************************************
static inline void ASysCtl_lockTemperatureSensor(void)
{
EALLOW;
//
// Write a 1 to the lock bit in the LOCK register.
//
HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_LOCK) |= ASYSCTL_LOCK_TSNSCTL;
EDIS;
}
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // ASYSCTL_H
28379d_P_SFRA/device/driverlib/can.c
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28379d_P_SFRA/device/driverlib/can.h
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28379d_P_SFRA/device/driverlib/ccs/driverlib.projectspec
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<projectSpec>
<project
name="f2837xd_driverlib"
device="Generic C28xx Device"
cgtVersion="22.6.2.LTS"
products="C2000WARE"
launchWizard="False"
outputType="staticLibrary"
location="."
>
<configuration name="Debug" compilerBuildOptions="--opt_level=off -I../ -v28 -ml -mt --float_support=fpu32 --define=DEBUG -g --diag_warning=225 --diag_wrap=off --display_error_number --gen_func_subsections=on --gen_data_subsections=on --abi=coffabi" archiverBuildOptions="driverlib_coff.lib" outputFormat="COFF" postBuildStep="if exist driverlib_eabi.lib ${C2000_CG_ROOT}/bin/libinfo2000.exe -o driverlib.lib driverlib_eabi.lib driverlib_coff.lib"/>
<configuration name="Debug_EABI" compilerBuildOptions="--opt_level=off -I../ -v28 -ml -mt --float_support=fpu32 --define=DEBUG -g --diag_warning=225 --diag_wrap=off --display_error_number --gen_func_subsections=on --gen_data_subsections=on --abi=eabi" archiverBuildOptions="../Debug/driverlib_eabi.lib" outputFormat="ELF" postBuildStep="if exist ../Debug/driverlib_coff.lib ${C2000_CG_ROOT}/bin/libinfo2000.exe -o ../Debug/driverlib.lib ../Debug/driverlib_eabi.lib ../Debug/driverlib_coff.lib"/>
<configuration name="Release" compilerBuildOptions="-O2 -I../ -v28 -ml -mt --float_support=fpu32 -g --diag_warning=225 --diag_wrap=off --display_error_number --gen_func_subsections=on --gen_data_subsections=on --abi=coffabi" archiverBuildOptions="driverlib_coff.lib" outputFormat="COFF" postBuildStep="if exist driverlib_eabi.lib ${C2000_CG_ROOT}/bin/libinfo2000.exe -o driverlib.lib driverlib_eabi.lib driverlib_coff.lib" />
<configuration name="Release_EABI" compilerBuildOptions="-O2 -I../ -v28 -ml -mt --float_support=fpu32 -g --diag_warning=225 --diag_wrap=off --display_error_number --gen_func_subsections=on --gen_data_subsections=on --abi=eabi" archiverBuildOptions="../Release/driverlib_eabi.lib" outputFormat="ELF" postBuildStep="if exist ../Release/driverlib_coff.lib ${C2000_CG_ROOT}/bin/libinfo2000.exe -o ../Release/driverlib.lib ../Release/driverlib_eabi.lib ../Release/driverlib_coff.lib" />
<file action="link" path="../adc.c" targetDirectory="." />
<file action="link" path="../asysctl.c" targetDirectory="." />
<file action="link" path="../can.c" targetDirectory="." />
<file action="link" path="../cla.c" targetDirectory="." />
<file action="link" path="../clb.c" targetDirectory="." />
<file action="link" path="../cmpss.c" targetDirectory="." />
<file action="link" path="../cputimer.c" targetDirectory="." />
<file action="link" path="../dac.c" targetDirectory="." />
<file action="link" path="../dcsm.c" targetDirectory="." />
<file action="link" path="../dma.c" targetDirectory="." />
<file action="link" path="../ecap.c" targetDirectory="." />
<file action="link" path="../emif.c" targetDirectory="." />
<file action="link" path="../epwm.c" targetDirectory="." />
<file action="link" path="../eqep.c" targetDirectory="." />
<file action="link" path="../flash.c" targetDirectory="." />
<file action="link" path="../gpio.c" targetDirectory="." />
<file action="link" path="../hrpwm.c" targetDirectory="." />
<file action="link" path="../i2c.c" targetDirectory="." />
<file action="link" path="../ipc.c" targetDirectory="." />
<file action="link" path="../interrupt.c" targetDirectory="." />
<file action="link" path="../mcbsp.c" targetDirectory="." />
<file action="link" path="../memcfg.c" targetDirectory="." />
<file action="link" path="../sci.c" targetDirectory="." />
<file action="link" path="../sdfm.c" targetDirectory="." />
<file action="link" path="../spi.c" targetDirectory="." />
<file action="link" path="../sysctl.c" targetDirectory="." />
<file action="link" path="../upp.c" targetDirectory="." />
<file action="link" path="../usb.c" targetDirectory="." />
<file action="link" path="../version.c" targetDirectory="." />
<file action="link" path="../xbar.c" targetDirectory="." />
</project>
</projectSpec>
28379d_P_SFRA/device/driverlib/cla.c
+89
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//###########################################################################
//
// FILE: cla.c
//
// TITLE: CLA Driver Implementation File
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "cla.h"
//*****************************************************************************
//
// CLA_setTriggerSource()
//
//*****************************************************************************
void
CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger)
{
uint32_t srcSelReg;
uint32_t shiftVal;
//
// Calculate the shift value for the specified task.
//
shiftVal = ((uint32_t)taskNumber * SYSCTL_CLA1TASKSRCSEL1_TASK2_S) % 32U;
//
// Calculate the register address for the specified task.
//
if(taskNumber <= CLA_TASK_4)
{
//
// Tasks 1-4
//
srcSelReg = (uint32_t)DMACLASRCSEL_BASE + SYSCTL_O_CLA1TASKSRCSEL1;
}
else
{
//
// Tasks 5-8
//
srcSelReg = (uint32_t)DMACLASRCSEL_BASE + SYSCTL_O_CLA1TASKSRCSEL2;
}
EALLOW;
//
// Write trigger selection to the appropriate register.
//
HWREG(srcSelReg) &= ~((uint32_t)SYSCTL_CLA1TASKSRCSEL1_TASK1_M
<< shiftVal);
HWREG(srcSelReg) = HWREG(srcSelReg) | ((uint32_t)trigger << shiftVal);
EDIS;
}
28379d_P_SFRA/device/driverlib/cla.h
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//###########################################################################
//
// FILE: cla.h
//
// TITLE: CLA Driver Implementation File
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef CLA_H
#define CLA_H
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup cla_api CLA
//! \brief This module is used for configurating CLA.
//! @{
//
//*****************************************************************************
#include <stdint.h>
#include <stdbool.h>
#include "cpu.h"
#include "debug.h"
#include "inc/hw_cla.h"
#include "inc/hw_memmap.h"
#include "inc/hw_sysctl.h"
#include "inc/hw_types.h"
//*****************************************************************************
//
// Useful defines used within the driver functions. Not intended for use by
// application code.
//
//*****************************************************************************
#define CLA_NUM_EOT_INTERRUPTS (8U)
//*****************************************************************************
//
// Values that can be passed to CLA_clearTaskFlags(), CLA_forceTasks(),
// and CLA_enableTasks(), CLA_disableTasks(), and CLA_enableSoftwareInterrupt()
// as the taskFlags parameter.
//
//*****************************************************************************
#define CLA_TASKFLAG_1 (0x01U) //!< CLA Task 1 Flag
#define CLA_TASKFLAG_2 (0x02U) //!< CLA Task 2 Flag
#define CLA_TASKFLAG_3 (0x04U) //!< CLA Task 3 Flag
#define CLA_TASKFLAG_4 (0x08U) //!< CLA Task 4 Flag
#define CLA_TASKFLAG_5 (0x10U) //!< CLA Task 5 Flag
#define CLA_TASKFLAG_6 (0x20U) //!< CLA Task 6 Flag
#define CLA_TASKFLAG_7 (0x40U) //!< CLA Task 7 Flag
#define CLA_TASKFLAG_8 (0x80U) //!< CLA Task 8 Flag
#define CLA_TASKFLAG_ALL (0xFFU) //!< CLA All Task Flag
//*****************************************************************************
//
//! Values that can be passed to CLA_getPendingTaskFlag(),
//! CLA_getTaskOverflowFlag(), CLA_getTaskRunStatus(), CLA_setTriggerSource(),
//! CLA_registerEndOfTaskInterrupt(), and CLA_unregisterEndOfTaskInterrupt()
//! as the taskNumber parameter.
//
//*****************************************************************************
typedef enum
{
CLA_TASK_1, //!< CLA Task 1
CLA_TASK_2, //!< CLA Task 2
CLA_TASK_3, //!< CLA Task 3
CLA_TASK_4, //!< CLA Task 4
CLA_TASK_5, //!< CLA Task 5
CLA_TASK_6, //!< CLA Task 6
CLA_TASK_7, //!< CLA Task 7
CLA_TASK_8 //!< CLA Task 8
} CLA_TaskNumber;
#ifdef __TMS320C28XX__ // These enums are only accessible by C28x
//*****************************************************************************
//
//! Values that can be passed to CLA_mapTaskVector() as the \e claIntVect
//! parameter.
//
//*****************************************************************************
typedef enum
{
CLA_MVECT_1 = CLA_O_MVECT1, //!< Task Interrupt Vector 1
CLA_MVECT_2 = CLA_O_MVECT2, //!< Task Interrupt Vector 2
CLA_MVECT_3 = CLA_O_MVECT3, //!< Task Interrupt Vector 3
CLA_MVECT_4 = CLA_O_MVECT4, //!< Task Interrupt Vector 4
CLA_MVECT_5 = CLA_O_MVECT5, //!< Task Interrupt Vector 5
CLA_MVECT_6 = CLA_O_MVECT6, //!< Task Interrupt Vector 6
CLA_MVECT_7 = CLA_O_MVECT7, //!< Task Interrupt Vector 7
CLA_MVECT_8 = CLA_O_MVECT8 //!< Task Interrupt Vector 8
} CLA_MVECTNumber;
//*****************************************************************************
//
//! Values that can be passed to CLA_setTriggerSource() as the \e trigger
//! parameter.
//
//*****************************************************************************
typedef enum
{
CLA_TRIGGER_SOFTWARE = 0U, //!< CLA Task Trigger Source is Software
CLA_TRIGGER_ADCA1 = 1U, //!< CLA Task Trigger Source is ADCA1
CLA_TRIGGER_ADCA2 = 2U, //!< CLA Task Trigger Source is ADCA2
CLA_TRIGGER_ADCA3 = 3U, //!< CLA Task Trigger Source is ADCA3
CLA_TRIGGER_ADCA4 = 4U, //!< CLA Task Trigger Source is ADCA4
CLA_TRIGGER_ADCAEVT = 5U, //!< CLA Task Trigger Source is ADCAEVT
CLA_TRIGGER_ADCB1 = 6U, //!< CLA Task Trigger Source is ADCB1
CLA_TRIGGER_ADCB2 = 7U, //!< CLA Task Trigger Source is ADCB2
CLA_TRIGGER_ADCB3 = 8U, //!< CLA Task Trigger Source is ADCB3
CLA_TRIGGER_ADCB4 = 9U, //!< CLA Task Trigger Source is ADCB4
CLA_TRIGGER_ADCBEVT = 10U, //!< CLA Task Trigger Source is ADCBEVT
CLA_TRIGGER_ADCC1 = 11U, //!< CLA Task Trigger Source is ADCC1
CLA_TRIGGER_ADCC2 = 12U, //!< CLA Task Trigger Source is ADCC2
CLA_TRIGGER_ADCC3 = 13U, //!< CLA Task Trigger Source is ADCC3
CLA_TRIGGER_ADCC4 = 14U, //!< CLA Task Trigger Source is ADCC4
CLA_TRIGGER_ADCCEVT = 15U, //!< CLA Task Trigger Source is ADCCEVT
CLA_TRIGGER_ADCD1 = 16U, //!< CLA Task Trigger Source is ADCD1
CLA_TRIGGER_ADCD2 = 17U, //!< CLA Task Trigger Source is ADCD2
CLA_TRIGGER_ADCD3 = 18U, //!< CLA Task Trigger Source is ADCD3
CLA_TRIGGER_ADCD4 = 19U, //!< CLA Task Trigger Source is ADCD4
CLA_TRIGGER_ADCDEVT = 20U, //!< CLA Task Trigger Source is ADCDEVT
CLA_TRIGGER_XINT1 = 29U, //!< CLA Task Trigger Source is XINT1
CLA_TRIGGER_XINT2 = 30U, //!< CLA Task Trigger Source is XINT2
CLA_TRIGGER_XINT3 = 31U, //!< CLA Task Trigger Source is XINT3
CLA_TRIGGER_XINT4 = 32U, //!< CLA Task Trigger Source is XINT4
CLA_TRIGGER_XINT5 = 33U, //!< CLA Task Trigger Source is XINT5
CLA_TRIGGER_EPWM1INT = 36U, //!< CLA Task Trigger Source is EPWM1INT
CLA_TRIGGER_EPWM2INT = 37U, //!< CLA Task Trigger Source is EPWM2INT
CLA_TRIGGER_EPWM3INT = 38U, //!< CLA Task Trigger Source is EPWM3INT
CLA_TRIGGER_EPWM4INT = 39U, //!< CLA Task Trigger Source is EPWM4INT
CLA_TRIGGER_EPWM5INT = 40U, //!< CLA Task Trigger Source is EPWM5INT
CLA_TRIGGER_EPWM6INT = 41U, //!< CLA Task Trigger Source is EPWM6INT
CLA_TRIGGER_EPWM7INT = 42U, //!< CLA Task Trigger Source is EPWM7INT
CLA_TRIGGER_EPWM8INT = 43U, //!< CLA Task Trigger Source is EPWM8INT
CLA_TRIGGER_EPWM9INT = 44U, //!< CLA Task Trigger Source is EPWM9INT
CLA_TRIGGER_EPWM10INT = 45U, //!< CLA Task Trigger Source is EPWM10INT
CLA_TRIGGER_EPWM11INT = 46U, //!< CLA Task Trigger Source is EPWM11INT
CLA_TRIGGER_EPWM12INT = 47U, //!< CLA Task Trigger Source is EPWM12INT
CLA_TRIGGER_TINT0 = 68U, //!< CLA Task Trigger Source is TINT0
CLA_TRIGGER_TINT1 = 69U, //!< CLA Task Trigger Source is TINT1
CLA_TRIGGER_TINT2 = 70U, //!< CLA Task Trigger Source is TINT2
CLA_TRIGGER_MXINTA = 71U, //!< CLA Task Trigger Source is MXINTA
CLA_TRIGGER_MRINTA = 72U, //!< CLA Task Trigger Source is MRINTA
CLA_TRIGGER_MXINTB = 73U, //!< CLA Task Trigger Source is MXINTB
CLA_TRIGGER_MRINTB = 74U, //!< CLA Task Trigger Source is MRINTB
CLA_TRIGGER_ECAP1INT = 75U, //!< CLA Task Trigger Source is ECAP1INT
CLA_TRIGGER_ECAP2INT = 76U, //!< CLA Task Trigger Source is ECAP2INT
CLA_TRIGGER_ECAP3INT = 77U, //!< CLA Task Trigger Source is ECAP3INT
CLA_TRIGGER_ECAP4INT = 78U, //!< CLA Task Trigger Source is ECAP4INT
CLA_TRIGGER_ECAP5INT = 79U, //!< CLA Task Trigger Source is ECAP5INT
CLA_TRIGGER_ECAP6INT = 80U, //!< CLA Task Trigger Source is ECAP6INT
CLA_TRIGGER_EQEP1INT = 83U, //!< CLA Task Trigger Source is EQEP1INT
CLA_TRIGGER_EQEP2INT = 84U, //!< CLA Task Trigger Source is EQEP2INT
CLA_TRIGGER_EQEP3INT = 85U, //!< CLA Task Trigger Source is EQEP3INT
CLA_TRIGGER_SDFM1INT = 95U, //!< CLA Task Trigger Source is SDFM1INT
CLA_TRIGGER_SDFM2INT = 96U, //!< CLA Task Trigger Source is SDFM2INT
CLA_TRIGGER_UPP1INT = 107U, //!< CLA Task Trigger Source is UPP1INT
CLA_TRIGGER_SPITXAINT = 109U, //!< CLA Task Trigger Source is SPITXAINT
CLA_TRIGGER_SPIRXAINT = 110U, //!< CLA Task Trigger Source is SPIRXAINT
CLA_TRIGGER_SPITXBINT = 111U, //!< CLA Task Trigger Source is SPITXBINT
CLA_TRIGGER_SPIRXBINT = 112U, //!< CLA Task Trigger Source is SPIRXBINT
CLA_TRIGGER_SPITXCINT = 113U, //!< CLA Task Trigger Source is SPITXCINT
CLA_TRIGGER_SPIRXCINT = 114U, //!< CLA Task Trigger Source is SPIRXCINT
CLA_TRIGGER_CLB1INT = 127, //!< CLA Task Trigger Source is CLB1INT
CLA_TRIGGER_CLB2INT = 128, //!< CLA Task Trigger Source is CLB2INT
CLA_TRIGGER_CLB3INT = 129, //!< CLA Task Trigger Source is CLB3INT
CLA_TRIGGER_CLB4INT = 130, //!< CLA Task Trigger Source is CLB4INT
} CLA_Trigger;
#endif // __TMS320C28XX__
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks a CLA base address.
//!
//! \param base is the base address of the CLA controller.
//!
//! This function determines if a CLA controller base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
#ifdef DEBUG
static inline bool
CLA_isBaseValid(uint32_t base)
{
return(base == CLA1_BASE);
}
#endif
#ifdef __TMS320C28XX__ // These functions are only accessible from the C28x
//*****************************************************************************
//
//! Map CLA Task Interrupt Vector
//!
//! \param base is the base address of the CLA controller.
//! \param claIntVect is CLA interrupt vector (MVECT1 to MVECT8)
//! the value of claIntVect can be any of the following:
//! - \b CLA_MVECT_1 - Task Interrupt Vector 1
//! - \b CLA_MVECT_2 - Task Interrupt Vector 2
//! - \b CLA_MVECT_3 - Task Interrupt Vector 3
//! - \b CLA_MVECT_4 - Task Interrupt Vector 4
//! - \b CLA_MVECT_5 - Task Interrupt Vector 5
//! - \b CLA_MVECT_6 - Task Interrupt Vector 6
//! - \b CLA_MVECT_7 - Task Interrupt Vector 7
//! - \b CLA_MVECT_8 - Task Interrupt Vector 8
//! \param claTaskAddr is the start address of the code for task
//!
//! Each CLA Task (1 to 8) has its own MVECTx register. When a task is
//! triggered, the CLA loads the MVECTx register of the task in question
//! to the MPC (CLA program counter) and begins execution from that point.
//! The CLA has a 16-bit address bus, and can therefore, access the lower
//! 64 KW space. The MVECTx registers take an address anywhere in this space.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_mapTaskVector(uint32_t base, CLA_MVECTNumber claIntVect,
uint16_t claTaskAddr)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Modify protected register
//
EALLOW;
HWREGH(base + (uint16_t)claIntVect) = claTaskAddr;
EDIS;
}
//*****************************************************************************
//
//! Hard Reset
//!
//! \param base is the base address of the CLA controller.
//!
//! This function will cause a hard reset of the CLA and set all CLA registers
//! to their default state.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_performHardReset(uint32_t base)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Modify protected register
//
EALLOW;
//
// Hard reset of the CLA
//
HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_HARDRESET;
EDIS;
//
// Wait for few cycles till the reset is complete
//
NOP;
NOP;
NOP;
}
//*****************************************************************************
//
//! Soft Reset
//!
//! \param base is the base address of the CLA controller.
//!
//! This function will cause a soft reset of the CLA. This will stop the
//! current task, clear the MIRUN flag and clear all bits in the MIER register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_performSoftReset(uint32_t base)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Modify protected register
//
EALLOW;
//
// Soft reset of the CLA
//
HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_SOFTRESET;
EDIS;
//
// Wait for few cycles till the reset is complete
//
NOP;
NOP;
NOP;
}
//*****************************************************************************
//
//! IACK enable
//!
//! \param base is the base address of the CLA controller.
//!
//! This function enables the main CPU to use the IACK #16bit instruction to
//! set MIFR bits in the same manner as writing to the MIFRC register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_enableIACK(uint32_t base)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Modify protected register
//
EALLOW;
//
// Enable the main CPU to use the IACK #16bit instruction
//
HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_IACKE;
EDIS;
}
//*****************************************************************************
//
//! IACK disable
//!
//! \param base is the base address of the CLA controller.
//!
//! This function disables the main CPU to use the IACK #16bit instruction to
//! set MIFR bits in the same manner as writing to the MIFRC register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_disableIACK(uint32_t base)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Modify protected register
//
EALLOW;
//
// Enable the main CPU to use the IACK #16bit instruction
//
HWREGH(base + CLA_O_MCTL) &= ~CLA_MCTL_IACKE;
EDIS;
}
//*****************************************************************************
//
//! Query task N to see if it is flagged and pending execution
//!
//! \param base is the base address of the CLA controller.
//! \param taskNumber is the number of the task CLA_TASK_N where N is a number
//! from 1 to 8. Do not use CLA_TASKFLAG_ALL.
//!
//! This function gets the status of each bit in the interrupt flag register
//! corresponds to a CLA task. The corresponding bit is automatically set
//! when the task is triggered (either from a peripheral, through software, or
//! through the MIFRC register). The bit gets cleared when the CLA starts to
//! execute the flagged task.
//!
//! \return \b True if the queried task has been triggered but pending
//! execution.
//
//*****************************************************************************
static inline bool
CLA_getPendingTaskFlag(uint32_t base, CLA_TaskNumber taskNumber)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Read the run status register and return the appropriate value.
//
return(((HWREGH(base + CLA_O_MIFR) >> (uint16_t)taskNumber) & 1U) != 0U);
}
//*****************************************************************************
//
//! Get status of All Task Interrupt Flag
//!
//! \param base is the base address of the CLA controller.
//!
//! This function gets the value of the interrupt flag register (MIFR)
//!
//! \return the value of Interrupt Flag Register (MIFR)
//
//*****************************************************************************
static inline uint16_t
CLA_getAllPendingTaskFlags(uint32_t base)
{
uint16_t status;
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Just return the Interrupt Flag Register (MIFR) since that is what was
// requested.
//
status = HWREGH(base + CLA_O_MIFR);
//
// Return the Interrupt Flag Register value
//
return(status);
}
//*****************************************************************************
//
//! Get status of Task n Interrupt Overflow Flag
//!
//! \param base is the base address of the CLA controller.
//! \param taskNumber is the number of the task CLA_TASK_N where N is a number
//! from 1 to 8. Do not use CLA_TASKFLAG_ALL.
//!
//! This function gets the status of each bit in the overflow flag register
//! corresponds to a CLA task, This bit is set when an interrupt overflow event
//! has occurred for the specific task.
//!
//! \return True if any of task interrupt overflow has occurred.
//
//*****************************************************************************
static inline bool
CLA_getTaskOverflowFlag(uint32_t base, CLA_TaskNumber taskNumber)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Read the run status register and return the appropriate value.
//
return(((HWREGH(base + CLA_O_MIOVF) >> (uint16_t)taskNumber) & 1U) != 0U);
}
//*****************************************************************************
//
//! Get status of All Task Interrupt Overflow Flag
//!
//! \param base is the base address of the CLA controller.
//!
//! This function gets the value of the Interrupt Overflow Flag Register
//!
//! \return the value of Interrupt Overflow Flag Register(MIOVF)
//
//*****************************************************************************
static inline uint16_t
CLA_getAllTaskOverflowFlags(uint32_t base)
{
uint16_t status;
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Just return Interrupt Overflow Flag Register(MIOVF) since that is what
// was requested.
//
status = HWREGH(base + CLA_O_MIOVF);
//
// Return the Interrupt Overflow Flag Register
//
return(status);
}
//*****************************************************************************
//
//! Clear the task interrupt flag
//!
//! \param base is the base address of the CLA controller.
//! \param taskFlags is the bitwise OR of the tasks' flags to be cleared
//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL
//! to clear all flags.
//!
//! This function is used to manually clear bits in the interrupt
//! flag (MIFR) register
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_clearTaskFlags(uint32_t base, uint16_t taskFlags)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
//Modify protected register
//
EALLOW;
//
// Clear the task interrupt flag
//
HWREGH(base + CLA_O_MICLR) |= taskFlags;
EDIS;
}
//*****************************************************************************
//
//! Force a CLA Task
//!
//! \param base is the base address of the CLA controller.
//! \param taskFlags is the bitwise OR of the tasks' flags to be forced
//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL
//! to force all tasks.
//!
//! This function forces a task through software.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_forceTasks(uint32_t base, uint16_t taskFlags)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Modify protected register
//
EALLOW;
//
// Force the task interrupt.
//
HWREGH(base + CLA_O_MIFRC) |= taskFlags;
EDIS;
}
//*****************************************************************************
//
//! Enable CLA task(s)
//!
//! \param base is the base address of the CLA controller.
//! \param taskFlags is the bitwise OR of the tasks' flags to be enabled
//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL
//! to enable all tasks
//!
//! This function allows an incoming interrupt or main CPU software to
//! start the corresponding CLA task.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_enableTasks(uint32_t base, uint16_t taskFlags)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Modify protected register
//
EALLOW;
//
// Enable CLA task
//
HWREGH(base + CLA_O_MIER) |= taskFlags;
EDIS;
}
//*****************************************************************************
//
//! Disable CLA task interrupt
//!
//! \param base is the base address of the CLA controller.
//! \param taskFlags is the bitwise OR of the tasks' flags to be disabled
//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL
//! to disable all tasks
//!
//! This function disables CLA task interrupt by setting the MIER register bit
//! to 0, while the corresponding task is executing this will have no effect
//! on the task. The task will continue to run until it hits the MSTOP
//! instruction.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_disableTasks(uint32_t base, uint16_t taskFlags)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Modify protected register
//
EALLOW;
//
// Disable CLA task interrupt
//
HWREGH(base + CLA_O_MIER) &= ~taskFlags;
EDIS;
}
//*****************************************************************************
//
//! Get the value of a task run status
//!
//! \param base is the base address of the CLA controller.
//! \param taskNumber is the number of the task CLA_TASK_N where N is a number
//! from 1 to 8. Do not use CLA_TASKFLAG_ALL.
//!
//! This function gets the status of each bit in the Interrupt Run Status
//! Register which indicates whether the task is currently executing
//!
//! \return True if the task is executing.
//
//*****************************************************************************
static inline bool
CLA_getTaskRunStatus(uint32_t base, CLA_TaskNumber taskNumber)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Read the run status register and return the appropriate value.
//
return(((HWREGH(base + CLA_O_MIRUN) >> (uint16_t)taskNumber) & 1U) != 0U);
}
//*****************************************************************************
//
//! Get the value of all task run status
//!
//! \param base is the base address of the CLA controller.
//!
//! This function indicates which task is currently executing.
//!
//! \return the value of Interrupt Run Status Register (MIRUN)
//
//*****************************************************************************
static inline uint16_t
CLA_getAllTaskRunStatus(uint32_t base)
{
uint16_t status;
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Just return the Interrupt Run Status Register since that is what was
// requested.
//
status = HWREGH(base + CLA_O_MIRUN);
//
// Return the Interrupt Run Status Register (MIRUN)
//
return(status);
}
#endif // #ifdef __TMS320C28XX__
//
// These functions are accessible only from the CLA (Type - 1/2)
//
#if defined(__TMS320C28XX_CLA1__) || defined(__TMS320C28XX_CLA2__)
//*****************************************************************************
//
//! Enable the Software Interrupt for a given CLA Task
//!
//! \param base is the base address of the CLA controller.
//! \param taskFlags is the bitwise OR of the tasks for which software
//! interrupts are to be enabled, CLA_TASKFLAG_N where N is the task number
//! from 1 to 8, or CLA_TASKFLAG_ALL to enable software interrupts of all tasks
//!
//! This function enables the Software Interrupt for a single, or set of, CLA
//! task(s). It does this by writing a 1 to the task's bit in the
//! CLA1SOFTINTEN register. By setting a task's SOFTINT bit, you disable its
//! ability to generate an end-of-task interrupt
//! For example, if we enable Task 2's SOFTINT bit, we disable its ability to
//! generate an end-of-task interrupt, but now any running CLA task has the
//! ability to force task 2's interrupt (through the CLA1INTFRC register) to
//! the main CPU. This interrupt will be handled by the End-of-Task 2 interrupt
//! handler even though the interrupt was not caused by Task 2 running to
//! completion. This allows programmers to generate interrupts while a control
//! task is running.
//!
//! \note
//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA.
//! -# Enabling a given task's software interrupt enable bit disables that
//! task's ability to generate an End-of-Task interrupt to the main CPU,
//! however, should another task force its interrupt (through the CLA1INTFRC
//! register), it will be handled by that task's End-of-Task Interrupt Handler.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_enableSoftwareInterrupt(uint32_t base, uint16_t taskFlags)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Modify protected register
//
__meallow();
//
// Enable Software Interrupt
//
HWREGH(base + CLA_O_SOFTINTEN) |= taskFlags;
__medis();
}
//*****************************************************************************
//
//! Disable the Software Interrupt for a given CLA Task
//!
//! \param base is the base address of the CLA controller.
//! \param taskFlags is the bitwise OR of the tasks for which software
//! interrupts are to be disabled, CLA_TASKFLAG_N where N is the task number
//! from 1 to 8, or CLA_TASKFLAG_ALL to disable software interrupts of all
//! tasks
//!
//! This function disables the Software Interrupt for a single, or set of, CLA
//! task(s). It does this by writing a 0 to the task's bit in the
//! CLA1SOFTINTEN register.
//!
//! \note
//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA.
//! -# Disabling a given task's software interrupt ability allows that
//! task to generate an End-of-Task interrupt to the main CPU.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_disableSoftwareInterrupt(uint32_t base, uint16_t taskFlags)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Modify protected register
//
__meallow();
//
// Enable Software Interrupt
//
HWREGH(base + CLA_O_SOFTINTEN) &= ~taskFlags;
__medis();
}
//*****************************************************************************
//
//! Force a particular Task's Software Interrupt
//!
//! \param base is the base address of the CLA controller.
//! \param taskFlags is the bitwise OR of the task's whose software
//! interrupts are to be forced, CLA_TASKFLAG_N where N is the task number
//! from 1 to 8, or CLA_TASKFLAG_ALL to force software interrupts for all tasks
//!
//! This function forces the Software Interrupt for a single, or set of, CLA
//! task(s). It does this by writing a 1 to the task's bit in the
//! CLA1INTFRC register.
//! For example, if we enable Task 2's SOFTINT bit, we disable its ability to
//! generate an end-of-task interrupt, but now any running CLA task has the
//! ability to force task 2's interrupt (through the CLA1INTFRC register) to
//! the main CPU. This interrupt will be handled by the End-of-Task 2 interrupt
//! handler even though the interrupt was not caused by Task 2 running to
//! completion. This allows programmers to generate interrupts while a control
//! task is running.
//!
//! \note
//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA.
//! -# Enabling a given task's software interrupt enable bit disables that
//! task's ability to generate an End-of-Task interrupt to the main CPU,
//! however, should another task force its interrupt (through the CLA1INTFRC
//! register), it will be handled by that task's End-of-Task Interrupt Handler.
//! -# This function will set the INTFRC bit for a task, but does not check
//! that its SOFTINT bit is set. It falls to the user to ensure that software
//! interrupt for a given task is enabled before it can be forced.
//!
//! \return None.
//
//*****************************************************************************
static inline void
CLA_forceSoftwareInterrupt(uint32_t base, uint16_t taskFlags)
{
//
// Check the arguments.
//
ASSERT(CLA_isBaseValid(base));
//
// Modify protected register
//
__meallow();
//
// Force Software Interrupt
//
HWREGH(base + CLA_O_SOFTINTFRC) |= taskFlags;
__medis();
}
#endif // #if defined(__TMS320C28XX_CLA1__) || defined(__TMS320C28XX_CLA2__)
//
// These functions can only be called from the C28x
//
#ifdef __TMS320C28XX__
//*****************************************************************************
//
//! Configures CLA task triggers.
//!
//! \param taskNumber is the number of the task CLA_TASK_N where N is a number
//! from 1 to 8.
//! \param trigger is the trigger source to be assigned to the selected task.
//!
//! This function configures the trigger source of a CLA task. The
//! \e taskNumber parameter indicates which task is being configured, and the
//! \e trigger parameter is the interrupt source from a specific peripheral
//! interrupt (or software) that will trigger the task.
//!
//! \return None.
//
//*****************************************************************************
extern void
CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger);
#endif //#ifdef __TMS320C28XX__
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // CLA_H
28379d_P_SFRA/device/driverlib/clb.c
+145
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@@ -0,0 +1,145 @@
//###########################################################################
//
// FILE: clb.c
//
// TITLE: C28x CLB driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "clb.h"
//*****************************************************************************
//
// CLB_configCounterLoadMatch
//
//*****************************************************************************
void CLB_configCounterLoadMatch(uint32_t base, CLB_Counters counterID,
uint32_t load, uint32_t match1, uint32_t match2)
{
ASSERT(CLB_isBaseValid(base));
EALLOW;
switch(counterID)
{
case CLB_CTR0:
CLB_writeInterface(base, CLB_ADDR_COUNTER_0_LOAD, load);
CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH1, match1);
CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH2, match2);
break;
case CLB_CTR1:
CLB_writeInterface(base, CLB_ADDR_COUNTER_1_LOAD, load);
CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH1, match1);
CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH2, match2);
break;
case CLB_CTR2:
CLB_writeInterface(base, CLB_ADDR_COUNTER_2_LOAD, load);
CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH1, match1);
CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH2, match2);
break;
default:
//
// Invalid counterID value
//
break;
}
EDIS;
}
//*****************************************************************************
//
// CLB_clearFIFOs
//
//*****************************************************************************
void CLB_clearFIFOs(uint32_t base)
{
uint16_t i;
ASSERT(CLB_isBaseValid(base));
for(i = 0U; i < CLB_FIFO_SIZE; i++)
{
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(i)) = 0U;
}
HWREG(base + CLB_LOGICCTL + CLB_O_BUF_PTR) = 0U;
}
//*****************************************************************************
//
// CLB_writeFIFOs
//
//*****************************************************************************
void CLB_writeFIFOs(uint32_t base , const uint32_t pullData[])
{
ASSERT(CLB_isBaseValid(base));
//
// Clear the FIFO and pointer
//
CLB_clearFIFOs(base);
//
// Write data into the FIFO.
//
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(0U)) = pullData[0U];
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(1U)) = pullData[1U];
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(2U)) = pullData[2U];
HWREG(base + CLB_DATAEXCH + CLB_O_PULL(3U)) = pullData[3U];
}
//*****************************************************************************
//
// CLB_readFIFOs
//
//*****************************************************************************
void CLB_readFIFOs(uint32_t base , uint32_t pushData[])
{
ASSERT(CLB_isBaseValid(base));
//
// Read data from the FIFO.
//
pushData[0U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(0U)) ;
pushData[1U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(1U)) ;
pushData[2U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(2U)) ;
pushData[3U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(3U)) ;
}
28379d_P_SFRA/device/driverlib/clb.h
+1290
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28379d_P_SFRA/device/driverlib/cmpss.c
+223
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@@ -0,0 +1,223 @@
//###########################################################################
//
// FILE: cmpss.c
//
// TITLE: C28x CMPSS driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "cmpss.h"
//*****************************************************************************
//
// CMPSS_configFilterHigh
//
//*****************************************************************************
void
CMPSS_configFilterHigh(uint32_t base, uint16_t samplePrescale,
uint16_t sampleWindow, uint16_t threshold)
{
uint16_t regValue;
//
// Check the arguments.
//
ASSERT(CMPSS_isBaseValid(base));
ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U));
//
// Shift the sample window and threshold values into the correct positions
// and write them to the appropriate register.
//
regValue = ((sampleWindow - 1U) << CMPSS_CTRIPHFILCTL_SAMPWIN_S) |
((threshold - 1U) << CMPSS_CTRIPHFILCTL_THRESH_S);
EALLOW;
HWREGH(base + CMPSS_O_CTRIPHFILCTL) =
(HWREGH(base + CMPSS_O_CTRIPHFILCTL) &
~(CMPSS_CTRIPHFILCTL_SAMPWIN_M | CMPSS_CTRIPHFILCTL_THRESH_M)) |
regValue;
//
// Set the filter sample clock prescale for the high comparator.
//
HWREGH(base + CMPSS_O_CTRIPHFILCLKCTL) = samplePrescale;
EDIS;
}
//*****************************************************************************
//
// CMPSS_configFilterLow
//
//*****************************************************************************
void
CMPSS_configFilterLow(uint32_t base, uint16_t samplePrescale,
uint16_t sampleWindow, uint16_t threshold)
{
uint16_t regValue;
//
// Check the arguments.
//
ASSERT(CMPSS_isBaseValid(base));
ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U));
//
// Shift the sample window and threshold values into the correct positions
// and write them to the appropriate register.
//
regValue = ((sampleWindow - 1U) << CMPSS_CTRIPLFILCTL_SAMPWIN_S) |
((threshold - 1U) << CMPSS_CTRIPLFILCTL_THRESH_S);
EALLOW;
HWREGH(base + CMPSS_O_CTRIPLFILCTL) =
(HWREGH(base + CMPSS_O_CTRIPLFILCTL) &
~(CMPSS_CTRIPLFILCTL_SAMPWIN_M | CMPSS_CTRIPLFILCTL_THRESH_M)) |
regValue;
//
// Set the filter sample clock prescale for the low comparator.
//
HWREGH(base + CMPSS_O_CTRIPLFILCLKCTL) = samplePrescale;
EDIS;
}
//*****************************************************************************
//
// CMPSS_configLatchOnPWMSYNC
//
//*****************************************************************************
void
CMPSS_configLatchOnPWMSYNC(uint32_t base, bool highEnable, bool lowEnable)
{
//
// Check the arguments.
//
ASSERT(CMPSS_isBaseValid(base));
//
// If the highEnable is true, set the bit that will enable PWMSYNC to reset
// the high comparator digital filter latch. If not, clear the bit.
//
EALLOW;
if(highEnable)
{
HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HSYNCCLREN;
}
else
{
HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_HSYNCCLREN;
}
//
// If the lowEnable is true, set the bit that will enable PWMSYNC to reset
// the low comparator digital filter latch. If not, clear the bit.
//
if(lowEnable)
{
HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LSYNCCLREN;
}
else
{
HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_LSYNCCLREN;
}
EDIS;
}
//*****************************************************************************
//
// CMPSS_configRamp
//
//*****************************************************************************
void
CMPSS_configRamp(uint32_t base, uint16_t maxRampVal, uint16_t decrementVal,
uint16_t delayVal, uint16_t pwmSyncSrc, bool useRampValShdw)
{
//
// Check the arguments.
//
ASSERT(CMPSS_isBaseValid(base));
ASSERT(delayVal <= CMPSS_RAMPDLYS_DELAY_M);
ASSERT((pwmSyncSrc >= 1U) && (pwmSyncSrc <= 12U));
EALLOW;
//
// Write the ramp generator source to the register
//
HWREGH(base + CMPSS_O_COMPDACCTL) =
(HWREGH(base + CMPSS_O_COMPDACCTL) &
~CMPSS_COMPDACCTL_RAMPSOURCE_M) |
((uint16_t)(pwmSyncSrc - 1U) << CMPSS_COMPDACCTL_RAMPSOURCE_S);
//
// Set or clear the bit that determines from where the max ramp value
// should be loaded.
//
if(useRampValShdw)
{
HWREGH(base + CMPSS_O_COMPDACCTL) |= CMPSS_COMPDACCTL_RAMPLOADSEL;
}
else
{
HWREGH(base + CMPSS_O_COMPDACCTL) &= ~CMPSS_COMPDACCTL_RAMPLOADSEL;
}
EDIS;
//
// Write the maximum ramp value to the shadow register.
//
HWREGH(base + CMPSS_O_RAMPMAXREFS) = maxRampVal;
//
// Write the ramp decrement value to the shadow register.
//
HWREGH(base + CMPSS_O_RAMPDECVALS) = decrementVal;
//
// Write the ramp delay value to the shadow register.
//
HWREGH(base + CMPSS_O_RAMPDLYS) = delayVal;
}
28379d_P_SFRA/device/driverlib/cmpss.h
+1325
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28379d_P_SFRA/device/driverlib/cpu.h
+172
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@@ -0,0 +1,172 @@
//###########################################################################
//
// FILE: cpu.h
//
// TITLE: Useful C28x CPU defines.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef CPU_H
#define CPU_H
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#include "stdint.h"
//
// External reference to the interrupt flag register (IFR) register
//
#ifndef __TMS320C28XX_CLA__
extern __cregister volatile uint16_t IFR;
#endif
//
// External reference to the interrupt enable register (IER) register
//
#ifndef __TMS320C28XX_CLA__
extern __cregister volatile uint16_t IER;
#endif
//
// Define to enable interrupts
//
#ifndef EINT
#define EINT __asm(" clrc INTM")
#endif
//
// Define to disable interrupts
//
#ifndef DINT
#define DINT __asm(" setc INTM")
#endif
//
// Define to enable debug events
//
#ifndef ERTM
#define ERTM __asm(" clrc DBGM")
#endif
//
// Define to disable debug events
//
#ifndef DRTM
#define DRTM __asm(" setc DBGM")
#endif
//
// Define to allow writes to protected registers
//
#ifndef EALLOW
#ifndef __TMS320C28XX_CLA__
#define EALLOW __eallow()
#else
#define EALLOW __meallow()
#endif // __TMS320C28XX_CLA__
#endif // EALLOW
//
// Define to disable writes to protected registers
//
#ifndef EDIS
#ifndef __TMS320C28XX_CLA__
#define EDIS __edis()
#else
#define EDIS __medis()
#endif // __TMS320C28XX_CLA__
#endif // EDIS
//
// Define for emulation stop
//
#ifndef ESTOP0
#define ESTOP0 __asm(" ESTOP0")
#endif
//
// Define for emulation stop
//
#ifndef ESTOP1
#define ESTOP1 __asm(" ESTOP1")
#endif
//
// Define for no operation
//
#ifndef NOP
#define NOP __asm(" NOP")
#endif
//
// Define for putting processor into a low-power mode
//
#ifndef _DUAL_HEADERS
#ifndef IDLE
#define IDLE __asm(" IDLE")
#endif
#else
#define IDLE_ASM __asm(" IDLE");
#endif
//*****************************************************************************
//
// Extern compiler intrinsic prototypes. See compiler User's Guide for details.
//
//*****************************************************************************
extern void __eallow(void);
extern void __edis(void);
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // CPU_H
28379d_P_SFRA/device/driverlib/cputimer.c
+61
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@@ -0,0 +1,61 @@
//#############################################################################
//
// FILE: cputimer.c
//
// TITLE: C28x CPU timer Driver
//
//#############################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
#include "cputimer.h"
//*****************************************************************************
//
// CPUTimer_setEmulationMode
//
//*****************************************************************************
void CPUTimer_setEmulationMode(uint32_t base, CPUTimer_EmulationMode mode)
{
ASSERT(CPUTimer_isBaseValid(base));
//
// Write to FREE_SOFT bits of register TCR
//
HWREGH(base + CPUTIMER_O_TCR) =
(HWREGH(base + CPUTIMER_O_TCR) &
~(CPUTIMER_TCR_FREE | CPUTIMER_TCR_SOFT)) |
(uint16_t)mode;
}
28379d_P_SFRA/device/driverlib/cputimer.h
+509
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@@ -0,0 +1,509 @@
//#############################################################################
//
// FILE: cputimer.h
//
// TITLE: C28x CPU timer Driver
//
//#############################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
#ifndef CPUTIMER_H
#define CPUTIMER_H
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __TMS320C28XX__
//*****************************************************************************
//
//! \addtogroup cputimer_api CPUTimer
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_cputimer.h"
#include "debug.h"
#include "sysctl.h"
//*****************************************************************************
//
// Defines for the API.
//
//*****************************************************************************
//*****************************************************************************
//
//! Values that can be passed to CPUTimer_setEmulationMode() as the
//! \e mode parameter.
//
//****************************************************************************
typedef enum
{
//! Denotes that the timer will stop after the next decrement
CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT = 0x0000,
//! Denotes that the timer will stop when it reaches zero
CPUTIMER_EMULATIONMODE_STOPATZERO = 0x0400,
//! Denotes that the timer will run free
CPUTIMER_EMULATIONMODE_RUNFREE = 0x0800
}CPUTimer_EmulationMode;
//*****************************************************************************
//
//! The following are values that can be passed to
//! CPUTimer_selectClockSource() as the \e source parameter.
//
//*****************************************************************************
typedef enum
{
//! System Clock Source
CPUTIMER_CLOCK_SOURCE_SYS = 0x0,
//! Internal Oscillator 1 Clock Source
CPUTIMER_CLOCK_SOURCE_INTOSC1 = 0x1,
//! Internal Oscillator 2 Clock Source
CPUTIMER_CLOCK_SOURCE_INTOSC2 = 0x2,
//! External Clock Source
CPUTIMER_CLOCK_SOURCE_XTAL = 0x3,
//! Auxiliary PLL Clock Source
CPUTIMER_CLOCK_SOURCE_AUX = 0x6
} CPUTimer_ClockSource;
//*****************************************************************************
//
//! The following are values that can be passed to
//! CPUTimer_selectClockSource() as the \e prescaler parameter.
//
//*****************************************************************************
typedef enum
{
CPUTIMER_CLOCK_PRESCALER_1 = 0, //!< Prescaler value of / 1
CPUTIMER_CLOCK_PRESCALER_2 = 1, //!< Prescaler value of / 2
CPUTIMER_CLOCK_PRESCALER_4 = 2, //!< Prescaler value of / 4
CPUTIMER_CLOCK_PRESCALER_8 = 3, //!< Prescaler value of / 8
CPUTIMER_CLOCK_PRESCALER_16 = 4 //!< Prescaler value of / 16
} CPUTimer_Prescaler;
//*****************************************************************************
//
//! \internal
//! Checks CPU timer base address.
//!
//! \param base specifies the Timer module base address.
//!
//! This function determines if a CPU timer module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
#ifdef DEBUG
static inline bool CPUTimer_isBaseValid(uint32_t base)
{
return((base == CPUTIMER0_BASE) || (base == CPUTIMER1_BASE) ||
(base == CPUTIMER2_BASE));
}
#endif
//*****************************************************************************
//
//! Clears CPU timer overflow flag.
//!
//! \param base is the base address of the timer module.
//!
//! This function clears the CPU timer overflow flag.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_clearOverflowFlag(uint32_t base)
{
ASSERT(CPUTimer_isBaseValid(base));
//
// Set TIF bit of TCR register
//
HWREGH(base + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF;
}
//*****************************************************************************
//
//! Disables CPU timer interrupt.
//!
//! \param base is the base address of the timer module.
//!
//! This function disables the CPU timer interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_disableInterrupt(uint32_t base)
{
ASSERT(CPUTimer_isBaseValid(base));
//
// Clear TIE bit of TCR register
//
HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TIE;
}
//*****************************************************************************
//
//! Enables CPU timer interrupt.
//!
//! \param base is the base address of the timer module.
//!
//! This function enables the CPU timer interrupt.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_enableInterrupt(uint32_t base)
{
uint16_t tcrValue = 0;
ASSERT(CPUTimer_isBaseValid(base));
//
// Set TIE bit of TCR register
//
tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF);
HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TIE;
}
//*****************************************************************************
//
//! Reloads CPU timer counter.
//!
//! \param base is the base address of the timer module.
//!
//! This function reloads the CPU timer counter with the values contained in
//! the CPU timer period register.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_reloadTimerCounter(uint32_t base)
{
uint16_t tcrValue = 0;
ASSERT(CPUTimer_isBaseValid(base));
//
// Set TRB bit of register TCR
//
tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF);
HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TRB;
}
//*****************************************************************************
//
//! Stops CPU timer.
//!
//! \param base is the base address of the timer module.
//!
//! This function stops the CPU timer.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_stopTimer(uint32_t base)
{
uint16_t tcrValue = 0;
ASSERT(CPUTimer_isBaseValid(base));
//
// Set TSS bit of register TCR
//
tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF);
HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TSS;
}
//*****************************************************************************
//
//! Starts(restarts) CPU timer.
//!
//! \param base is the base address of the timer module.
//!
//! This function starts (restarts) the CPU timer.
//!
//! \b Note: This function doesn't reset the timer counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_resumeTimer(uint32_t base)
{
ASSERT(CPUTimer_isBaseValid(base));
//
// Clear TSS bit of register TCR
//
HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS;
}
//*****************************************************************************
//
//! Starts(restarts) CPU timer.
//!
//! \param base is the base address of the timer module.
//!
//! This function starts (restarts) the CPU timer.
//!
//! \b Note: This function reloads the timer counter.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_startTimer(uint32_t base)
{
uint16_t tcrValue = 0;
ASSERT(CPUTimer_isBaseValid(base));
//
// Reload the timer counter
//
tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF);
HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TRB;
//
// Clear TSS bit of register TCR
//
HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS;
}
//*****************************************************************************
//
//! Sets CPU timer period.
//!
//! \param base is the base address of the timer module.
//! \param periodCount is the CPU timer period count.
//!
//! This function sets the CPU timer period count.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_setPeriod(uint32_t base, uint32_t periodCount)
{
ASSERT(CPUTimer_isBaseValid(base));
//
// Load the MSB period Count
//
HWREG(base + CPUTIMER_O_PRD) = periodCount;
}
//*****************************************************************************
//
//! Returns the current CPU timer counter value.
//!
//! \param base is the base address of the timer module.
//!
//! This function returns the current CPU timer counter value.
//!
//! \return Returns the current CPU timer count value.
//
//*****************************************************************************
static inline uint32_t CPUTimer_getTimerCount(uint32_t base)
{
ASSERT(CPUTimer_isBaseValid(base));
//
// Get the TIMH:TIM registers value
//
return(HWREG(base + CPUTIMER_O_TIM));
}
//*****************************************************************************
//
//! Set CPU timer pre-scaler value.
//!
//! \param base is the base address of the timer module.
//! \param prescaler is the CPU timer pre-scaler value.
//!
//! This function sets the pre-scaler value for the CPU timer. For every value
//! of (prescaler + 1), the CPU timer counter decrements by 1.
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_setPreScaler(uint32_t base, uint16_t prescaler)
{
ASSERT(CPUTimer_isBaseValid(base));
//
// Writes to TPR.TDDR and TPRH.TDDRH bits
//
HWREGH(base + CPUTIMER_O_TPRH) = prescaler >> 8U;
HWREGH(base + CPUTIMER_O_TPR) = (prescaler & CPUTIMER_TPR_TDDR_M) ;
}
//*****************************************************************************
//
//! Return the CPU timer overflow status.
//!
//! \param base is the base address of the timer module.
//!
//! This function returns the CPU timer overflow status.
//!
//! \return Returns true if the CPU timer has overflowed, false if not.
//
//*****************************************************************************
static inline bool CPUTimer_getTimerOverflowStatus(uint32_t base)
{
ASSERT(CPUTimer_isBaseValid(base));
//
// Check if TIF bits of register TCR are set
//
return(((HWREGH(base + CPUTIMER_O_TCR) & CPUTIMER_TCR_TIF) ==
CPUTIMER_TCR_TIF) ? true : false);
}
//*****************************************************************************
//
//! Select CPU Timer 2 Clock Source and Prescaler
//!
//! \param base is the base address of the timer module.
//! \param source is the clock source to use for CPU Timer 2
//! \param prescaler is the value that configures the selected clock source
//! relative to the system clock
//!
//! This function selects the specified clock source and prescaler value
//! for the CPU timer (CPU timer 2 only).
//!
//! The \e source parameter can be any one of the following:
//! - \b CPUTIMER_CLOCK_SOURCE_SYS - System Clock
//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC1 - Internal Oscillator 1 Clock
//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC2 - Internal Oscillator 2 Clock
//! - \b CPUTIMER_CLOCK_SOURCE_XTAL - External Clock
//! - \b CPUTIMER_CLOCK_SOURCE_AUX - Auxiliary PLL Clock
//!
//! The \e prescaler parameter can be any one of the following:
//! - \b CPUTIMER_CLOCK_PRESCALER_1 - Prescaler value of / 1
//! - \b CPUTIMER_CLOCK_PRESCALER_2 - Prescaler value of / 2
//! - \b CPUTIMER_CLOCK_PRESCALER_4 - Prescaler value of / 4
//! - \b CPUTIMER_CLOCK_PRESCALER_8 - Prescaler value of / 8
//! - \b CPUTIMER_CLOCK_PRESCALER_16 - Prescaler value of / 16
//!
//! \return None.
//
//*****************************************************************************
static inline void CPUTimer_selectClockSource(uint32_t base,
CPUTimer_ClockSource source,
CPUTimer_Prescaler prescaler)
{
ASSERT(base == CPUTIMER2_BASE);
//
// Set source and prescaler for CPU Timer 2
//
if(base == CPUTIMER2_BASE)
{
EALLOW;
//
// Set Clock Source
//
HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) =
(HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) &
~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | (uint16_t)source;
SYSCTL_REGWRITE_DELAY;
//
// Set Clock Prescaler
//
HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) =
(HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) &
~SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M) |
((uint16_t)prescaler <<SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_S);
EDIS;
}
SYSCTL_REGWRITE_DELAY;
}
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! Sets Emulation mode for CPU timer.
//!
//! \param base is the base address of the timer module.
//! \param mode is the emulation mode of the timer.
//!
//! This function sets the behaviour of CPU timer during emulation. Valid
//! values mode are: CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT,
//! CPUTIMER_EMULATIONMODE_STOPATZERO and CPUTIMER_EMULATIONMODE_RUNFREE.
//!
//! \return None.
//
//*****************************************************************************
extern void CPUTimer_setEmulationMode(uint32_t base,
CPUTimer_EmulationMode mode);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // #ifdef __TMS320C28XX__
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // CPUTIMER_H
28379d_P_SFRA/device/driverlib/dac.c
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//###########################################################################
//
// FILE: dac.c
//
// TITLE: C28x DAC driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "dac.h"
//*****************************************************************************
//
// DAC_tuneOffsetTrim()
//
//*****************************************************************************
void
DAC_tuneOffsetTrim(uint32_t base, float32_t referenceVoltage)
{
uint16_t oldOffsetTrim;
float32_t newOffsetTrim;
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
ASSERT(referenceVoltage > 0.0F);
//
// Get the sign-extended offset trim value
//
oldOffsetTrim = (HWREGH(base + DAC_O_TRIM) & DAC_TRIM_OFFSET_TRIM_M);
oldOffsetTrim = ((oldOffsetTrim & (uint16_t)DAC_REG_BYTE_MASK) ^
(uint16_t)0x80) - (uint16_t)0x80;
//
// Calculate new offset trim value if DAC is operating at a reference
// voltage other than 2.5v.
//
newOffsetTrim = ((float32_t)(2.5 / referenceVoltage) *
(int16_t)oldOffsetTrim);
//
// Check if the new offset trim value is valid
//
ASSERT(((int16_t)newOffsetTrim > -129) && ((int16_t)newOffsetTrim < 128));
//
// Set the new offset trim value
//
EALLOW;
HWREGH(base + DAC_O_TRIM) = (HWREGH(base + DAC_O_TRIM) &
~DAC_TRIM_OFFSET_TRIM_M) |
(int16_t)newOffsetTrim;
EDIS;
}
28379d_P_SFRA/device/driverlib/dac.h
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//###########################################################################
//
// FILE: dac.h
//
// TITLE: C28x DAC driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DAC_H
#define DAC_H
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup dac_api DAC
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_dac.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "cpu.h"
#include "debug.h"
//
// A 8-bit register mask
//
#define DAC_REG_BYTE_MASK (0xFFU) //!< Register Byte Mask
//
// Lock Key
//
#define DAC_LOCK_KEY (0xA000U) //!< DAC Lock Key
#ifndef DOXYGEN_PDF_IGNORE
//*****************************************************************************
//
// The following are defines for the reg parameter of the
// DAC_lockRegister() and DAC_isRegisterLocked() functions.
//
//*****************************************************************************
#define DAC_LOCK_CONTROL (0x1U) //!< Lock the control register
#define DAC_LOCK_SHADOW (0x2U) //!< Lock the shadow value register
#define DAC_LOCK_OUTPUT (0x4U) //!< Lock the output enable register
#endif // DOXYGEN_PDF_IGNORE
//*****************************************************************************
//
//! Values that can be passed to DAC_setReferenceVoltage() as the \e source
//! parameter.
//
//*****************************************************************************
typedef enum
{
DAC_REF_VDAC = 0, //!< VDAC reference voltage
DAC_REF_ADC_VREFHI = 1 //!< ADC VREFHI reference voltage
}DAC_ReferenceVoltage;
//*****************************************************************************
//
//! Values that can be passed to DAC_setLoadMode() as the \e mode parameter.
//
//*****************************************************************************
typedef enum
{
DAC_LOAD_SYSCLK = 0, //!< Load on next SYSCLK
DAC_LOAD_PWMSYNC = 4 //!< Load on next PWMSYNC specified by SYNCSEL
}DAC_LoadMode;
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! Checks DAC base address.
//!
//! \param base specifies the DAC module base address.
//!
//! This function determines if an DAC module base address is valid.
//!
//! \return Returns \b true if the base address is valid and \b false
//! otherwise.
//
//*****************************************************************************
#ifdef DEBUG
static inline bool
DAC_isBaseValid(uint32_t base)
{
return(
(base == DACA_BASE) ||
(base == DACB_BASE) ||
(base == DACC_BASE)
);
}
#endif
//*****************************************************************************
//
//! Get the DAC Revision value
//!
//! \param base is the DAC module base address
//!
//! This function gets the DAC revision value.
//!
//! \return Returns the DAC revision value.
//
//*****************************************************************************
static inline uint16_t
DAC_getRevision(uint32_t base)
{
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
//
// Get the revision value.
//
return(HWREGH(base + DAC_O_REV) & DAC_REV_REV_M);
}
//*****************************************************************************
//
//! Sets the DAC Reference Voltage
//!
//! \param base is the DAC module base address
//! \param source is the selected reference voltage
//!
//! This function sets the DAC reference voltage.
//!
//! The \e source parameter can have the following value:
//! - \b DAC_REF_VDAC - The VDAC reference voltage
//! - \b DAC_REF_ADC_VREFHI - The ADC VREFHI reference voltage
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_setReferenceVoltage(uint32_t base, DAC_ReferenceVoltage source)
{
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
//
// Set the reference voltage
//
EALLOW;
HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) &
~DAC_CTL_DACREFSEL) | (uint16_t)source;
EDIS;
}
//*****************************************************************************
//
//! Sets the DAC Load Mode
//!
//! \param base is the DAC module base address
//! \param mode is the selected load mode
//!
//! This function sets the DAC load mode.
//!
//! The \e mode parameter can have one of two values:
//! - \b DAC_LOAD_SYSCLK - Load on next SYSCLK
//! - \b DAC_LOAD_PWMSYNC - Load on next PWMSYNC specified by SYNCSEL
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_setLoadMode(uint32_t base, DAC_LoadMode mode)
{
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
//
// Set the load mode
//
EALLOW;
HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) &
~DAC_CTL_LOADMODE) | (uint16_t)mode;
EDIS;
}
//*****************************************************************************
//
//! Sets the DAC PWMSYNC Signal
//!
//! \param base is the DAC module base address
//! \param signal is the selected PWM signal
//!
//! This function sets the DAC PWMSYNC signal.
//!
//! The \e signal parameter must be set to a number that represents the PWM
//! signal that will be set. For instance, passing 2 into \e signal will
//! select PWM sync signal 2.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_setPWMSyncSignal(uint32_t base, uint16_t pwmSignal)
{
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
ASSERT((pwmSignal > 0U) && (pwmSignal < 17U));
//
// Set the PWM sync signal
//
EALLOW;
HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) &
~DAC_CTL_SYNCSEL_M) |
((uint16_t)(pwmSignal - 1U) <<
DAC_CTL_SYNCSEL_S);
EDIS;
}
//*****************************************************************************
//
//! Get the DAC Active Output Value
//!
//! \param base is the DAC module base address
//!
//! This function gets the DAC active output value.
//!
//! \return Returns the DAC active output value.
//
//*****************************************************************************
static inline uint16_t
DAC_getActiveValue(uint32_t base)
{
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
//
// Get the active value
//
return(HWREGH(base + DAC_O_VALA) & DAC_VALA_DACVALA_M);
}
//*****************************************************************************
//
//! Set the DAC Shadow Output Value
//!
//! \param base is the DAC module base address
//! \param value is the 12-bit code to be loaded into the active value register
//!
//! This function sets the DAC shadow output value.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_setShadowValue(uint32_t base, uint16_t value)
{
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
ASSERT(value <= DAC_VALS_DACVALS_M);
//
// Set the shadow value
//
HWREGH(base + DAC_O_VALS) = (HWREGH(base + DAC_O_VALS) &
~DAC_VALS_DACVALS_M) |
(uint16_t)(value & DAC_VALS_DACVALS_M);
}
//*****************************************************************************
//
//! Get the DAC Shadow Output Value
//!
//! \param base is the DAC module base address
//!
//! This function gets the DAC shadow output value.
//!
//! \return Returns the DAC shadow output value.
//
//*****************************************************************************
static inline uint16_t
DAC_getShadowValue(uint32_t base)
{
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
//
// Get the shadow value
//
return(HWREGH(base + DAC_O_VALS) & DAC_VALS_DACVALS_M);
}
//*****************************************************************************
//
//! Enable the DAC Output
//!
//! \param base is the DAC module base address
//!
//! This function enables the DAC output.
//!
//! \note A delay is required after enabling the DAC. Further details
//! regarding the exact delay time length can be found in the device datasheet.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_enableOutput(uint32_t base)
{
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
//
// Enable the output
//
EALLOW;
HWREGH(base + DAC_O_OUTEN) |= DAC_OUTEN_DACOUTEN;
EDIS;
}
//*****************************************************************************
//
//! Disable the DAC Output
//!
//! \param base is the DAC module base address
//!
//! This function disables the DAC output.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_disableOutput(uint32_t base)
{
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
//
// Disable the output
//
EALLOW;
HWREGH(base + DAC_O_OUTEN) &= ~DAC_OUTEN_DACOUTEN;
EDIS;
}
//*****************************************************************************
//
//! Set DAC Offset Trim
//!
//! \param base is the DAC module base address
//! \param offset is the specified value for the offset trim
//!
//! This function sets the DAC offset trim. The \e offset value should be a
//! signed number in the range of -128 to 127.
//!
//! \note The offset should not be modified unless specifically indicated by
//! TI Errata or other documentation. Modifying the offset value could cause
//! this module to operate outside of the datasheet specifications.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_setOffsetTrim(uint32_t base, int16_t offset)
{
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
ASSERT((offset > -129) && (offset < 128));
//
// Set the offset trim value
//
EALLOW;
HWREGH(base + DAC_O_TRIM) = (HWREGH(base + DAC_O_TRIM) &
~DAC_TRIM_OFFSET_TRIM_M) | (int16_t)offset;
EDIS;
}
//*****************************************************************************
//
//! Get DAC Offset Trim
//!
//! \param base is the DAC module base address
//!
//! This function gets the DAC offset trim value.
//!
//! \return None.
//
//*****************************************************************************
static inline int16_t
DAC_getOffsetTrim(uint32_t base)
{
uint16_t value;
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
//
// Get the sign-extended offset trim value
//
value = (HWREGH(base + DAC_O_TRIM) & DAC_TRIM_OFFSET_TRIM_M);
value = ((value & (uint16_t)DAC_REG_BYTE_MASK) ^ (uint16_t)0x80) -
(uint16_t)0x80;
return((int16_t)value);
}
//*****************************************************************************
//
//! Lock write-access to DAC Register
//!
//! \param base is the DAC module base address
//! \param reg is the selected DAC registers
//!
//! This function locks the write-access to the specified DAC register. Only a
//! system reset can unlock the register once locked.
//!
//! The \e reg parameter can be an ORed combination of any of the following
//! values:
//! - \b DAC_LOCK_CONTROL - Lock the DAC control register
//! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register
//! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register
//!
//! \return None.
//
//*****************************************************************************
static inline void
DAC_lockRegister(uint32_t base, uint16_t reg)
{
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
ASSERT((reg & ~(DAC_LOCK_CONTROL | DAC_LOCK_SHADOW |
DAC_LOCK_OUTPUT)) == 0U);
//
// Lock the specified registers
//
EALLOW;
HWREGH(base + DAC_O_LOCK) |= (DAC_LOCK_KEY | reg);
EDIS;
}
//*****************************************************************************
//
//! Check if DAC Register is locked
//!
//! \param base is the DAC module base address
//! \param reg is the selected DAC register locks to check
//!
//! This function checks if write-access has been locked on the specified DAC
//! register.
//!
//! The \e reg parameter can be an ORed combination of any of the following
//! values:
//! - \b DAC_LOCK_CONTROL - Lock the DAC control register
//! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register
//! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register
//!
//! \return Returns \b true if any of the registers specified are locked, and
//! \b false if all specified registers aren't locked.
//
//*****************************************************************************
static inline bool
DAC_isRegisterLocked(uint32_t base, uint16_t reg)
{
//
// Check the arguments.
//
ASSERT(DAC_isBaseValid(base));
ASSERT((reg & ~(DAC_LOCK_CONTROL | DAC_LOCK_SHADOW |
DAC_LOCK_OUTPUT)) == 0U);
//
// Return the lock status on the specified registers
//
return((bool)((HWREGH(base + DAC_O_LOCK) & reg) != 0U));
}
//*****************************************************************************
//
//! Tune DAC Offset Trim
//!
//! \param base is the DAC module base address
//! \param referenceVoltage is the reference voltage the DAC
//! module is operating at.
//!
//! This function adjusts/tunes the DAC offset trim. The \e referenceVoltage
//! value should be a floating point number in the range specified in the
//! device data manual.
//!
//! \note Use this function to adjust the DAC offset trim if operating
//! at a reference voltage other than 2.5v. Since this function modifies
//! the DAC offset trim register, it should only be called once after
//! Device_cal. If it is called multiple times after Device_cal, the offset
//! value scaled would be the wrong value.
//!
//! \return None.
//
//*****************************************************************************
extern void
DAC_tuneOffsetTrim(uint32_t base, float32_t referenceVoltage);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // DAC_H
28379d_P_SFRA/device/driverlib/dcsm.c
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//#############################################################################
//
// FILE: dcsm.c
//
// TITLE: C28x Driver for the DCSM security module.
//
//#############################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
#include "dcsm.h"
//*****************************************************************************
//
// DCSM_unlockZone1CSM
//
//*****************************************************************************
void
DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey)
{
uint32_t linkPointer;
uint32_t zsbBase = (DCSM_Z1OTP_BASE + 0x20U); // base address of the ZSB
int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer)
int32_t zeroFound = 0;
//
// Check the arguments.
//
ASSERT(psCMDKey != NULL);
linkPointer = HWREG(DCSM_Z1_BASE + DCSM_O_Z1_LINKPOINTER);
//
// Bits 31 and 30 as most-significant 0 are invalid LinkPointer options
//
linkPointer = linkPointer << 3;
//
// Zone-Select Block (ZSB) selection using Link-Pointers
// and 0's bit position within the Link pointer
//
while((zeroFound == 0) && (bitPos > -1))
{
//
// The most significant bit position in the resolved link pointer
// which is 0, defines the valid base address for the ZSB.
//
if((linkPointer & 0x80000000U) == 0U)
{
zeroFound = 1;
//
// Base address of the ZSB is calculated using
// 0x10 as the slope/step with which zsbBase expands with
// change in the bitPos and 3*0x10 is the offset
//
zsbBase = (DCSM_Z1OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U));
}
else
{
//
// Move through the linkPointer to find the most significant
// bit position of 0
//
bitPos--;
linkPointer = linkPointer << 1;
}
}
//
// Perform dummy reads on the 128-bit password
// Using linkPointer because it is no longer needed
//
linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD0);
linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD1);
linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD2);
linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD3);
if(psCMDKey != NULL)
{
HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY0) = psCMDKey->csmKey0;
HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY1) = psCMDKey->csmKey1;
HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY2) = psCMDKey->csmKey2;
HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY3) = psCMDKey->csmKey3;
}
}
//*****************************************************************************
//
// DCSM_unlockZone2CSM
//
//*****************************************************************************
void
DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey)
{
uint32_t linkPointer;
uint32_t zsbBase = (DCSM_Z2OTP_BASE + 0x20U); // base address of the ZSB
int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer)
int32_t zeroFound = 0;
//
// Check the arguments.
//
ASSERT(psCMDKey != NULL);
linkPointer = HWREG(DCSM_Z2_BASE + DCSM_O_Z2_LINKPOINTER);
//
// Bits 31 and 30 as most-significant 0 are invalid LinkPointer options
//
linkPointer = linkPointer << 3;
//
// Zone-Select Block (ZSB) selection using Link-Pointers
// and 0's bit position within the Link pointer
//
while((zeroFound == 0) && (bitPos > -1))
{
//
// The most significant bit position in the resolved link pointer
// which is 0, defines the valid base address for the ZSB.
//
if((linkPointer & 0x80000000U) == 0U)
{
zeroFound = 1;
//
// Base address of the ZSB is calculated using
// 0x10 as the slope/step with which zsbBase expands with
// change in the bitPos and 3*0x10 is the offset
//
zsbBase = (DCSM_Z2OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U));
}
else
{
//
// Move through the linkPointer to find the most significant
// bit position of 0
//
bitPos--;
linkPointer = linkPointer << 1;
}
}
//
// Perform dummy reads on the 128-bit password
// Using linkPointer because it is no longer needed
//
linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD0);
linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD1);
linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD2);
linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD3);
if(psCMDKey != NULL)
{
HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY0) = psCMDKey->csmKey0;
HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY1) = psCMDKey->csmKey1;
HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY2) = psCMDKey->csmKey2;
HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY3) = psCMDKey->csmKey3;
}
}
//*****************************************************************************
//
// DCSM_getZone1FlashEXEStatus
//
//*****************************************************************************
DCSM_EXEOnlyStatus
DCSM_getZone1FlashEXEStatus(DCSM_Sector sector)
{
uint16_t regValue;
DCSM_EXEOnlyStatus status;
//
// Check if sector belongs to this zone
//
if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE1)
{
status = DCSM_INCORRECT_ZONE;
}
else
{
//
// Get the EXE status register
//
regValue = HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYSECTR);
//
// Get the EXE status of the Flash Sector
//
status = (DCSM_EXEOnlyStatus)((uint16_t)
((regValue >> (uint16_t)sector) &
0x01U));
}
return(status);
}
//*****************************************************************************
//
// DCSM_getZone1RAMEXEStatus
//
//*****************************************************************************
DCSM_EXEOnlyStatus
DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module)
{
ASSERT(module != DCSM_CLA);
uint32_t status;
//
// Check if module belongs to this zone
//
if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE1)
{
status = DCSM_INCORRECT_ZONE;
}
else
{
//
// Get the EXE status of the RAM Module
//
status = (uint16_t)((HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYRAMR) >>
(uint16_t)module) & 0x01U);
}
return((DCSM_EXEOnlyStatus)status);
}
//*****************************************************************************
//
// DCSM_getZone2FlashEXEStatus
//
//*****************************************************************************
DCSM_EXEOnlyStatus
DCSM_getZone2FlashEXEStatus(DCSM_Sector sector)
{
uint16_t regValue;
DCSM_EXEOnlyStatus status;
//
// Check if sector belongs to this zone
//
if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE2)
{
status = DCSM_INCORRECT_ZONE;
}
else
{
//
// Get the EXE status register
//
regValue = HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_EXEONLYSECTR);
//
// Get the EXE status of the Flash Sector
//
status = (DCSM_EXEOnlyStatus)((uint16_t)((regValue >>
(uint16_t)sector) & 0x01U));
}
return(status);
}
//*****************************************************************************
//
// DCSM_getZone2RAMEXEStatus
//
//*****************************************************************************
DCSM_EXEOnlyStatus
DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module)
{
ASSERT(module != DCSM_CLA);
uint32_t status;
//
// Check if module belongs to this zone
//
if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE2)
{
status = DCSM_INCORRECT_ZONE;
}
else
{
//
// Get the EXE status of the RAM Module
//
status = (uint16_t)((HWREGH(DCSM_Z2_BASE +
DCSM_O_Z2_EXEONLYRAMR) >> (uint16_t)module) & 0x01U);
}
return((DCSM_EXEOnlyStatus)status);
}
//*****************************************************************************
//
// DCSM_claimZoneSemaphore
//
//*****************************************************************************
bool
DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone)
{
//
// FLSEM register address.
//
uint32_t regAddress = DCSMCOMMON_BASE + DCSM_O_FLSEM;
EALLOW;
//
// Write 0xA5 to the key and write the zone that is attempting to claim the
// Flash Pump Semaphore to the semaphore bits.
//
HWREGH(regAddress) = ((uint16_t)FLSEM_KEY << DCSM_FLSEM_KEY_S) |
(uint16_t)zone;
EDIS;
//
// If the calling function was unable to claim the zone semaphore, then
// return false
//
return(((HWREGH(regAddress) & DCSM_FLSEM_SEM_M) == (uint16_t)zone) ?
true : false);
}
//*****************************************************************************
//
// DCSM_releaseZoneSemaphore
//
//*****************************************************************************
bool
DCSM_releaseZoneSemaphore(void)
{
//
// FLSEM register address.
//
uint32_t regAddress = DCSMCOMMON_BASE + DCSM_O_FLSEM;
EALLOW;
//
// Write 0xA5 to the key and write the zone that is attempting to claim the
// Flash Pump Semaphore to the semaphore bits.
//
HWREGH(regAddress) = ((uint16_t)FLSEM_KEY << DCSM_FLSEM_KEY_S);
EDIS;
//
// If the calling function was unable to release the zone semaphore, then
// return false
//
return(((HWREGH(regAddress) & DCSM_FLSEM_SEM_M) == 0x0U) ? true : false);
}
28379d_P_SFRA/device/driverlib/dcsm.h
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//#############################################################################
//
// FILE: dcsm.h
//
// TITLE: C28x Driver for the DCSM security module.
//
//#############################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//#############################################################################
#ifndef DCSM_H
#define DCSM_H
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup dcsm_api DCSM
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_dcsm.h"
#include "inc/hw_types.h"
#include "inc/hw_memmap.h"
#include "inc/hw_sysctl.h"
#include "cpu.h"
#include "debug.h"
//*****************************************************************************
//
// Defines for the unlockZone1CSM() and unlockZone2CSM().
// These are not parameters for any function.
// These are not intended for application code.
//
//*****************************************************************************
#define DCSM_O_Z1_CSMPSWD0 0x08U //!< Z1 CSMPSWD0 offset
#define DCSM_O_Z1_CSMPSWD1 0x0AU //!< Z1 CSMPSWD1 offset
#define DCSM_O_Z1_CSMPSWD2 0x0CU //!< Z1 CSMPSWD2 offset
#define DCSM_O_Z1_CSMPSWD3 0x0EU //!< Z1 CSMPSWD3 offset
#define DCSM_O_Z2_CSMPSWD0 0x08U //!< Z2 CSMPSWD0 offset
#define DCSM_O_Z2_CSMPSWD1 0x0AU //!< Z2 CSMPSWD1 offset
#define DCSM_O_Z2_CSMPSWD2 0x0CU //!< Z2 CSMPSWD2 offset
#define DCSM_O_Z2_CSMPSWD3 0x0EU //!< Z2 CSMPSWD3 offset
//*****************************************************************************
//
// Register key defines.
//
//*****************************************************************************
#define FLSEM_KEY 0xA5U //!< Zone semaphore key
//*****************************************************************************
//
//! Data structures to hold password keys.
//
//*****************************************************************************
typedef struct
{
uint32_t csmKey0;
uint32_t csmKey1;
uint32_t csmKey2;
uint32_t csmKey3;
} DCSM_CSMPasswordKey;
//*****************************************************************************
//
//! Values to distinguish the status of RAM or FLASH sectors. These values
//! describe which zone the memory location belongs too.
//! These values can be returned from DCSM_getRAMZone(),
//! DCSM_getFlashSectorZone().
//
//*****************************************************************************
typedef enum
{
DCSM_MEMORY_INACCESSIBLE, //!< Inaccessible
DCSM_MEMORY_ZONE1, //!< Zone 1
DCSM_MEMORY_ZONE2, //!< Zone 2
DCSM_MEMORY_FULL_ACCESS //!< Full access
} DCSM_MemoryStatus;
//*****************************************************************************
//
//! Values to pass to DCSM_claimZoneSemaphore(). These values are used
//! to describe the zone that can write to Flash Wrapper registers.
//
//*****************************************************************************
typedef enum
{
DCSM_FLSEM_ZONE1 = 0x01U, //!< Flash semaphore Zone 1
DCSM_FLSEM_ZONE2 = 0x02U //!< Flash semaphore Zone 2
} DCSM_SemaphoreZone;
//*****************************************************************************
//
//! Values to distinguish the security status of the zones.
//! These values can be returned from DCSM_getZone1CSMSecurityStatus(),
//! DCSM_getZone2CSMSecurityStatus().
//
//*****************************************************************************
typedef enum
{
DCSM_STATUS_SECURE, //!< Secure
DCSM_STATUS_UNSECURE, //!< Unsecure
DCSM_STATUS_LOCKED, //!< Locked
} DCSM_SecurityStatus;
//*****************************************************************************
//
// Values to distinguish the status of the Control Registers. These values
// describe can be used with the return values of
// DCSM_getZone1ControlStatus(), and DCSM_getZone2ControlStatus().
//
//*****************************************************************************
#define DCSM_ALLZERO 0x08U //!< CSM Passwords all zeros
#define DCSM_ALLONE 0x10U //!< CSM Passwords all ones
#define DCSM_UNSECURE 0x20U //!< Zone is secure/unsecure
#define DCSM_ARMED 0x40U //!< CSM is armed
//*****************************************************************************
//
//! Values to decribe the EXEONLY Status.
//! These values are returned from to DCSM_getZone1RAMEXEStatus(),
//! DCSM_getZone2RAMEXEStatus(), DCSM_getZone1FlashEXEStatus(),
//! DCSM_getZone2FlashEXEStatus().
//
//*****************************************************************************
typedef enum
{
DCSM_PROTECTED, //!< Protected
DCSM_UNPROTECTED, //!< Unprotected
DCSM_INCORRECT_ZONE //!< Incorrect Zone
}DCSM_EXEOnlyStatus;
//*****************************************************************************
//
//! Values to distinguish RAM Module.
//! These values can be passed to DCSM_getZone1RAMEXEStatus()
//! DCSM_getZone2RAMEXEStatus(), DCSM_getRAMZone().
//
//*****************************************************************************
typedef enum
{
//
//C28x RAMs
//
DCSM_RAMLS0, //!< RAMLS0
DCSM_RAMLS1, //!< RAMLS1
DCSM_RAMLS2, //!< RAMLS2
DCSM_RAMLS3, //!< RAMLS3
DCSM_RAMLS4, //!< RAMLS4
DCSM_RAMLS5, //!< RAMLS5
DCSM_RAMD0, //!< RAMD0
DCSM_RAMD1, //!< RAMD1
DCSM_CLA = 14U //!<Offset of CLA field in in RAMSTAT divided by two
} DCSM_RAMModule;
//*****************************************************************************
//
//! Values to distinguish Flash Sector.
//! These values can be passed to DCSM_getZone1FlashEXEStatus()
//! DCSM_getZone2FlashEXEStatus(), DCSM_getFlashSectorZone().
//
//*****************************************************************************
typedef enum
{
DCSM_SECTOR_A, //!< Sector A
DCSM_SECTOR_B, //!< Sector B
DCSM_SECTOR_C, //!< Sector C
DCSM_SECTOR_D, //!< Sector D
DCSM_SECTOR_E, //!< Sector E
DCSM_SECTOR_F, //!< Sector F
DCSM_SECTOR_G, //!< Sector G
DCSM_SECTOR_H, //!< Sector H
DCSM_SECTOR_I, //!< Sector I
DCSM_SECTOR_J, //!< Sector J
DCSM_SECTOR_K, //!< Sector K
DCSM_SECTOR_L, //!< Sector L
DCSM_SECTOR_M, //!< Sector M
DCSM_SECTOR_N, //!< Sector N
} DCSM_Sector;
//*****************************************************************************
//
// DCSM functions
//
//*****************************************************************************
//*****************************************************************************
//
//! Secures zone 1 by setting the FORCESEC bit of Z1_CR register
//!
//! This function resets the state of the zone. If the zone is unlocked,
//! it will lock(secure) the zone and also reset all the bits in the
//! Control Register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCSM_secureZone1(void)
{
//
// Write to the FORCESEC bit.
//
HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_CR)|= DCSM_Z1_CR_FORCESEC;
}
//*****************************************************************************
//
//! Secures zone 2 by setting the FORCESEC bit of Z2_CR register
//!
//! This function resets the state of the zone. If the zone is unlocked,
//! it will lock(secure) the zone and also reset all the bits in the
//! Control Register.
//!
//! \return None.
//
//*****************************************************************************
static inline void
DCSM_secureZone2(void)
{
//
// Write to the FORCESEC bit.
//
HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_CR)|= DCSM_Z2_CR_FORCESEC;
}
//*****************************************************************************
//
//! Returns the CSM security status of zone 1
//!
//! This function returns the security status of zone 1 CSM
//!
//! \return Returns security status as an enumerated type DCSM_SecurityStatus.
//
//*****************************************************************************
static inline DCSM_SecurityStatus
DCSM_getZone1CSMSecurityStatus(void)
{
uint16_t status;
DCSM_SecurityStatus returnStatus;
status = HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_CR);
//
// if ARMED bit is set and UNSECURED bit or ALLONE bit or both UNSECURED
// and ALLONE bits are set then CSM is unsecured. Else it is secure.
//
if(((status & DCSM_Z1_CR_ARMED) != 0U) &&
(((status & DCSM_Z1_CR_UNSECURE) != 0U) ||
((status & DCSM_Z1_CR_ALLONE) != 0U )))
{
returnStatus = DCSM_STATUS_UNSECURE;
}
else if((status & DCSM_Z1_CR_ALLZERO) == DCSM_Z1_CR_ALLZERO)
{
returnStatus = DCSM_STATUS_LOCKED;
}
else
{
returnStatus = DCSM_STATUS_SECURE;
}
return(returnStatus);
}
//*****************************************************************************
//
//! Returns the CSM security status of zone 2
//!
//! This function returns the security status of zone 2 CSM
//!
//! \return Returns security status as an enumerated type DCSM_SecurityStatus.
//
//*****************************************************************************
static inline DCSM_SecurityStatus
DCSM_getZone2CSMSecurityStatus(void)
{
uint16_t status;
DCSM_SecurityStatus returnStatus;
status = HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_CR);
//
// if ARMED bit is set and UNSECURED bit or ALLONE bit or both UNSECURED
// and ALLONE bits are set then CSM is unsecured. Else it is secure.
//
if(((status & DCSM_Z2_CR_ARMED) != 0U) &&
(((status & DCSM_Z2_CR_UNSECURE) != 0U) ||
((status & DCSM_Z2_CR_ALLONE) != 0U )))
{
returnStatus = DCSM_STATUS_UNSECURE;
}
else if((status & DCSM_Z2_CR_ALLZERO) == DCSM_Z2_CR_ALLZERO)
{
returnStatus = DCSM_STATUS_LOCKED;
}
else
{
returnStatus = DCSM_STATUS_SECURE;
}
return(returnStatus);
}
//*****************************************************************************
//
//! Returns the Control Status of zone 1
//!
//! This function returns the Control Status of zone 1 CSM
//!
//! \return Returns the contents of the Control Register which can be
//! used with provided defines.
//
//*****************************************************************************
static inline uint16_t
DCSM_getZone1ControlStatus(void)
{
//
// Return the contents of the CR register.
//
return(HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_CR));
}
//*****************************************************************************
//
//! Returns the Control Status of zone 2
//!
//! This function returns the Control Status of zone 2 CSM
//!
//! \return Returns the contents of the Control Register which can be
//! used with the provided defines.
//
//*****************************************************************************
static inline uint16_t
DCSM_getZone2ControlStatus(void)
{
//
// Return the contents of the CR register.
//
return(HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_CR));
}
//*****************************************************************************
//
//! Returns the security zone a RAM section belongs to
//!
//! \param module is the RAM module value. Valid values are type DCSM_RAMModule
//! C28x RAMs :
//! - \b DCSM_RAMLS0
//! - \b DCSM_RAMLS1
//! - \b DCSM_RAMLS2
//! - \b DCSM_RAMLS3
//! - \b DCSM_RAMLS4
//! - \b DCSM_RAMLS5
//! - \b DCSM_RAMD0
//! - \b DCSM_RAMD1
//!
//! This function returns the security zone a RAM section belongs to.
//!
//! \return Returns DCSM_MEMORY_INACCESSIBLE if the section is inaccessible,
//! DCSM_MEMORY_ZONE1 if the section belongs to zone 1, DCSM_MEMORY_ZONE2 if
//! the section belongs to zone 2 and DCSM_MEMORY_FULL_ACCESS if the section
//! doesn't belong to any zone (or if the section is unsecure).
//
//*****************************************************************************
static inline DCSM_MemoryStatus
DCSM_getRAMZone(DCSM_RAMModule module)
{
uint16_t shift = (uint16_t)module * 2U;
uint32_t ramStatus;
//
//Read the RAMSTAT register for the specific RAM Module.
//
ramStatus = ((HWREG(DCSMCOMMON_BASE + DCSM_O_RAMSTAT) >>
shift) & 0x03U);
return((DCSM_MemoryStatus)ramStatus);
}
//*****************************************************************************
//
//! Returns the security zone a flash sector belongs to
//!
//! \param sector is the flash sector value. Use DCSM_Sector type.
//!
//! This function returns the security zone a flash sector belongs to.
//!
//! \return Returns DCSM_MEMORY_INACCESSIBLE if the section is inaccessible ,
//! DCSM_MEMORY_ZONE1 if the section belongs to zone 1, DCSM_MEMORY_ZONE2 if
//! the section belongs to zone 2 and DCSM_MEMORY_FULL_ACCESS if the section
//! doesn't belong to any zone (or if the section is unsecure)..
//
//*****************************************************************************
static inline DCSM_MemoryStatus
DCSM_getFlashSectorZone(DCSM_Sector sector)
{
uint32_t sectStat;
uint16_t shift;
//
// Get the Sector status register for the specific bank
//
sectStat = HWREG(DCSMCOMMON_BASE + DCSM_O_SECTSTAT);
shift = (uint16_t)sector * 2U;
//
//Read the SECTSTAT register for the specific Flash Sector.
//
return((DCSM_MemoryStatus)((uint16_t)((sectStat >> shift) & 0x3U)));
}
//*****************************************************************************
//
//! Read Zone 1 Link Pointer Error
//!
//! A non-zero value indicates an error on the bit position that is set to 1.
//!
//! \return Returns the value of the Zone 1 Link Pointer error.
//
//*****************************************************************************
static inline uint32_t
DCSM_getZone1LinkPointerError(void)
{
//
// Return the LinkPointer Error for specific bank
//
return(HWREG(DCSM_Z1_BASE + DCSM_O_Z1_LINKPOINTERERR));
}
//*****************************************************************************
//
//! Read Zone 2 Link Pointer Error
//!
//! A non-zero value indicates an error on the bit position that is set to 1.
//!
//! \return Returns the value of the Zone 2 Link Pointer error.
//
//*****************************************************************************
static inline uint32_t
DCSM_getZone2LinkPointerError(void)
{
//
// Return the LinkPointer Error for specific bank
//
return(HWREG(DCSM_Z2_BASE + DCSM_O_Z2_LINKPOINTERERR));
}
//*****************************************************************************
//
//! Unlocks Zone 1 CSM.
//!
//! \param psCMDKey is a pointer to the DCSM_CSMPasswordKey struct that has the
//! CSM password for zone 1.
//!
//! This function unlocks the CSM password. It first reads the
//! four password locations in the User OTP. If any of the password values is
//! different from 0xFFFFFFFF, it unlocks the device by writing the provided
//! passwords into CSM Key registers
//!
//! \return None.
//!
//! \note This function should not be called in an actual application,
//! should only be used for once to program the OTP memory. Ensure flash data
//! cache is disabled before calling this function(Flash_disableCache).
//
//*****************************************************************************
extern void
DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey);
//*****************************************************************************
//
//! Unlocks Zone 2 CSM.
//!
//! \param psCMDKey is a pointer to the CSMPSWDKEY that has the CSM
//! password for zone 2.
//!
//! This function unlocks the CSM password. It first reads
//! the four password locations in the User OTP. If any of the password values
//! is different from 0xFFFFFFFF, it unlocks the device by writing the
//! provided passwords into CSM Key registers
//!
//! \return None.
//!
//! \note This function should not be called in an actual application,
//! should only be used for once to program the OTP memory. Ensure flash data
//! cache is disabled before calling this function(Flash_disableCache).
//
//*****************************************************************************
extern void
DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey);
//*****************************************************************************
//
//! Returns the EXE-ONLY status of zone 1 for a flash sector
//!
//! \param sector is the flash sector value. Use DCSM_Sector type.
//!
//! This function takes in a valid sector value and returns the status of EXE
//! ONLY security protection for the sector.
//!
//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected,
//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected,
//! DCSM_INCORRECT_ZONE if sector does not belong to this zone.
//
//*****************************************************************************
extern DCSM_EXEOnlyStatus
DCSM_getZone1FlashEXEStatus(DCSM_Sector sector);
//*****************************************************************************
//
//! Returns the EXE-ONLY status of zone 1 for a RAM module
//!
//! \param module is the RAM module value. Valid values are type DCSM_RAMModule
//! C28x RAMs :
//! - \b DCSM_RAMLS0
//! - \b DCSM_RAMLS1
//! - \b DCSM_RAMLS2
//! - \b DCSM_RAMLS3
//! - \b DCSM_RAMLS4
//! - \b DCSM_RAMLS5
//! - \b DCSM_RAMD0
//! - \b DCSM_RAMD1
//!
//! This function takes in a valid module value and returns the status of EXE
//! ONLY security protection for that module. DCSM_CLA is an invalid module
//! value. There is no EXE-ONLY available for DCSM_CLA.
//!
//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected,
//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected,
//! DCSM_INCORRECT_ZONE if module does not belong to this zone.
//
//*****************************************************************************
extern DCSM_EXEOnlyStatus
DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module);
//*****************************************************************************
//
//! Returns the EXE-ONLY status of zone 2 for a flash sector
//!
//! \param sector is the flash sector value. Use DCSM_Sector type.
//!
//! This function takes in a valid sector value and returns the status of EXE
//! ONLY security protection for the sector.
//!
//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected,
//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected,
//! DCSM_INCORRECT_ZONE if sector does not belong to this zone.
//
//*****************************************************************************
extern DCSM_EXEOnlyStatus
DCSM_getZone2FlashEXEStatus(DCSM_Sector sector);
//*****************************************************************************
//
//! Returns the EXE-ONLY status of zone 2 for a RAM module
//!
//! \param module is the RAM module value. Valid values are type DCSM_RAMModule
//! C28x RAMs :
//! - \b DCSM_RAMLS0
//! - \b DCSM_RAMLS1
//! - \b DCSM_RAMLS2
//! - \b DCSM_RAMLS3
//! - \b DCSM_RAMLS4
//! - \b DCSM_RAMLS5
//! - \b DCSM_RAMD0
//! - \b DCSM_RAMD1
//!
//! This function takes in a valid module value and returns the status of EXE
//! ONLY security protection for that module. DCSM_CLA is an invalid module
//! value. There is no EXE-ONLY available for DCSM_CLA.
//!
//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected,
//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected,
//! DCSM_INCORRECT_ZONE if module does not belong to this zone.
//
//*****************************************************************************
extern DCSM_EXEOnlyStatus
DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module);
//*****************************************************************************
//
//! Claims the zone semaphore which allows access to the Flash Wrapper register
//! for that zone.
//!
//! \param zone is the zone which is trying to claim the semaphore which allows
//! access to the Flash Wrapper registers.
//!
//! \return Returns true for a successful semaphore capture, false if it was
//! unable to capture the semaphore.
//
//*****************************************************************************
extern bool
DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone);
//*****************************************************************************
//
//! Releases the zone semaphore.
//!
//! \return Returns true if it was successful in releasing the zone semaphore
//! and false if it was unsuccessful in releasing the zone semaphore.
//!
//! \note If the calling function is not in the right zone to be able
//! to access this register, it will return a false.
//
//*****************************************************************************
extern bool
DCSM_releaseZoneSemaphore(void);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // DCSM_H
28379d_P_SFRA/device/driverlib/debug.h
+91
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@@ -0,0 +1,91 @@
//###########################################################################
//
// FILE: debug.h
//
// TITLE: Assert definition macro for debug.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef DEBUG_H
#define DEBUG_H
//*****************************************************************************
//
// Prototype for the function that is called when an invalid argument is passed
// to an API. This is only used when doing a DEBUG build. It is the
// application's responsibility to define the __error__ function.
//
//*****************************************************************************
extern void __error__(const char *filename, uint32_t line);
//*****************************************************************************
//
// The ASSERT macro, which does the actual assertion checking. Typically, this
// will be for procedure arguments.
//
//*****************************************************************************
#ifdef DEBUG
#ifdef __TMS320C28XX__
//
// When called from C28x application
//
#define ASSERT(expr) do \
{ \
if(!(expr)) \
{ \
__error__(__FILE__, __LINE__); \
} \
} \
while((_Bool)0)
#else
//
// When called from CLA application. Update as needed.
//
#define ASSERT(expr) do \
{ \
if(!(expr)) \
{ \
__mdebugstop(); \
} \
} \
while((_Bool)0)
#endif
#else
#define ASSERT(expr)
#endif
#endif // DEBUG_H
28379d_P_SFRA/device/driverlib/dma.c
+370
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@@ -0,0 +1,370 @@
//###########################################################################
//
// FILE: dma.c
//
// TITLE: C28x DMA driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "dma.h"
//*****************************************************************************
//
// DMA_configAddresses
//
//*****************************************************************************
void DMA_configAddresses(uint32_t base, const void *destAddr,
const void *srcAddr)
{
//
// Check the arguments.
//
ASSERT(DMA_isBaseValid(base));
EALLOW;
//
// Set up SOURCE address.
//
HWREG(base + DMA_O_SRC_BEG_ADDR_SHADOW) = (uint32_t)srcAddr;
HWREG(base + DMA_O_SRC_ADDR_SHADOW) = (uint32_t)srcAddr;
//
// Set up DESTINATION address.
//
HWREG(base + DMA_O_DST_BEG_ADDR_SHADOW) = (uint32_t)destAddr;
HWREG(base + DMA_O_DST_ADDR_SHADOW) = (uint32_t)destAddr;
EDIS;
}
//*****************************************************************************
//
// DMA_configBurst
//
//*****************************************************************************
void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep,
int16_t destStep)
{
//
// Check the arguments.
//
ASSERT(DMA_isBaseValid(base));
ASSERT((size >= 1U) && (size <= 32U));
ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) &&
((destStep >= -4096) && (destStep <= 4095)));
EALLOW;
//
// Set up BURST registers.
//
HWREGH(base + DMA_O_BURST_SIZE) = size - 1U;
HWREGH(base + DMA_O_SRC_BURST_STEP) = srcStep;
HWREGH(base + DMA_O_DST_BURST_STEP) = destStep;
EDIS;
}
//*****************************************************************************
//
// DMA_configTransfer
//
//*****************************************************************************
void DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep,
int16_t destStep)
{
//
// Check the arguments.
//
ASSERT(DMA_isBaseValid(base));
ASSERT(transferSize <= 0x10000U);
ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) &&
((destStep >= -4096) && (destStep <= 4095)));
EALLOW;
//
// Set up TRANSFER registers.
//
HWREGH(base + DMA_O_TRANSFER_SIZE) = (uint16_t)(transferSize - 1U);
HWREGH(base + DMA_O_SRC_TRANSFER_STEP) = srcStep;
HWREGH(base + DMA_O_DST_TRANSFER_STEP) = destStep;
EDIS;
}
//*****************************************************************************
//
// DMA_configWrap
//
//*****************************************************************************
void DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep,
uint32_t destWrapSize, int16_t destStep)
{
//
// Check the arguments.
//
ASSERT(DMA_isBaseValid(base));
ASSERT((srcWrapSize <= 0x10000U) || (destWrapSize <= 0x10000U));
ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) &&
((destStep >= -4096) && (destStep <= 4095)));
EALLOW;
//
// Set up WRAP registers.
//
HWREGH(base + DMA_O_SRC_WRAP_SIZE) = (uint16_t)(srcWrapSize - 1U);
HWREGH(base + DMA_O_SRC_WRAP_STEP) = srcStep;
HWREGH(base + DMA_O_DST_WRAP_SIZE) = (uint16_t)(destWrapSize - 1U);
HWREGH(base + DMA_O_DST_WRAP_STEP) = destStep;
EDIS;
}
//*****************************************************************************
//
// DMA_configMode
//
//*****************************************************************************
void DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config)
{
//
// Check the arguments.
//
ASSERT(DMA_isBaseValid(base));
EALLOW;
//
// Set up trigger selection in the CMA/CLA trigger source selection
// registers. These are considered part of system control.
//
switch(base)
{
case DMA_CH1_BASE:
//
// Channel 1
//
HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) =
(HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) &
~((uint32_t)SYSCTL_DMACHSRCSEL1_CH1_M)) |
((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH1_S);
//
// Set peripheral interrupt select bits to the channel number.
//
HWREGH(DMA_CH1_BASE + DMA_O_MODE) =
(HWREGH(DMA_CH1_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 1U;
break;
case DMA_CH2_BASE:
//
// Channel 2
//
HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) =
(HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) &
~((uint32_t)SYSCTL_DMACHSRCSEL1_CH2_M)) |
((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH2_S);
//
// Set peripheral interrupt select bits to the channel number.
//
HWREGH(DMA_CH2_BASE + DMA_O_MODE) =
(HWREGH(DMA_CH2_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 2U;
break;
case DMA_CH3_BASE:
//
// Channel 3
//
HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) =
(HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) &
~((uint32_t)SYSCTL_DMACHSRCSEL1_CH3_M)) |
((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH3_S);
//
// Set peripheral interrupt select bits to the channel number.
//
HWREGH(DMA_CH3_BASE + DMA_O_MODE) =
(HWREGH(DMA_CH3_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 3U;
break;
case DMA_CH4_BASE:
//
// Channel 4
//
HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) =
(HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) &
~((uint32_t)SYSCTL_DMACHSRCSEL1_CH4_M)) |
((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH4_S);
//
// Set peripheral interrupt select bits to the channel number.
//
HWREGH(DMA_CH4_BASE + DMA_O_MODE) =
(HWREGH(DMA_CH4_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 4U;
break;
case DMA_CH5_BASE:
//
// Channel 5
//
HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) =
(HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) &
~((uint32_t)SYSCTL_DMACHSRCSEL2_CH5_M)) |
((uint32_t)trigger << SYSCTL_DMACHSRCSEL2_CH5_S);
//
// Set peripheral interrupt select bits to the channel number.
//
HWREGH(DMA_CH5_BASE + DMA_O_MODE) =
(HWREGH(DMA_CH5_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 5U;
break;
case DMA_CH6_BASE:
//
// Channel 6
//
HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) =
(HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) &
~((uint32_t)SYSCTL_DMACHSRCSEL2_CH6_M)) |
((uint32_t)trigger << SYSCTL_DMACHSRCSEL2_CH6_S);
//
// Set peripheral interrupt select bits to the channel number.
//
HWREGH(DMA_CH6_BASE + DMA_O_MODE) =
(HWREGH(DMA_CH6_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 6U;
break;
default:
//
// Invalid base.
//
break;
}
//
// Write the configuration to the mode register.
//
HWREGH(base + DMA_O_MODE) &= ~(DMA_MODE_DATASIZE | DMA_MODE_CONTINUOUS |
DMA_MODE_ONESHOT);
HWREGH(base + DMA_O_MODE) |= config;
EDIS;
}
//*****************************************************************************
//
// DMA_configChannel
//
//*****************************************************************************
void DMA_configChannel(uint32_t base, const DMA_ConfigParams *transfParams)
{
//
// Check the arguments.
//
ASSERT(DMA_isBaseValid(base));
ASSERT(((transfParams->configSize == DMA_CFG_SIZE_16BIT) ||
(transfParams->configSize == DMA_CFG_SIZE_32BIT)) &&
((transfParams->transferMode == DMA_CFG_ONESHOT_DISABLE) ||
(transfParams->transferMode == DMA_CFG_ONESHOT_ENABLE)) &&
((transfParams->reinitMode == DMA_CFG_CONTINUOUS_DISABLE) ||
(transfParams->reinitMode == DMA_CFG_CONTINUOUS_ENABLE)));
//
// Configure DMA Channel
//
DMA_configAddresses(base, (const void *)transfParams->destAddr,
(const void *)transfParams->srcAddr);
//
// Configure the size of each burst and the address step size
//
DMA_configBurst(base, transfParams->burstSize, transfParams->srcBurstStep,
transfParams->destBurstStep);
//
// Configure the transfer size and the address step that is
// made after each burst.
//
DMA_configTransfer(base, transfParams->transferSize,
transfParams->srcTransferStep,
transfParams->destTransferStep);
//
// Configure the DMA channel's wrap settings
//
DMA_configWrap(base, transfParams->srcWrapSize, transfParams->srcWrapStep,
transfParams->destWrapSize, transfParams->destWrapStep);
//
// Configure the DMA channel's trigger and mode
//
DMA_configMode(base, transfParams->transferTrigger,
transfParams->transferMode | transfParams->reinitMode |
transfParams->configSize);
//
// Enable the selected peripheral trigger to start a DMA transfer
//
DMA_enableTrigger(base);
if(transfParams->enableInterrupt)
{
//
// Set the channel interrupt mode
//
DMA_setInterruptMode(base, transfParams->interruptMode);
//
// Enable the indicated DMA channel interrupt source
//
DMA_enableInterrupt(base);
}
else
{
//
// Disable the indicated DMA channel interrupt source
//
DMA_disableInterrupt(base);
}
}
28379d_P_SFRA/device/driverlib/dma.h
+1171
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28379d_P_SFRA/device/driverlib/driver_inclusive_terminology_mapping.h
+109
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@@ -0,0 +1,109 @@
#ifndef DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_
#define DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_
//*****************************************************************************
// CLB
//*****************************************************************************
#define CLB_LOCAL_IN_MUX_SPISIMO_SLAVE CLB_LOCAL_IN_MUX_SPIPICO_PERIPHERAL
#define CLB_LOCAL_IN_MUX_SPISIMO_MASTER CLB_LOCAL_IN_MUX_SPIPICO_CONTROLLER
#define CLB_GLOBAL_IN_MUX_SPI1_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI1_SPIPOCI_CONTROLLER
#define CLB_GLOBAL_IN_MUX_SPI1_SPISTE CLB_GLOBAL_IN_MUX_SPI1_SPIPTE
#define CLB_GLOBAL_IN_MUX_SPI2_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI2_SPIPOCI_CONTROLLER
#define CLB_GLOBAL_IN_MUX_SPI2_SPISTE CLB_GLOBAL_IN_MUX_SPI2_SPIPTE
#define CLB_GLOBAL_IN_MUX_SPI3_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI3_SPIPOCI_CONTROLLER
#define CLB_GLOBAL_IN_MUX_SPI3_SPISTE CLB_GLOBAL_IN_MUX_SPI3_SPIPTE
#define CLB_GLOBAL_IN_MUX_SPI4_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI4_SPIPOCI_CONTROLLER
#define CLB_GLOBAL_IN_MUX_SPI4_SPISTE CLB_GLOBAL_IN_MUX_SPI4_SPIPTE
//*****************************************************************************
// SPI
//*****************************************************************************
#define SPI_MODE_SLAVE SPI_MODE_PERIPHERAL
#define SPI_MODE_MASTER SPI_MODE_CONTROLLER
#define SPI_MODE_SLAVE_OD SPI_MODE_PERIPHERAL_OD
#define SPI_MODE_MASTER_OD SPI_MODE_CONTROLLER_OD
#define SPI_STE_ACTIVE_LOW SPI_PTE_ACTIVE_LOW
#define SPI_STE_ACTIVE_HIGH SPI_PTE_ACTIVE_HIGH
#define SPI_setSTESignalPolarity SPI_setPTESignalPolarity
//*****************************************************************************
// Interrupt
//*****************************************************************************
#define Interrupt_enableMaster Interrupt_enableGlobal
#define Interrupt_disableMaster Interrupt_disableGlobal
//*****************************************************************************
// SysCtrl
//*****************************************************************************
#define SysCtl_AccessMaster SysCtl_AccessController
#define SYSCTL_SEC_MASTER_CLA SYSCTL_SEC_CONTROLLER_CLA
#define SYSCTL_SEC_MASTER_DMA SYSCTL_SEC_CONTROLLER_DMA
#define SysCtl_selectSecMaster SysCtl_selectSecController
//*****************************************************************************
// GPIO
//*****************************************************************************
#define GPIO_setMasterCore GPIO_setControllerCore
//*****************************************************************************
// Memcfg
//*****************************************************************************
#define MemCfg_LSRAMMMasterSel MemCfg_LSRAMMControllerSel
#define MEMCFG_LSRAMMASTER_CPU_ONLY MEMCFG_LSRAMCONTROLLER_CPU_ONLY
#define MEMCFG_LSRAMMASTER_CPU_CLA1 MEMCFG_LSRAMCONTROLLER_CPU_CLA1
#define MemCfg_setLSRAMMasterSel MemCfg_setLSRAMControllerSel
#define MemCfg_GSRAMMasterSel MemCfg_GSRAMControllerSel
#define MEMCFG_GSRAMMASTER_CPU1 MEMCFG_GSRAMCONTROLLER_CPU1
#define MEMCFG_GSRAMMASTER_CPU2 MEMCFG_GSRAMCONTROLLER_CPU2
#define MemCfg_setGSRAMMasterSel MemCfg_setGSRAMControllerSel
//*****************************************************************************
// EMIF
//*****************************************************************************
#define EMIF_MasterSelect EMIF_ControllerSelect
#define EMIF_selectMaster EMIF_selectController
#define EMIF_MASTER_CPU1_NG EMIF_CONTROLLER_CPU1_NG
#define EMIF_MASTER_CPU1_G EMIF_CONTROLLER_CPU1_G
#define EMIF_MASTER_CPU2_G EMIF_CONTROLLER_CPU2_G
#define EMIF_MASTER_CPU1_NG2 EMIF_CONTROLLER_CPU1_NG2
//*****************************************************************************
// I2C
//*****************************************************************************
#define I2C_MASTER_SEND_MODE I2C_CONTROLLER_SEND_MODE
#define I2C_MASTER_RECEIVE_MODE I2C_CONTROLLER_RECEIVE_MODE
#define I2C_SLAVE_SEND_MODE I2C_TARGET_SEND_MODE
#define I2C_SLAVE_RECEIVE_MODE I2C_TARGET_RECEIVE_MODE
#define I2C_INT_ADDR_SLAVE I2C_INT_ADDR_TARGET
#define I2C_STS_ADDR_SLAVE I2C_STS_ADDR_TARGET
#define I2C_STS_SLAVE_DIR I2C_STS_TARGET_DIR
#define I2C_INTSRC_ADDR_SLAVE I2C_INTSRC_ADDR_TARGET
#define I2C_initMaster I2C_initController
#define I2C_setSlaveAddress I2C_setTargetAddress
#define I2C_setOwnSlaveAddress I2C_setOwnAddress
//*****************************************************************************
// SDFM
//*****************************************************************************
#define SDFM_enableMasterInterrupt SDFM_enableMainInterrupt
#define SDFM_disableMasterInterrupt SDFM_disableMainInterrupt
#define SDFM_enableMasterFilter SDFM_enableMainFilter
#define SDFM_disableMasterFilter SDFM_disableMainFilter
#define SDFM_MASTER_INTERRUPT_FLAG SDFM_MAIN_INTERRUPT_FLAG
#endif /* DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ */
28379d_P_SFRA/device/driverlib/ecap.c
+61
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@@ -0,0 +1,61 @@
//###########################################################################
//
// FILE: ecap.c
//
// TITLE: C28x ECAP driver
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "ecap.h"
//*****************************************************************************
//
// ECAP_setEmulationMode
//
//*****************************************************************************
void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode)
{
ASSERT(ECAP_isBaseValid(base));
//
// Write to FREE/SOFT bit
//
HWREGH(base + ECAP_O_ECCTL1) =
((HWREGH(base + ECAP_O_ECCTL1) & (~ECAP_ECCTL1_FREE_SOFT_M)) |
((uint16_t)mode << ECAP_ECCTL1_FREE_SOFT_S));
}
28379d_P_SFRA/device/driverlib/ecap.h
+1164
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28379d_P_SFRA/device/driverlib/emif.c
+46
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//###########################################################################
//
// FILE: emif.c
//
// TITLE: C28x EMIF driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include <stdbool.h>
#include <stdint.h>
#include "emif.h"
28379d_P_SFRA/device/driverlib/emif.h
+1369
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28379d_P_SFRA/device/driverlib/epwm.c
+363
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@@ -0,0 +1,363 @@
//###########################################################################
//
// FILE: epwm.c
//
// TITLE: C28x EPWM driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "epwm.h"
//*****************************************************************************
//
// EPWM_setEmulationMode
//
//*****************************************************************************
void EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode)
{
//
// Check the arguments.
//
ASSERT(EPWM_isBaseValid(base));
//
// Write to FREE_SOFT bits
//
HWREGH(base + EPWM_O_TBCTL) =
((HWREGH(base + EPWM_O_TBCTL) & (~EPWM_TBCTL_FREE_SOFT_M)) |
((uint16_t)emulationMode << EPWM_TBCTL_FREE_SOFT_S));
}
//*****************************************************************************
//
// EPWM_configureSignal
//
//*****************************************************************************
void EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams)
{
float32_t tbClkInHz = 0.0F;
uint16_t tbPrdVal = 0U, cmpAVal = 0U, cmpBVal = 0U;
//
// Check the arguments.
//
ASSERT(EPWM_isBaseValid(base));
//
// Valid values in the function for TBCTR Mode are UP, DOWN
// and UP-DOWN count.
//
ASSERT((uint16_t)signalParams->tbCtrMode <= 2U);
//
// Configure EPWM clock Divider
//
SysCtl_setEPWMClockDivider(signalParams->epwmClkDiv);
//
// Configure Time Base counter Clock
//
EPWM_setClockPrescaler(base, signalParams->tbClkDiv,
signalParams->tbHSClkDiv);
//
// Configure Time Base Counter Mode
//
EPWM_setTimeBaseCounterMode(base, signalParams->tbCtrMode);
//
// Calculate TBCLK, TBPRD and CMPx values to be configured for
// achieving desired signal
//
tbClkInHz = ((float32_t)signalParams->sysClkInHz /
(float32_t)(1U << ((uint16_t)signalParams->epwmClkDiv +
(uint16_t)signalParams->tbClkDiv)));
if(signalParams->tbHSClkDiv <= EPWM_HSCLOCK_DIVIDER_4)
{
tbClkInHz /= (float32_t)(1U << (uint16_t)signalParams->tbHSClkDiv);
}
else
{
tbClkInHz /= (float32_t)(2U * (uint16_t)signalParams->tbHSClkDiv);
}
if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP)
{
tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f);
cmpAVal = (uint16_t)(signalParams->dutyValA *
(float32_t)(tbPrdVal + 1U));
cmpBVal = (uint16_t)(signalParams->dutyValB *
(float32_t)(tbPrdVal + 1U));
}
else if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN)
{
tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f);
cmpAVal = (uint16_t)((float32_t)(tbPrdVal + 1U) -
(signalParams->dutyValA * (float32_t)(tbPrdVal + 1U)));
cmpBVal = (uint16_t)((float32_t)(tbPrdVal + 1U) -
(signalParams->dutyValB * (float32_t)(tbPrdVal + 1U)));
}
else
{
tbPrdVal = (uint16_t)(tbClkInHz / (2.0f * signalParams->freqInHz));
cmpAVal = (uint16_t)(((float32_t)tbPrdVal -
((signalParams->dutyValA *
(float32_t)tbPrdVal))) + 0.5f);
cmpBVal = (uint16_t)(((float32_t)tbPrdVal -
((signalParams->dutyValB *
(float32_t)tbPrdVal))) + 0.5f);
}
//
// Configure TBPRD value
//
EPWM_setTimeBasePeriod(base, tbPrdVal);
//
// Default Configurations.
//
EPWM_disablePhaseShiftLoad(base);
EPWM_setPhaseShift(base, 0U);
EPWM_setTimeBaseCounter(base, 0U);
//
// Setup shadow register load on ZERO
//
EPWM_setCounterCompareShadowLoadMode(base,
EPWM_COUNTER_COMPARE_A,
EPWM_COMP_LOAD_ON_CNTR_ZERO);
EPWM_setCounterCompareShadowLoadMode(base,
EPWM_COUNTER_COMPARE_B,
EPWM_COMP_LOAD_ON_CNTR_ZERO);
//
// Set Compare values
//
EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A,
cmpAVal);
EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_B,
cmpBVal);
//
// Set actions for ePWMxA & ePWMxB
//
if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP)
{
//
// Set PWMxA on Zero
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
//
// Clear PWMxA on event A, up count
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
if(signalParams->invertSignalB == true)
{
//
// Clear PWMxB on Zero
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
//
// Set PWMxB on event B, up count
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
}
else
{
//
// Set PWMxB on Zero
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
//
// Clear PWMxB on event B, up count
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
}
}
else if((signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN))
{
//
// Set PWMxA on Zero
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
//
// Clear PWMxA on event A, down count
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
if(signalParams->invertSignalB == true)
{
//
// Clear PWMxB on Zero
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
//
// Set PWMxB on event B, down count
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
}
else
{
//
// Set PWMxB on Zero
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
//
// Clear PWMxB on event B, down count
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
}
}
else
{
//
// Clear PWMxA on Zero
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
//
// Set PWMxA on event A, up count
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA);
//
// Clear PWMxA on event A, down count
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_A,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA);
if(signalParams->invertSignalB == true)
{
//
// Set PWMxB on Zero
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
//
// Clear PWMxB on event B, up count
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
//
// Set PWMxB on event B, down count
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
}
else
{
//
// Clear PWMxB on Zero
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO);
//
// Set PWMxB on event B, up count
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_HIGH,
EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB);
//
// Clear PWMxB on event B, down count
//
EPWM_setActionQualifierAction(base,
EPWM_AQ_OUTPUT_B,
EPWM_AQ_OUTPUT_LOW,
EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB);
}
}
}
28379d_P_SFRA/device/driverlib/epwm.h
+7496
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28379d_P_SFRA/device/driverlib/eqep.c
+149
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@@ -0,0 +1,149 @@
//###########################################################################
//
// FILE: eqep.c
//
// TITLE: C28x eQEP driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "eqep.h"
//*****************************************************************************
//
// EQEP_setCompareConfig
//
//*****************************************************************************
void
EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue,
uint16_t cycles)
{
uint16_t regValue;
//
// Check the arguments.
//
ASSERT(EQEP_isBaseValid(base));
ASSERT(cycles <= (EQEP_QPOSCTL_PCSPW_M + 1U));
//
// Set the compare match value
//
HWREG(base + EQEP_O_QPOSCMP) = compareValue;
//
// Set the shadow register settings and pulse width.
//
regValue = (config & (uint16_t)(EQEP_QPOSCTL_PCSHDW |
EQEP_QPOSCTL_PCLOAD)) | (cycles - 1U);
HWREGH(base + EQEP_O_QPOSCTL) = (HWREGH(base + EQEP_O_QPOSCTL) &
~(EQEP_QPOSCTL_PCSPW_M |
EQEP_QPOSCTL_PCLOAD |
EQEP_QPOSCTL_PCSHDW)) | regValue;
//
// Set position compare sync-output mode.
//
regValue = config & (uint16_t)(EQEP_QDECCTL_SOEN | EQEP_QDECCTL_SPSEL);
HWREGH(base + EQEP_O_QDECCTL) = (HWREGH(base + EQEP_O_QDECCTL) &
~(EQEP_QDECCTL_SOEN |
EQEP_QDECCTL_SPSEL)) | regValue;
}
//*****************************************************************************
//
// EQEP_setInputPolarity
//
//*****************************************************************************
void
EQEP_setInputPolarity(uint32_t base, bool invertQEPA, bool invertQEPB,
bool invertIndex, bool invertStrobe)
{
//
// Check the arguments.
//
ASSERT(EQEP_isBaseValid(base));
//
// Configure QEPA signal
//
if(invertQEPA)
{
HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QAP;
}
else
{
HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QAP;
}
//
// Configure QEPB signal
//
if(invertQEPB)
{
HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QBP;
}
else
{
HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QBP;
}
//
// Configure index signal
//
if(invertIndex)
{
HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QIP;
}
else
{
HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QIP;
}
//
// Configure strobe signal
//
if(invertStrobe)
{
HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QSP;
}
else
{
HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QSP;
}
}
28379d_P_SFRA/device/driverlib/eqep.h
+1691
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28379d_P_SFRA/device/driverlib/flash.c
+175
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@@ -0,0 +1,175 @@
//###########################################################################
//
// FILE: flash.c
//
// TITLE: C28x Flash driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "flash.h"
#ifndef __cplusplus
#pragma CODE_SECTION(Flash_initModule, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_powerDown, ".TI.ramfunc");
#pragma CODE_SECTION(Flash_wakeFromLPM, ".TI.ramfunc");
#endif
//*****************************************************************************
//
// Flash_initModule
//
//*****************************************************************************
#ifdef __cplusplus
#pragma CODE_SECTION(".TI.ramfunc");
#endif
void
Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates)
{
//
// Check the arguments.
//
ASSERT(Flash_isCtrlBaseValid(ctrlBase));
ASSERT(Flash_isECCBaseValid(eccBase));
ASSERT(waitstates <= 0xFU);
//
// Set the bank power up delay so that the bank will power up properly.
//
Flash_setBankPowerUpDelay(ctrlBase, 0x14);
//
// Set the bank fallback power mode to active.
//
Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_ACTIVE);
//
// Power up flash bank and pump and this also sets the fall back mode of
// flash and pump as active
//
Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE);
//
// Disable cache and prefetch mechanism before changing wait states
//
Flash_disableCache(ctrlBase);
Flash_disablePrefetch(ctrlBase);
//
// Set waitstates according to frequency.
//
Flash_setWaitstates(ctrlBase, waitstates);
//
// Enable cache and prefetch mechanism to improve performance of code
// executed from flash.
//
Flash_enableCache(ctrlBase);
Flash_enablePrefetch(ctrlBase);
//
// At reset, ECC is enabled. If it is disabled by application software and
// if application again wants to enable ECC.
//
Flash_enableECC(eccBase);
//
// Force a pipeline flush to ensure that the write to the last register
// configured occurs before returning.
//
FLASH_DELAY_CONFIG;
}
//*****************************************************************************
//
// Flash_powerDown
//
//*****************************************************************************
#ifdef __cplusplus
#pragma CODE_SECTION(".TI.ramfunc");
#endif
void
Flash_powerDown(uint32_t ctrlBase)
{
//
// Check the arguments.
//
ASSERT(Flash_isCtrlBaseValid(ctrlBase));
//
// Set the bank power up delay so that it will power up properly.
//
Flash_setBankPowerUpDelay(ctrlBase, 0x14);
//
// Power down the flash bank.
//
Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_SLEEP);
//
// Power down the flash pump.
//
Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_SLEEP);
}
//*****************************************************************************
//
// Flash_wakeFromLPM
//
//*****************************************************************************
#ifdef __cplusplus
#pragma CODE_SECTION(".TI.ramfunc");
#endif
void
Flash_wakeFromLPM(uint32_t ctrlBase)
{
//
// Check the arguments.
//
ASSERT(Flash_isCtrlBaseValid(ctrlBase));
//
// Set the bank fallback power modes to active.
//
Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_ACTIVE);
//
// Set the flash pump power mode to active.
//
Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE);
}
28379d_P_SFRA/device/driverlib/flash.h
+1671
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28379d_P_SFRA/device/driverlib/gpio.c
+489
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@@ -0,0 +1,489 @@
//###########################################################################
//
// FILE: gpio.c
//
// TITLE: C28x GPIO driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "gpio.h"
//*****************************************************************************
//
// GPIO_setDirectionMode
//
//*****************************************************************************
void
GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO)
{
volatile uint32_t *gpioBaseAddr;
uint32_t pinMask;
//
// Check the arguments.
//
ASSERT(GPIO_isPinValid(pin));
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
((pin / 32U) * GPIO_CTRL_REGS_STEP);
pinMask = (uint32_t)1U << (pin % 32U);
EALLOW;
//
// Set the data direction
//
if(pinIO == GPIO_DIR_MODE_OUT)
{
//
// Output
//
gpioBaseAddr[GPIO_GPxDIR_INDEX] |= pinMask;
}
else
{
//
// Input
//
gpioBaseAddr[GPIO_GPxDIR_INDEX] &= ~pinMask;
}
EDIS;
}
//*****************************************************************************
//
// GPIO_getDirectionMode
//
//*****************************************************************************
GPIO_Direction
GPIO_getDirectionMode(uint32_t pin)
{
volatile uint32_t *gpioBaseAddr;
//
// Check the arguments.
//
ASSERT(GPIO_isPinValid(pin));
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
((pin / 32U) * GPIO_CTRL_REGS_STEP);
return((GPIO_Direction)((uint32_t)((gpioBaseAddr[GPIO_GPxDIR_INDEX] >>
(pin % 32U)) & 1U)));
}
//*****************************************************************************
//
// GPIO_setInterruptPin
//
//*****************************************************************************
void
GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum)
{
XBAR_InputNum input;
//
// Check the arguments.
//
ASSERT(GPIO_isPinValid(pin));
//
// Pick the X-BAR input that corresponds to the requested XINT.
//
switch(extIntNum)
{
case GPIO_INT_XINT1:
input = XBAR_INPUT4;
break;
case GPIO_INT_XINT2:
input = XBAR_INPUT5;
break;
case GPIO_INT_XINT3:
input = XBAR_INPUT6;
break;
case GPIO_INT_XINT4:
input = XBAR_INPUT13;
break;
case GPIO_INT_XINT5:
input = XBAR_INPUT14;
break;
default:
//
// Invalid interrupt. Shouldn't happen if enum value is used.
// XBAR_INPUT1 isn't tied to an XINT, so we'll use it to check for
// a bad value.
//
input = XBAR_INPUT1;
break;
}
if(input != XBAR_INPUT1)
{
XBAR_setInputPin(input, (uint16_t)pin);
}
}
//*****************************************************************************
//
// GPIO_setPadConfig
//
//*****************************************************************************
void
GPIO_setPadConfig(uint32_t pin, uint32_t pinType)
{
volatile uint32_t *gpioBaseAddr;
uint32_t pinMask;
//
// Check the arguments.
//
ASSERT(GPIO_isPinValid(pin));
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
((pin / 32U) * GPIO_CTRL_REGS_STEP);
pinMask = (uint32_t)1U << (pin % 32U);
EALLOW;
//
// Enable open drain if necessary
//
if((pinType & GPIO_PIN_TYPE_OD) != 0U)
{
gpioBaseAddr[GPIO_GPxODR_INDEX] |= pinMask;
}
else
{
gpioBaseAddr[GPIO_GPxODR_INDEX] &= ~pinMask;
}
//
// Enable pull-up if necessary
//
if((pinType & GPIO_PIN_TYPE_PULLUP) != 0U)
{
gpioBaseAddr[GPIO_GPxPUD_INDEX] &= ~pinMask;
}
else
{
gpioBaseAddr[GPIO_GPxPUD_INDEX] |= pinMask;
}
//
// Invert polarity if necessary
//
if((pinType & GPIO_PIN_TYPE_INVERT) != 0U)
{
gpioBaseAddr[GPIO_GPxINV_INDEX] |= pinMask;
}
else
{
gpioBaseAddr[GPIO_GPxINV_INDEX] &= ~pinMask;
}
EDIS;
}
//*****************************************************************************
//
// GPIO_getPadConfig
//
//*****************************************************************************
uint32_t
GPIO_getPadConfig(uint32_t pin)
{
volatile uint32_t *gpioBaseAddr;
uint32_t pinMask;
uint32_t pinTypeRes;
//
// Check the arguments.
//
ASSERT(GPIO_isPinValid(pin));
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
((pin / 32U) * GPIO_CTRL_REGS_STEP);
pinMask = (uint32_t)1U << (pin % 32U);
pinTypeRes = GPIO_PIN_TYPE_STD;
//
// Get open drain value
//
if((gpioBaseAddr[GPIO_GPxODR_INDEX] & pinMask) != 0U)
{
pinTypeRes |= GPIO_PIN_TYPE_OD;
}
//
// Get pull-up value
//
if((gpioBaseAddr[GPIO_GPxPUD_INDEX] & pinMask) == 0U)
{
pinTypeRes |= GPIO_PIN_TYPE_PULLUP;
}
//
// Get polarity value
//
if((gpioBaseAddr[GPIO_GPxINV_INDEX] & pinMask) != 0U)
{
pinTypeRes |= GPIO_PIN_TYPE_INVERT;
}
return(pinTypeRes);
}
//*****************************************************************************
//
// GPIO_setQualificationMode
//
//*****************************************************************************
void
GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification)
{
volatile uint32_t *gpioBaseAddr;
uint32_t qSelIndex;
uint32_t shiftAmt;
//
// Check the arguments.
//
ASSERT(GPIO_isPinValid(pin));
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
((pin / 32U) * GPIO_CTRL_REGS_STEP);
shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U);
qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U);
//
// Write the input qualification mode to the register.
//
EALLOW;
gpioBaseAddr[qSelIndex] &= ~((uint32_t)GPIO_GPAQSEL1_GPIO0_M << shiftAmt);
gpioBaseAddr[qSelIndex] |= (uint32_t)qualification << shiftAmt;
EDIS;
}
//*****************************************************************************
//
// GPIO_getQualificationMode
//
//*****************************************************************************
GPIO_QualificationMode
GPIO_getQualificationMode(uint32_t pin)
{
volatile uint32_t *gpioBaseAddr;
uint32_t qSelIndex;
uint32_t qualRes;
uint32_t shiftAmt;
//
// Check the arguments.
//
ASSERT(GPIO_isPinValid(pin));
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
((pin / 32U) * GPIO_CTRL_REGS_STEP);
shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U);
qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U);
//
// Read the qualification mode register and shift and mask to get the
// value for the specified pin.
//
qualRes = (gpioBaseAddr[qSelIndex] >> shiftAmt) &
(uint32_t)GPIO_GPAQSEL1_GPIO0_M;
return((GPIO_QualificationMode)qualRes);
}
//*****************************************************************************
//
// GPIO_setQualificationPeriod
//
//*****************************************************************************
void
GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider)
{
volatile uint32_t *gpioBaseAddr;
uint32_t pinMask, regVal, shiftAmt;
//
// Check the arguments.
//
ASSERT(GPIO_isPinValid(pin));
ASSERT((divider >= 1U) && (divider <= 510U));
shiftAmt = (pin % 32U) & ~((uint32_t)0x7U);
pinMask = (uint32_t)0xFFU << shiftAmt;
//
// Divide divider by two to get the value that needs to go into the field.
// Then shift it into the right place.
//
regVal = (divider / 2U) << shiftAmt;
//
// Write the divider parameter into the register.
//
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
((pin / 32U) * GPIO_CTRL_REGS_STEP);
EALLOW;
gpioBaseAddr[GPIO_GPxCTRL_INDEX] &= ~pinMask;
gpioBaseAddr[GPIO_GPxCTRL_INDEX] |= regVal;
EDIS;
}
//*****************************************************************************
//
// GPIO_setControllerCore
//
//*****************************************************************************
void
GPIO_setControllerCore(uint32_t pin, GPIO_CoreSelect core)
{
volatile uint32_t *gpioBaseAddr;
uint32_t cSelIndex;
uint32_t shiftAmt;
//
// Check the arguments.
//
ASSERT(GPIO_isPinValid(pin));
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
((pin / 32U) * GPIO_CTRL_REGS_STEP);
shiftAmt = (uint32_t)GPIO_GPACSEL1_GPIO1_S * (pin % 8U);
cSelIndex = GPIO_GPxCSEL_INDEX + ((pin % 32U) / 8U);
//
// Write the core parameter into the register.
//
EALLOW;
gpioBaseAddr[cSelIndex] &= ~((uint32_t)GPIO_GPACSEL1_GPIO0_M << shiftAmt);
gpioBaseAddr[cSelIndex] |= (uint32_t)core << shiftAmt;
EDIS;
}
//*****************************************************************************
//
// GPIO_setAnalogMode
//
//*****************************************************************************
void
GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode)
{
volatile uint32_t *gpioBaseAddr;
uint32_t pinMask;
//
// Check the arguments.
//
ASSERT((pin == 42U) || (pin == 43U));
pinMask = (uint32_t)1U << (pin % 32U);
gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE +
((pin / 32U) * GPIO_CTRL_REGS_STEP);
EALLOW;
//
// Set the analog mode selection.
//
if(mode == GPIO_ANALOG_ENABLED)
{
//
// Enable analog mode
//
gpioBaseAddr[GPIO_GPxAMSEL_INDEX] |= pinMask;
}
else
{
//
// Disable analog mode
//
gpioBaseAddr[GPIO_GPxAMSEL_INDEX] &= ~pinMask;
}
EDIS;
}
//*****************************************************************************
//
// GPIO_setPinConfig
//
//*****************************************************************************
void
GPIO_setPinConfig(uint32_t pinConfig)
{
uint32_t muxRegAddr;
uint32_t pinMask, shiftAmt;
muxRegAddr = (uint32_t)GPIOCTRL_BASE + (pinConfig >> 16);
shiftAmt = ((pinConfig >> 8) & (uint32_t)0xFFU);
pinMask = (uint32_t)0x3U << shiftAmt;
EALLOW;
//
// Clear fields in MUX register first to avoid glitches
//
HWREG(muxRegAddr) &= ~pinMask;
//
// Write value into GMUX register
//
HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) =
(HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) & ~pinMask) |
(((pinConfig >> 2) & (uint32_t)0x3U) << shiftAmt);
//
// Write value into MUX register
//
HWREG(muxRegAddr) |= ((pinConfig & (uint32_t)0x3U) << shiftAmt);
EDIS;
}
28379d_P_SFRA/device/driverlib/gpio.h
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28379d_P_SFRA/device/driverlib/hrpwm.c
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//###########################################################################
//
// FILE: hrpwm.c
//
// TITLE: C28x HRPWM driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "hrpwm.h"
//
// All the API functions are in-lined in hrpwm.h
//
28379d_P_SFRA/device/driverlib/hrpwm.h
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28379d_P_SFRA/device/driverlib/hw_reg_inclusive_terminology.h
+29
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#ifndef HW_REG_INCLUSIVE_TERMINOLOGY_H
#define HW_REG_INCLUSIVE_TERMINOLOGY_H
//*****************************************************************************
// SPI
//*****************************************************************************
#define SPI_CTL_CONTROLLER_PERIPHERAL SPI_CTL_MASTER_SLAVE
#define SPI_PRI_PTEINV SPI_PRI_STEINV
//*****************************************************************************
// I2C
//*****************************************************************************
#define I2C_O_TAR I2C_O_SAR
#define I2C_TAR_TAR_S I2C_SAR_SAR_S
#define I2C_TAR_TAR_M I2C_SAR_SAR_M
#define I2C_IER_AAT I2C_IER_AAS
#define I2C_STR_AAT I2C_STR_AAS
#define I2C_STR_TDIR I2C_STR_SDIR
#define I2C_MDR_CNT I2C_MDR_MST
#endif // HW_REG_INCLUSIVE_TERMINOLOGY_H
28379d_P_SFRA/device/driverlib/i2c.c
+351
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//###########################################################################
//
// FILE: i2c.c
//
// TITLE: C28x I2C driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include <stdbool.h>
#include <stdint.h>
#include "i2c.h"
//*****************************************************************************
//
// I2C_initController
//
//*****************************************************************************
void
I2C_initController(uint32_t base, uint32_t sysclkHz, uint32_t bitRate,
I2C_DutyCycle dutyCycle)
{
uint32_t modPrescale;
uint32_t divider;
uint32_t dValue;
//
// Check the arguments.
//
ASSERT(I2C_isBaseValid(base));
ASSERT((10000000U / bitRate) > 10U);
//
// Set the prescaler for the module clock.
//
modPrescale = (sysclkHz / 10000000U) - 1U;
HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale;
switch(modPrescale)
{
case 0U:
dValue = 7U;
break;
case 1U:
dValue = 6U;
break;
default:
dValue = 5U;
break;
}
//
// Set the divider for the time low
//
divider = (10000000U / bitRate) - (2U * dValue);
if(dutyCycle == I2C_DUTYCYCLE_50)
{
HWREGH(base + I2C_O_CLKH) = divider / 2U;
}
else
{
HWREGH(base + I2C_O_CLKH) = divider / 3U;
}
HWREGH(base + I2C_O_CLKL) = divider - HWREGH(base + I2C_O_CLKH);
}
//*****************************************************************************
//
// I2C_initControllerModuleFrequency
//
//*****************************************************************************
void
I2C_initControllerModuleFrequency(uint32_t base, uint32_t sysclkHz, uint32_t bitRate,
I2C_DutyCycle dutyCycle, uint32_t moduleFrequency)
{
uint32_t modPrescale;
uint32_t divider;
uint32_t dValue;
//
// Check the arguments.
//
ASSERT(I2C_isBaseValid(base));
ASSERT((moduleFrequency / bitRate) > 10U);
//
// Set the prescaler for the module clock.
//
modPrescale = (sysclkHz / moduleFrequency) - 1U;
HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale;
switch(modPrescale)
{
case 0U:
dValue = 7U;
break;
case 1U:
dValue = 6U;
break;
default:
dValue = 5U;
break;
}
//
// Set the divider for the time low
//
divider = (moduleFrequency / bitRate) - (2U * dValue);
if(dutyCycle == I2C_DUTYCYCLE_50)
{
HWREGH(base + I2C_O_CLKH) = divider / 2U;
}
else
{
HWREGH(base + I2C_O_CLKH) = divider / 3U;
}
HWREGH(base + I2C_O_CLKL) = divider - HWREGH(base + I2C_O_CLKH);
}
//*****************************************************************************
//
// I2C_enableInterrupt
//
//*****************************************************************************
void
I2C_enableInterrupt(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
ASSERT(I2C_isBaseValid(base));
//
// Enable the desired basic interrupts
//
HWREGH(base + I2C_O_IER) |= (intFlags & 0xFFFFU);
//
// Enabling addressed-as-target interrupt separately because its bit is
// different between the IER and STR registers.
//
if((intFlags & I2C_INT_ADDR_TARGET) != 0U)
{
HWREGH(base + I2C_O_IER) |= I2C_IER_AAT;
}
//
// Enable desired FIFO interrupts.
//
if((intFlags & I2C_INT_TXFF) != 0U)
{
HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_TXFFIENA;
}
if((intFlags & I2C_INT_RXFF) != 0U)
{
HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFIENA;
}
}
//*****************************************************************************
//
// I2C_disableInterrupt
//
//*****************************************************************************
void
I2C_disableInterrupt(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
ASSERT(I2C_isBaseValid(base));
//
// Disable the desired basic interrupts.
//
HWREGH(base + I2C_O_IER) &= ~(intFlags & 0xFFFFU);
//
// Disabling addressed-as-target interrupt separately because its bit is
// different between the IER and STR registers.
//
if((intFlags & I2C_INT_ADDR_TARGET) != 0U)
{
HWREGH(base + I2C_O_IER) &= ~I2C_IER_AAT;
}
//
// Disable the desired FIFO interrupts.
//
if((intFlags & I2C_INT_TXFF) != 0U)
{
HWREGH(base + I2C_O_FFTX) &= ~(I2C_FFTX_TXFFIENA);
}
if((intFlags & I2C_INT_RXFF) != 0U)
{
HWREGH(base + I2C_O_FFRX) &= ~(I2C_FFRX_RXFFIENA);
}
}
//*****************************************************************************
//
// I2C_getInterruptStatus
//
//*****************************************************************************
uint32_t
I2C_getInterruptStatus(uint32_t base)
{
uint32_t temp;
//
// Check the arguments.
//
ASSERT(I2C_isBaseValid(base));
//
// Return only the status bits associated with interrupts.
//
temp = (uint32_t)HWREGH(base + I2C_O_STR) & (uint32_t)I2C_STR_INTMASK;
//
// Read FIFO interrupt flags.
//
if((HWREGH(base + I2C_O_FFTX) & I2C_FFTX_TXFFINT) != 0U)
{
temp |= I2C_INT_TXFF;
}
if((HWREGH(base + I2C_O_FFRX) & I2C_FFRX_RXFFINT) != 0U)
{
temp |= I2C_INT_RXFF;
}
return(temp);
}
//*****************************************************************************
//
// I2C_clearInterruptStatus
//
//*****************************************************************************
void
I2C_clearInterruptStatus(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
ASSERT(I2C_isBaseValid(base));
//
// Clear the interrupt flags that are located in STR.
//
HWREGH(base + I2C_O_STR) = ((uint16_t)intFlags & I2C_STR_INTMASK);
//
// Clear the FIFO interrupt flags if needed.
//
if((intFlags & I2C_INT_TXFF) != 0U)
{
HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_TXFFINTCLR;
}
if((intFlags & I2C_INT_RXFF) != 0U)
{
HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFINTCLR;
}
}
//*****************************************************************************
//
// I2C_configureModuleFrequency
//
//*****************************************************************************
void
I2C_configureModuleFrequency(uint32_t base, uint32_t sysclkHz)
{
uint32_t modPrescale;
//
// Check the arguments.
//
ASSERT(I2C_isBaseValid(base));
//
// Set the prescaler for the module clock.
//
modPrescale = (sysclkHz / 10000000U) - 1U;
HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale;
}
//*****************************************************************************
//
// I2C_configureModuleClockFrequency
//
//*****************************************************************************
void
I2C_configureModuleClockFrequency(uint32_t base, uint32_t sysclkHz, uint32_t moduleFrequency)
{
uint32_t modPrescale;
//
// Check the arguments.
//
ASSERT(I2C_isBaseValid(base));
//
// Set the prescaler for the module clock.
//
modPrescale = (sysclkHz / moduleFrequency) - 1U;
HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale;
}
28379d_P_SFRA/device/driverlib/i2c.h
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28379d_P_SFRA/device/driverlib/inc/hw_adc.h
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//###########################################################################
//
// FILE: hw_adc.h
//
// TITLE: Definitions for the ADC registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_ADC_H
#define HW_ADC_H
//*************************************************************************************************
//
// The following are defines for the ADC register offsets
//
//*************************************************************************************************
#define ADC_O_CTL1 0x0U // ADC Control 1 Register
#define ADC_O_CTL2 0x1U // ADC Control 2 Register
#define ADC_O_BURSTCTL 0x2U // ADC Burst Control Register
#define ADC_O_INTFLG 0x3U // ADC Interrupt Flag Register
#define ADC_O_INTFLGCLR 0x4U // ADC Interrupt Flag Clear Register
#define ADC_O_INTOVF 0x5U // ADC Interrupt Overflow Register
#define ADC_O_INTOVFCLR 0x6U // ADC Interrupt Overflow Clear Register
#define ADC_O_INTSEL1N2 0x7U // ADC Interrupt 1 and 2 Selection Register
#define ADC_O_INTSEL3N4 0x8U // ADC Interrupt 3 and 4 Selection Register
#define ADC_O_SOCPRICTL 0x9U // ADC SOC Priority Control Register
#define ADC_O_INTSOCSEL1 0xAU // ADC Interrupt SOC Selection 1 Register
#define ADC_O_INTSOCSEL2 0xBU // ADC Interrupt SOC Selection 2 Register
#define ADC_O_SOCFLG1 0xCU // ADC SOC Flag 1 Register
#define ADC_O_SOCFRC1 0xDU // ADC SOC Force 1 Register
#define ADC_O_SOCOVF1 0xEU // ADC SOC Overflow 1 Register
#define ADC_O_SOCOVFCLR1 0xFU // ADC SOC Overflow Clear 1 Register
#define ADC_O_SOC0CTL 0x10U // ADC SOC0 Control Register
#define ADC_O_SOC1CTL 0x12U // ADC SOC1 Control Register
#define ADC_O_SOC2CTL 0x14U // ADC SOC2 Control Register
#define ADC_O_SOC3CTL 0x16U // ADC SOC3 Control Register
#define ADC_O_SOC4CTL 0x18U // ADC SOC4 Control Register
#define ADC_O_SOC5CTL 0x1AU // ADC SOC5 Control Register
#define ADC_O_SOC6CTL 0x1CU // ADC SOC6 Control Register
#define ADC_O_SOC7CTL 0x1EU // ADC SOC7 Control Register
#define ADC_O_SOC8CTL 0x20U // ADC SOC8 Control Register
#define ADC_O_SOC9CTL 0x22U // ADC SOC9 Control Register
#define ADC_O_SOC10CTL 0x24U // ADC SOC10 Control Register
#define ADC_O_SOC11CTL 0x26U // ADC SOC11 Control Register
#define ADC_O_SOC12CTL 0x28U // ADC SOC12 Control Register
#define ADC_O_SOC13CTL 0x2AU // ADC SOC13 Control Register
#define ADC_O_SOC14CTL 0x2CU // ADC SOC14 Control Register
#define ADC_O_SOC15CTL 0x2EU // ADC SOC15 Control Register
#define ADC_O_EVTSTAT 0x30U // ADC Event Status Register
#define ADC_O_EVTCLR 0x32U // ADC Event Clear Register
#define ADC_O_EVTSEL 0x34U // ADC Event Selection Register
#define ADC_O_EVTINTSEL 0x36U // ADC Event Interrupt Selection Register
#define ADC_O_OSDETECT 0x38U // ADC Open and Shorts Detect Register
#define ADC_O_COUNTER 0x39U // ADC Counter Register
#define ADC_O_REV 0x3AU // ADC Revision Register
#define ADC_O_OFFTRIM 0x3BU // ADC Offset Trim Register
#define ADC_O_PPB1CONFIG 0x40U // ADC PPB1 Config Register
#define ADC_O_PPB1STAMP 0x41U // ADC PPB1 Sample Delay Time Stamp Register
#define ADC_O_PPB1OFFCAL 0x42U // ADC PPB1 Offset Calibration Register
#define ADC_O_PPB1OFFREF 0x43U // ADC PPB1 Offset Reference Register
#define ADC_O_PPB1TRIPHI 0x44U // ADC PPB1 Trip High Register
#define ADC_O_PPB1TRIPLO 0x46U // ADC PPB1 Trip Low/Trigger Time Stamp Register
#define ADC_O_PPB2CONFIG 0x48U // ADC PPB2 Config Register
#define ADC_O_PPB2STAMP 0x49U // ADC PPB2 Sample Delay Time Stamp Register
#define ADC_O_PPB2OFFCAL 0x4AU // ADC PPB2 Offset Calibration Register
#define ADC_O_PPB2OFFREF 0x4BU // ADC PPB2 Offset Reference Register
#define ADC_O_PPB2TRIPHI 0x4CU // ADC PPB2 Trip High Register
#define ADC_O_PPB2TRIPLO 0x4EU // ADC PPB2 Trip Low/Trigger Time Stamp Register
#define ADC_O_PPB3CONFIG 0x50U // ADC PPB3 Config Register
#define ADC_O_PPB3STAMP 0x51U // ADC PPB3 Sample Delay Time Stamp Register
#define ADC_O_PPB3OFFCAL 0x52U // ADC PPB3 Offset Calibration Register
#define ADC_O_PPB3OFFREF 0x53U // ADC PPB3 Offset Reference Register
#define ADC_O_PPB3TRIPHI 0x54U // ADC PPB3 Trip High Register
#define ADC_O_PPB3TRIPLO 0x56U // ADC PPB3 Trip Low/Trigger Time Stamp Register
#define ADC_O_PPB4CONFIG 0x58U // ADC PPB4 Config Register
#define ADC_O_PPB4STAMP 0x59U // ADC PPB4 Sample Delay Time Stamp Register
#define ADC_O_PPB4OFFCAL 0x5AU // ADC PPB4 Offset Calibration Register
#define ADC_O_PPB4OFFREF 0x5BU // ADC PPB4 Offset Reference Register
#define ADC_O_PPB4TRIPHI 0x5CU // ADC PPB4 Trip High Register
#define ADC_O_PPB4TRIPLO 0x5EU // ADC PPB4 Trip Low/Trigger Time Stamp Register
#define ADC_O_INLTRIM1 0x70U // ADC Linearity Trim 1 Register
#define ADC_O_INLTRIM2 0x72U // ADC Linearity Trim 2 Register
#define ADC_O_INLTRIM3 0x74U // ADC Linearity Trim 3 Register
#define ADC_O_INLTRIM4 0x76U // ADC Linearity Trim 4 Register
#define ADC_O_INLTRIM5 0x78U // ADC Linearity Trim 5 Register
#define ADC_O_INLTRIM6 0x7AU // ADC Linearity Trim 6 Register
#define ADC_O_RESULT0 0x0U // ADC Result 0 Register
#define ADC_O_RESULT1 0x1U // ADC Result 1 Register
#define ADC_O_RESULT2 0x2U // ADC Result 2 Register
#define ADC_O_RESULT3 0x3U // ADC Result 3 Register
#define ADC_O_RESULT4 0x4U // ADC Result 4 Register
#define ADC_O_RESULT5 0x5U // ADC Result 5 Register
#define ADC_O_RESULT6 0x6U // ADC Result 6 Register
#define ADC_O_RESULT7 0x7U // ADC Result 7 Register
#define ADC_O_RESULT8 0x8U // ADC Result 8 Register
#define ADC_O_RESULT9 0x9U // ADC Result 9 Register
#define ADC_O_RESULT10 0xAU // ADC Result 10 Register
#define ADC_O_RESULT11 0xBU // ADC Result 11 Register
#define ADC_O_RESULT12 0xCU // ADC Result 12 Register
#define ADC_O_RESULT13 0xDU // ADC Result 13 Register
#define ADC_O_RESULT14 0xEU // ADC Result 14 Register
#define ADC_O_RESULT15 0xFU // ADC Result 15 Register
#define ADC_O_PPB1RESULT 0x10U // ADC Post Processing Block 1 Result Register
#define ADC_O_PPB2RESULT 0x12U // ADC Post Processing Block 2 Result Register
#define ADC_O_PPB3RESULT 0x14U // ADC Post Processing Block 3 Result Register
#define ADC_O_PPB4RESULT 0x16U // ADC Post Processing Block 4 Result Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCCTL1 register
//
//*************************************************************************************************
#define ADC_CTL1_INTPULSEPOS 0x4U // ADC Interrupt Pulse Position
#define ADC_CTL1_ADCPWDNZ 0x80U // ADC Power Down
#define ADC_CTL1_ADCBSYCHN_S 8U
#define ADC_CTL1_ADCBSYCHN_M 0xF00U // ADC Busy Channel
#define ADC_CTL1_ADCBSY 0x2000U // ADC Busy
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCCTL2 register
//
//*************************************************************************************************
#define ADC_CTL2_PRESCALE_S 0U
#define ADC_CTL2_PRESCALE_M 0xFU // ADC Clock Prescaler
#define ADC_CTL2_RESOLUTION 0x40U // SOC Conversion Resolution
#define ADC_CTL2_SIGNALMODE 0x80U // SOC Signaling Mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCBURSTCTL register
//
//*************************************************************************************************
#define ADC_BURSTCTL_BURSTTRIGSEL_S 0U
#define ADC_BURSTCTL_BURSTTRIGSEL_M 0x3FU // SOC Burst Trigger Source Select
#define ADC_BURSTCTL_BURSTSIZE_S 8U
#define ADC_BURSTCTL_BURSTSIZE_M 0xF00U // SOC Burst Size Select
#define ADC_BURSTCTL_BURSTEN 0x8000U // SOC Burst Mode Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTFLG register
//
//*************************************************************************************************
#define ADC_INTFLG_ADCINT1 0x1U // ADC Interrupt 1 Flag
#define ADC_INTFLG_ADCINT2 0x2U // ADC Interrupt 2 Flag
#define ADC_INTFLG_ADCINT3 0x4U // ADC Interrupt 3 Flag
#define ADC_INTFLG_ADCINT4 0x8U // ADC Interrupt 4 Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTFLGCLR register
//
//*************************************************************************************************
#define ADC_INTFLGCLR_ADCINT1 0x1U // ADC Interrupt 1 Flag Clear
#define ADC_INTFLGCLR_ADCINT2 0x2U // ADC Interrupt 2 Flag Clear
#define ADC_INTFLGCLR_ADCINT3 0x4U // ADC Interrupt 3 Flag Clear
#define ADC_INTFLGCLR_ADCINT4 0x8U // ADC Interrupt 4 Flag Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTOVF register
//
//*************************************************************************************************
#define ADC_INTOVF_ADCINT1 0x1U // ADC Interrupt 1 Overflow Flags
#define ADC_INTOVF_ADCINT2 0x2U // ADC Interrupt 2 Overflow Flags
#define ADC_INTOVF_ADCINT3 0x4U // ADC Interrupt 3 Overflow Flags
#define ADC_INTOVF_ADCINT4 0x8U // ADC Interrupt 4 Overflow Flags
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTOVFCLR register
//
//*************************************************************************************************
#define ADC_INTOVFCLR_ADCINT1 0x1U // ADC Interrupt 1 Overflow Clear Bits
#define ADC_INTOVFCLR_ADCINT2 0x2U // ADC Interrupt 2 Overflow Clear Bits
#define ADC_INTOVFCLR_ADCINT3 0x4U // ADC Interrupt 3 Overflow Clear Bits
#define ADC_INTOVFCLR_ADCINT4 0x8U // ADC Interrupt 4 Overflow Clear Bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTSEL1N2 register
//
//*************************************************************************************************
#define ADC_INTSEL1N2_INT1SEL_S 0U
#define ADC_INTSEL1N2_INT1SEL_M 0xFU // ADCINT1 EOC Source Select
#define ADC_INTSEL1N2_INT1E 0x20U // ADCINT1 Interrupt Enable
#define ADC_INTSEL1N2_INT1CONT 0x40U // ADCINT1 Continue to Interrupt Mode
#define ADC_INTSEL1N2_INT2SEL_S 8U
#define ADC_INTSEL1N2_INT2SEL_M 0xF00U // ADCINT2 EOC Source Select
#define ADC_INTSEL1N2_INT2E 0x2000U // ADCINT2 Interrupt Enable
#define ADC_INTSEL1N2_INT2CONT 0x4000U // ADCINT2 Continue to Interrupt Mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTSEL3N4 register
//
//*************************************************************************************************
#define ADC_INTSEL3N4_INT3SEL_S 0U
#define ADC_INTSEL3N4_INT3SEL_M 0xFU // ADCINT3 EOC Source Select
#define ADC_INTSEL3N4_INT3E 0x20U // ADCINT3 Interrupt Enable
#define ADC_INTSEL3N4_INT3CONT 0x40U // ADCINT3 Continue to Interrupt Mode
#define ADC_INTSEL3N4_INT4SEL_S 8U
#define ADC_INTSEL3N4_INT4SEL_M 0xF00U // ADCINT4 EOC Source Select
#define ADC_INTSEL3N4_INT4E 0x2000U // ADCINT4 Interrupt Enable
#define ADC_INTSEL3N4_INT4CONT 0x4000U // ADCINT4 Continue to Interrupt Mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOCPRICTL register
//
//*************************************************************************************************
#define ADC_SOCPRICTL_SOCPRIORITY_S 0U
#define ADC_SOCPRICTL_SOCPRIORITY_M 0x1FU // SOC Priority
#define ADC_SOCPRICTL_RRPOINTER_S 5U
#define ADC_SOCPRICTL_RRPOINTER_M 0x3E0U // Round Robin Pointer
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTSOCSEL1 register
//
//*************************************************************************************************
#define ADC_INTSOCSEL1_SOC0_S 0U
#define ADC_INTSOCSEL1_SOC0_M 0x3U // SOC0 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL1_SOC1_S 2U
#define ADC_INTSOCSEL1_SOC1_M 0xCU // SOC1 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL1_SOC2_S 4U
#define ADC_INTSOCSEL1_SOC2_M 0x30U // SOC2 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL1_SOC3_S 6U
#define ADC_INTSOCSEL1_SOC3_M 0xC0U // SOC3 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL1_SOC4_S 8U
#define ADC_INTSOCSEL1_SOC4_M 0x300U // SOC4 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL1_SOC5_S 10U
#define ADC_INTSOCSEL1_SOC5_M 0xC00U // SOC5 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL1_SOC6_S 12U
#define ADC_INTSOCSEL1_SOC6_M 0x3000U // SOC6 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL1_SOC7_S 14U
#define ADC_INTSOCSEL1_SOC7_M 0xC000U // SOC7 ADC Interrupt Trigger Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCINTSOCSEL2 register
//
//*************************************************************************************************
#define ADC_INTSOCSEL2_SOC8_S 0U
#define ADC_INTSOCSEL2_SOC8_M 0x3U // SOC8 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL2_SOC9_S 2U
#define ADC_INTSOCSEL2_SOC9_M 0xCU // SOC9 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL2_SOC10_S 4U
#define ADC_INTSOCSEL2_SOC10_M 0x30U // SOC10 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL2_SOC11_S 6U
#define ADC_INTSOCSEL2_SOC11_M 0xC0U // SOC11 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL2_SOC12_S 8U
#define ADC_INTSOCSEL2_SOC12_M 0x300U // SOC12 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL2_SOC13_S 10U
#define ADC_INTSOCSEL2_SOC13_M 0xC00U // SOC13 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL2_SOC14_S 12U
#define ADC_INTSOCSEL2_SOC14_M 0x3000U // SOC14 ADC Interrupt Trigger Select
#define ADC_INTSOCSEL2_SOC15_S 14U
#define ADC_INTSOCSEL2_SOC15_M 0xC000U // SOC15 ADC Interrupt Trigger Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOCFLG1 register
//
//*************************************************************************************************
#define ADC_SOCFLG1_SOC0 0x1U // SOC0 Start of Conversion Flag
#define ADC_SOCFLG1_SOC1 0x2U // SOC1 Start of Conversion Flag
#define ADC_SOCFLG1_SOC2 0x4U // SOC2 Start of Conversion Flag
#define ADC_SOCFLG1_SOC3 0x8U // SOC3 Start of Conversion Flag
#define ADC_SOCFLG1_SOC4 0x10U // SOC4 Start of Conversion Flag
#define ADC_SOCFLG1_SOC5 0x20U // SOC5 Start of Conversion Flag
#define ADC_SOCFLG1_SOC6 0x40U // SOC6 Start of Conversion Flag
#define ADC_SOCFLG1_SOC7 0x80U // SOC7 Start of Conversion Flag
#define ADC_SOCFLG1_SOC8 0x100U // SOC8 Start of Conversion Flag
#define ADC_SOCFLG1_SOC9 0x200U // SOC9 Start of Conversion Flag
#define ADC_SOCFLG1_SOC10 0x400U // SOC10 Start of Conversion Flag
#define ADC_SOCFLG1_SOC11 0x800U // SOC11 Start of Conversion Flag
#define ADC_SOCFLG1_SOC12 0x1000U // SOC12 Start of Conversion Flag
#define ADC_SOCFLG1_SOC13 0x2000U // SOC13 Start of Conversion Flag
#define ADC_SOCFLG1_SOC14 0x4000U // SOC14 Start of Conversion Flag
#define ADC_SOCFLG1_SOC15 0x8000U // SOC15 Start of Conversion Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOCFRC1 register
//
//*************************************************************************************************
#define ADC_SOCFRC1_SOC0 0x1U // SOC0 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC1 0x2U // SOC1 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC2 0x4U // SOC2 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC3 0x8U // SOC3 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC4 0x10U // SOC4 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC5 0x20U // SOC5 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC6 0x40U // SOC6 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC7 0x80U // SOC7 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC8 0x100U // SOC8 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC9 0x200U // SOC9 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC10 0x400U // SOC10 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC11 0x800U // SOC11 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC12 0x1000U // SOC12 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC13 0x2000U // SOC13 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC14 0x4000U // SOC14 Force Start of Conversion Bit
#define ADC_SOCFRC1_SOC15 0x8000U // SOC15 Force Start of Conversion Bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOCOVF1 register
//
//*************************************************************************************************
#define ADC_SOCOVF1_SOC0 0x1U // SOC0 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC1 0x2U // SOC1 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC2 0x4U // SOC2 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC3 0x8U // SOC3 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC4 0x10U // SOC4 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC5 0x20U // SOC5 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC6 0x40U // SOC6 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC7 0x80U // SOC7 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC8 0x100U // SOC8 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC9 0x200U // SOC9 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC10 0x400U // SOC10 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC11 0x800U // SOC11 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC12 0x1000U // SOC12 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC13 0x2000U // SOC13 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC14 0x4000U // SOC14 Start of Conversion Overflow Flag
#define ADC_SOCOVF1_SOC15 0x8000U // SOC15 Start of Conversion Overflow Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOCOVFCLR1 register
//
//*************************************************************************************************
#define ADC_SOCOVFCLR1_SOC0 0x1U // SOC0 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC1 0x2U // SOC1 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC2 0x4U // SOC2 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC3 0x8U // SOC3 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC4 0x10U // SOC4 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC5 0x20U // SOC5 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC6 0x40U // SOC6 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC7 0x80U // SOC7 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC8 0x100U // SOC8 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC9 0x200U // SOC9 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC10 0x400U // SOC10 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC11 0x800U // SOC11 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC12 0x1000U // SOC12 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC13 0x2000U // SOC13 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC14 0x4000U // SOC14 Clear Start of Conversion Overflow Bit
#define ADC_SOCOVFCLR1_SOC15 0x8000U // SOC15 Clear Start of Conversion Overflow Bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC0CTL register
//
//*************************************************************************************************
#define ADC_SOC0CTL_ACQPS_S 0U
#define ADC_SOC0CTL_ACQPS_M 0x1FFU // SOC0 Acquisition Prescale
#define ADC_SOC0CTL_CHSEL_S 15U
#define ADC_SOC0CTL_CHSEL_M 0x78000U // SOC0 Channel Select
#define ADC_SOC0CTL_TRIGSEL_S 20U
#define ADC_SOC0CTL_TRIGSEL_M 0x1F00000U // SOC0 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC1CTL register
//
//*************************************************************************************************
#define ADC_SOC1CTL_ACQPS_S 0U
#define ADC_SOC1CTL_ACQPS_M 0x1FFU // SOC1 Acquisition Prescale
#define ADC_SOC1CTL_CHSEL_S 15U
#define ADC_SOC1CTL_CHSEL_M 0x78000U // SOC1 Channel Select
#define ADC_SOC1CTL_TRIGSEL_S 20U
#define ADC_SOC1CTL_TRIGSEL_M 0x1F00000U // SOC1 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC2CTL register
//
//*************************************************************************************************
#define ADC_SOC2CTL_ACQPS_S 0U
#define ADC_SOC2CTL_ACQPS_M 0x1FFU // SOC2 Acquisition Prescale
#define ADC_SOC2CTL_CHSEL_S 15U
#define ADC_SOC2CTL_CHSEL_M 0x78000U // SOC2 Channel Select
#define ADC_SOC2CTL_TRIGSEL_S 20U
#define ADC_SOC2CTL_TRIGSEL_M 0x1F00000U // SOC2 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC3CTL register
//
//*************************************************************************************************
#define ADC_SOC3CTL_ACQPS_S 0U
#define ADC_SOC3CTL_ACQPS_M 0x1FFU // SOC3 Acquisition Prescale
#define ADC_SOC3CTL_CHSEL_S 15U
#define ADC_SOC3CTL_CHSEL_M 0x78000U // SOC3 Channel Select
#define ADC_SOC3CTL_TRIGSEL_S 20U
#define ADC_SOC3CTL_TRIGSEL_M 0x1F00000U // SOC3 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC4CTL register
//
//*************************************************************************************************
#define ADC_SOC4CTL_ACQPS_S 0U
#define ADC_SOC4CTL_ACQPS_M 0x1FFU // SOC4 Acquisition Prescale
#define ADC_SOC4CTL_CHSEL_S 15U
#define ADC_SOC4CTL_CHSEL_M 0x78000U // SOC4 Channel Select
#define ADC_SOC4CTL_TRIGSEL_S 20U
#define ADC_SOC4CTL_TRIGSEL_M 0x1F00000U // SOC4 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC5CTL register
//
//*************************************************************************************************
#define ADC_SOC5CTL_ACQPS_S 0U
#define ADC_SOC5CTL_ACQPS_M 0x1FFU // SOC5 Acquisition Prescale
#define ADC_SOC5CTL_CHSEL_S 15U
#define ADC_SOC5CTL_CHSEL_M 0x78000U // SOC5 Channel Select
#define ADC_SOC5CTL_TRIGSEL_S 20U
#define ADC_SOC5CTL_TRIGSEL_M 0x1F00000U // SOC5 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC6CTL register
//
//*************************************************************************************************
#define ADC_SOC6CTL_ACQPS_S 0U
#define ADC_SOC6CTL_ACQPS_M 0x1FFU // SOC6 Acquisition Prescale
#define ADC_SOC6CTL_CHSEL_S 15U
#define ADC_SOC6CTL_CHSEL_M 0x78000U // SOC6 Channel Select
#define ADC_SOC6CTL_TRIGSEL_S 20U
#define ADC_SOC6CTL_TRIGSEL_M 0x1F00000U // SOC6 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC7CTL register
//
//*************************************************************************************************
#define ADC_SOC7CTL_ACQPS_S 0U
#define ADC_SOC7CTL_ACQPS_M 0x1FFU // SOC7 Acquisition Prescale
#define ADC_SOC7CTL_CHSEL_S 15U
#define ADC_SOC7CTL_CHSEL_M 0x78000U // SOC7 Channel Select
#define ADC_SOC7CTL_TRIGSEL_S 20U
#define ADC_SOC7CTL_TRIGSEL_M 0x1F00000U // SOC7 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC8CTL register
//
//*************************************************************************************************
#define ADC_SOC8CTL_ACQPS_S 0U
#define ADC_SOC8CTL_ACQPS_M 0x1FFU // SOC8 Acquisition Prescale
#define ADC_SOC8CTL_CHSEL_S 15U
#define ADC_SOC8CTL_CHSEL_M 0x78000U // SOC8 Channel Select
#define ADC_SOC8CTL_TRIGSEL_S 20U
#define ADC_SOC8CTL_TRIGSEL_M 0x1F00000U // SOC8 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC9CTL register
//
//*************************************************************************************************
#define ADC_SOC9CTL_ACQPS_S 0U
#define ADC_SOC9CTL_ACQPS_M 0x1FFU // SOC9 Acquisition Prescale
#define ADC_SOC9CTL_CHSEL_S 15U
#define ADC_SOC9CTL_CHSEL_M 0x78000U // SOC9 Channel Select
#define ADC_SOC9CTL_TRIGSEL_S 20U
#define ADC_SOC9CTL_TRIGSEL_M 0x1F00000U // SOC9 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC10CTL register
//
//*************************************************************************************************
#define ADC_SOC10CTL_ACQPS_S 0U
#define ADC_SOC10CTL_ACQPS_M 0x1FFU // SOC10 Acquisition Prescale
#define ADC_SOC10CTL_CHSEL_S 15U
#define ADC_SOC10CTL_CHSEL_M 0x78000U // SOC10 Channel Select
#define ADC_SOC10CTL_TRIGSEL_S 20U
#define ADC_SOC10CTL_TRIGSEL_M 0x1F00000U // SOC10 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC11CTL register
//
//*************************************************************************************************
#define ADC_SOC11CTL_ACQPS_S 0U
#define ADC_SOC11CTL_ACQPS_M 0x1FFU // SOC11 Acquisition Prescale
#define ADC_SOC11CTL_CHSEL_S 15U
#define ADC_SOC11CTL_CHSEL_M 0x78000U // SOC11 Channel Select
#define ADC_SOC11CTL_TRIGSEL_S 20U
#define ADC_SOC11CTL_TRIGSEL_M 0x1F00000U // SOC11 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC12CTL register
//
//*************************************************************************************************
#define ADC_SOC12CTL_ACQPS_S 0U
#define ADC_SOC12CTL_ACQPS_M 0x1FFU // SOC12 Acquisition Prescale
#define ADC_SOC12CTL_CHSEL_S 15U
#define ADC_SOC12CTL_CHSEL_M 0x78000U // SOC12 Channel Select
#define ADC_SOC12CTL_TRIGSEL_S 20U
#define ADC_SOC12CTL_TRIGSEL_M 0x1F00000U // SOC12 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC13CTL register
//
//*************************************************************************************************
#define ADC_SOC13CTL_ACQPS_S 0U
#define ADC_SOC13CTL_ACQPS_M 0x1FFU // SOC13 Acquisition Prescale
#define ADC_SOC13CTL_CHSEL_S 15U
#define ADC_SOC13CTL_CHSEL_M 0x78000U // SOC13 Channel Select
#define ADC_SOC13CTL_TRIGSEL_S 20U
#define ADC_SOC13CTL_TRIGSEL_M 0x1F00000U // SOC13 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC14CTL register
//
//*************************************************************************************************
#define ADC_SOC14CTL_ACQPS_S 0U
#define ADC_SOC14CTL_ACQPS_M 0x1FFU // SOC14 Acquisition Prescale
#define ADC_SOC14CTL_CHSEL_S 15U
#define ADC_SOC14CTL_CHSEL_M 0x78000U // SOC14 Channel Select
#define ADC_SOC14CTL_TRIGSEL_S 20U
#define ADC_SOC14CTL_TRIGSEL_M 0x1F00000U // SOC14 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCSOC15CTL register
//
//*************************************************************************************************
#define ADC_SOC15CTL_ACQPS_S 0U
#define ADC_SOC15CTL_ACQPS_M 0x1FFU // SOC15 Acquisition Prescale
#define ADC_SOC15CTL_CHSEL_S 15U
#define ADC_SOC15CTL_CHSEL_M 0x78000U // SOC15 Channel Select
#define ADC_SOC15CTL_TRIGSEL_S 20U
#define ADC_SOC15CTL_TRIGSEL_M 0x1F00000U // SOC15 Trigger Source Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCEVTSTAT register
//
//*************************************************************************************************
#define ADC_EVTSTAT_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Flag
#define ADC_EVTSTAT_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Flag
#define ADC_EVTSTAT_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Flag
#define ADC_EVTSTAT_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Flag
#define ADC_EVTSTAT_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Flag
#define ADC_EVTSTAT_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Flag
#define ADC_EVTSTAT_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Flag
#define ADC_EVTSTAT_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Flag
#define ADC_EVTSTAT_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Flag
#define ADC_EVTSTAT_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Flag
#define ADC_EVTSTAT_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Flag
#define ADC_EVTSTAT_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCEVTCLR register
//
//*************************************************************************************************
#define ADC_EVTCLR_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Clear
#define ADC_EVTCLR_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Clear
#define ADC_EVTCLR_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Clear
#define ADC_EVTCLR_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Clear
#define ADC_EVTCLR_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Clear
#define ADC_EVTCLR_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Clear
#define ADC_EVTCLR_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Clear
#define ADC_EVTCLR_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Clear
#define ADC_EVTCLR_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Clear
#define ADC_EVTCLR_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Clear
#define ADC_EVTCLR_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Clear
#define ADC_EVTCLR_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCEVTSEL register
//
//*************************************************************************************************
#define ADC_EVTSEL_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Event Enable
#define ADC_EVTSEL_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Event Enable
#define ADC_EVTSEL_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Event Enable
#define ADC_EVTSEL_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Event Enable
#define ADC_EVTSEL_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Event Enable
#define ADC_EVTSEL_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Event Enable
#define ADC_EVTSEL_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Event Enable
#define ADC_EVTSEL_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Event Enable
#define ADC_EVTSEL_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Event Enable
#define ADC_EVTSEL_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Event Enable
#define ADC_EVTSEL_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Event Enable
#define ADC_EVTSEL_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Event Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCEVTINTSEL register
//
//*************************************************************************************************
#define ADC_EVTINTSEL_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Interrupt Enable
#define ADC_EVTINTSEL_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Interrupt Enable
#define ADC_EVTINTSEL_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Interrupt
// Enable
#define ADC_EVTINTSEL_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Interrupt Enable
#define ADC_EVTINTSEL_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Interrupt Enable
#define ADC_EVTINTSEL_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Interrupt
// Enable
#define ADC_EVTINTSEL_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Interrupt Enable
#define ADC_EVTINTSEL_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Interrupt Enable
#define ADC_EVTINTSEL_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Interrupt
// Enable
#define ADC_EVTINTSEL_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Interrupt Enable
#define ADC_EVTINTSEL_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Interrupt Enable
#define ADC_EVTINTSEL_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Interrupt
// Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCOSDETECT register
//
//*************************************************************************************************
#define ADC_OSDETECT_DETECTCFG_S 0U
#define ADC_OSDETECT_DETECTCFG_M 0x7U // ADC Opens and Shorts Detect Configuration
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCCOUNTER register
//
//*************************************************************************************************
#define ADC_COUNTER_FREECOUNT_S 0U
#define ADC_COUNTER_FREECOUNT_M 0xFFFU // ADC Free Running Counter Value
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCREV register
//
//*************************************************************************************************
#define ADC_REV_TYPE_S 0U
#define ADC_REV_TYPE_M 0xFFU // ADC Type
#define ADC_REV_REV_S 8U
#define ADC_REV_REV_M 0xFF00U // ADC Revision
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCOFFTRIM register
//
//*************************************************************************************************
#define ADC_OFFTRIM_OFFTRIM_S 0U
#define ADC_OFFTRIM_OFFTRIM_M 0xFFU // ADC Offset Trim
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1CONFIG register
//
//*************************************************************************************************
#define ADC_PPB1CONFIG_CONFIG_S 0U
#define ADC_PPB1CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 1 Configuration
#define ADC_PPB1CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 1 Two's Complement Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1STAMP register
//
//*************************************************************************************************
#define ADC_PPB1STAMP_DLYSTAMP_S 0U
#define ADC_PPB1STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 1 Delay Time Stamp
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1OFFCAL register
//
//*************************************************************************************************
#define ADC_PPB1OFFCAL_OFFCAL_S 0U
#define ADC_PPB1OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1TRIPHI register
//
//*************************************************************************************************
#define ADC_PPB1TRIPHI_LIMITHI_S 0U
#define ADC_PPB1TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 1 Trip High Limit
#define ADC_PPB1TRIPHI_HSIGN 0x10000U // High Limit Sign Bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1TRIPLO register
//
//*************************************************************************************************
#define ADC_PPB1TRIPLO_LIMITLO_S 0U
#define ADC_PPB1TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 1 Trip Low Limit
#define ADC_PPB1TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit
#define ADC_PPB1TRIPLO_REQSTAMP_S 20U
#define ADC_PPB1TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 1 Request Time Stamp
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2CONFIG register
//
//*************************************************************************************************
#define ADC_PPB2CONFIG_CONFIG_S 0U
#define ADC_PPB2CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 2 Configuration
#define ADC_PPB2CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 2 Two's Complement Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2STAMP register
//
//*************************************************************************************************
#define ADC_PPB2STAMP_DLYSTAMP_S 0U
#define ADC_PPB2STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 2 Delay Time Stamp
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2OFFCAL register
//
//*************************************************************************************************
#define ADC_PPB2OFFCAL_OFFCAL_S 0U
#define ADC_PPB2OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2TRIPHI register
//
//*************************************************************************************************
#define ADC_PPB2TRIPHI_LIMITHI_S 0U
#define ADC_PPB2TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 2 Trip High Limit
#define ADC_PPB2TRIPHI_HSIGN 0x10000U // High Limit Sign Bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2TRIPLO register
//
//*************************************************************************************************
#define ADC_PPB2TRIPLO_LIMITLO_S 0U
#define ADC_PPB2TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 2 Trip Low Limit
#define ADC_PPB2TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit
#define ADC_PPB2TRIPLO_REQSTAMP_S 20U
#define ADC_PPB2TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 2 Request Time Stamp
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3CONFIG register
//
//*************************************************************************************************
#define ADC_PPB3CONFIG_CONFIG_S 0U
#define ADC_PPB3CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 3 Configuration
#define ADC_PPB3CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 3 Two's Complement Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3STAMP register
//
//*************************************************************************************************
#define ADC_PPB3STAMP_DLYSTAMP_S 0U
#define ADC_PPB3STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 3 Delay Time Stamp
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3OFFCAL register
//
//*************************************************************************************************
#define ADC_PPB3OFFCAL_OFFCAL_S 0U
#define ADC_PPB3OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3TRIPHI register
//
//*************************************************************************************************
#define ADC_PPB3TRIPHI_LIMITHI_S 0U
#define ADC_PPB3TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 3 Trip High Limit
#define ADC_PPB3TRIPHI_HSIGN 0x10000U // High Limit Sign Bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3TRIPLO register
//
//*************************************************************************************************
#define ADC_PPB3TRIPLO_LIMITLO_S 0U
#define ADC_PPB3TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 3 Trip Low Limit
#define ADC_PPB3TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit
#define ADC_PPB3TRIPLO_REQSTAMP_S 20U
#define ADC_PPB3TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 3 Request Time Stamp
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4CONFIG register
//
//*************************************************************************************************
#define ADC_PPB4CONFIG_CONFIG_S 0U
#define ADC_PPB4CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 4 Configuration
#define ADC_PPB4CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 4 Two's Complement Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4STAMP register
//
//*************************************************************************************************
#define ADC_PPB4STAMP_DLYSTAMP_S 0U
#define ADC_PPB4STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 4 Delay Time Stamp
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4OFFCAL register
//
//*************************************************************************************************
#define ADC_PPB4OFFCAL_OFFCAL_S 0U
#define ADC_PPB4OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4TRIPHI register
//
//*************************************************************************************************
#define ADC_PPB4TRIPHI_LIMITHI_S 0U
#define ADC_PPB4TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 4 Trip High Limit
#define ADC_PPB4TRIPHI_HSIGN 0x10000U // High Limit Sign Bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4TRIPLO register
//
//*************************************************************************************************
#define ADC_PPB4TRIPLO_LIMITLO_S 0U
#define ADC_PPB4TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 4 Trip Low Limit
#define ADC_PPB4TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit
#define ADC_PPB4TRIPLO_REQSTAMP_S 20U
#define ADC_PPB4TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 4 Request Time Stamp
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB1RESULT register
//
//*************************************************************************************************
#define ADC_PPB1RESULT_PPBRESULT_S 0U
#define ADC_PPB1RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result
#define ADC_PPB1RESULT_SIGN_S 16U
#define ADC_PPB1RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB2RESULT register
//
//*************************************************************************************************
#define ADC_PPB2RESULT_PPBRESULT_S 0U
#define ADC_PPB2RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result
#define ADC_PPB2RESULT_SIGN_S 16U
#define ADC_PPB2RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB3RESULT register
//
//*************************************************************************************************
#define ADC_PPB3RESULT_PPBRESULT_S 0U
#define ADC_PPB3RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result
#define ADC_PPB3RESULT_SIGN_S 16U
#define ADC_PPB3RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the ADCPPB4RESULT register
//
//*************************************************************************************************
#define ADC_PPB4RESULT_PPBRESULT_S 0U
#define ADC_PPB4RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result
#define ADC_PPB4RESULT_SIGN_S 16U
#define ADC_PPB4RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits
#endif
28379d_P_SFRA/device/driverlib/inc/hw_asysctl.h
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//###########################################################################
//
// FILE: hw_asysctl.h
//
// TITLE: Definitions for the ASYSCTL registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_ASYSCTL_H
#define HW_ASYSCTL_H
//*************************************************************************************************
//
// The following are defines for the ASYSCTL register offsets
//
//*************************************************************************************************
#define ASYSCTL_O_INTOSC1TRIM 0x20U // Internal Oscillator 1 Trim Register
#define ASYSCTL_O_INTOSC2TRIM 0x22U // Internal Oscillator 2 Trim Register
#define ASYSCTL_O_TSNSCTL 0x26U // Temperature Sensor Control Register
#define ASYSCTL_O_LOCK 0x2EU // Lock Register
#define ASYSCTL_O_ANAREFTRIMA 0x36U // Analog Reference Trim A Register
#define ASYSCTL_O_ANAREFTRIMB 0x38U // Analog Reference Trim B Register
#define ASYSCTL_O_ANAREFTRIMC 0x3AU // Analog Reference Trim C Register
#define ASYSCTL_O_ANAREFTRIMD 0x3CU // Analog Reference Trim D Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the INTOSC1TRIM register
//
//*************************************************************************************************
#define ASYSCTL_INTOSC1TRIM_VALFINETRIM_S 0U
#define ASYSCTL_INTOSC1TRIM_VALFINETRIM_M 0xFFFU // Oscillator Value Fine Trim Bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the INTOSC2TRIM register
//
//*************************************************************************************************
#define ASYSCTL_INTOSC2TRIM_VALFINETRIM_S 0U
#define ASYSCTL_INTOSC2TRIM_VALFINETRIM_M 0xFFFU // Oscillator Value Fine Trim Bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the TSNSCTL register
//
//*************************************************************************************************
#define ASYSCTL_TSNSCTL_ENABLE 0x1U // Temperature Sensor Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the LOCK register
//
//*************************************************************************************************
#define ASYSCTL_LOCK_TSNSCTL 0x8U // Temperature Sensor Control Register Lock
#define ASYSCTL_LOCK_ANAREFTRIMA 0x800000U // Analog Reference A Trim Register Lock
#define ASYSCTL_LOCK_ANAREFTRIMB 0x1000000U // Analog Reference B Trim Register Lock
#define ASYSCTL_LOCK_ANAREFTRIMC 0x2000000U // Analog Reference C Trim Register Lock
#define ASYSCTL_LOCK_ANAREFTRIMD 0x4000000U // Analog Reference D Trim Register Lock
//*************************************************************************************************
//
// The following are defines for the bit fields in the ANAREFTRIMA register
//
//*************************************************************************************************
#define ASYSCTL_ANAREFTRIMA_BGVALTRIM_S 0U
#define ASYSCTL_ANAREFTRIMA_BGVALTRIM_M 0x3FU // Bandgap Value Trim
#define ASYSCTL_ANAREFTRIMA_BGSLOPETRIM_S 6U
#define ASYSCTL_ANAREFTRIMA_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim
#define ASYSCTL_ANAREFTRIMA_IREFTRIM_S 11U
#define ASYSCTL_ANAREFTRIMA_IREFTRIM_M 0xF800U // Reference Current Trim
//*************************************************************************************************
//
// The following are defines for the bit fields in the ANAREFTRIMB register
//
//*************************************************************************************************
#define ASYSCTL_ANAREFTRIMB_BGVALTRIM_S 0U
#define ASYSCTL_ANAREFTRIMB_BGVALTRIM_M 0x3FU // Bandgap Value Trim
#define ASYSCTL_ANAREFTRIMB_BGSLOPETRIM_S 6U
#define ASYSCTL_ANAREFTRIMB_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim
#define ASYSCTL_ANAREFTRIMB_IREFTRIM_S 11U
#define ASYSCTL_ANAREFTRIMB_IREFTRIM_M 0xF800U // Reference Current Trim
//*************************************************************************************************
//
// The following are defines for the bit fields in the ANAREFTRIMC register
//
//*************************************************************************************************
#define ASYSCTL_ANAREFTRIMC_BGVALTRIM_S 0U
#define ASYSCTL_ANAREFTRIMC_BGVALTRIM_M 0x3FU // Bandgap Value Trim
#define ASYSCTL_ANAREFTRIMC_BGSLOPETRIM_S 6U
#define ASYSCTL_ANAREFTRIMC_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim
#define ASYSCTL_ANAREFTRIMC_IREFTRIM_S 11U
#define ASYSCTL_ANAREFTRIMC_IREFTRIM_M 0xF800U // Reference Current Trim
//*************************************************************************************************
//
// The following are defines for the bit fields in the ANAREFTRIMD register
//
//*************************************************************************************************
#define ASYSCTL_ANAREFTRIMD_BGVALTRIM_S 0U
#define ASYSCTL_ANAREFTRIMD_BGVALTRIM_M 0x3FU // Bandgap Value Trim
#define ASYSCTL_ANAREFTRIMD_BGSLOPETRIM_S 6U
#define ASYSCTL_ANAREFTRIMD_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim
#define ASYSCTL_ANAREFTRIMD_IREFTRIM_S 11U
#define ASYSCTL_ANAREFTRIMD_IREFTRIM_M 0xF800U // Reference Current Trim
#endif
28379d_P_SFRA/device/driverlib/inc/hw_can.h
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//###########################################################################
//
// FILE: hw_can.h
//
// TITLE: Definitions for the CAN registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_CAN_H
#define HW_CAN_H
//*************************************************************************************************
//
// The following are defines for the CAN register offsets
//
//*************************************************************************************************
#define CAN_O_CTL 0x0U // CAN Control Register
#define CAN_O_ES 0x4U // Error and Status Register
#define CAN_O_ERRC 0x8U // Error Counter Register
#define CAN_O_BTR 0xCU // Bit Timing Register
#define CAN_O_INT 0x10U // Interrupt Register
#define CAN_O_TEST 0x14U // Test Register
#define CAN_O_PERR 0x1CU // CAN Parity Error Code Register
#define CAN_O_RAM_INIT 0x40U // CAN RAM Initialization Register
#define CAN_O_GLB_INT_EN 0x50U // CAN Global Interrupt Enable Register
#define CAN_O_GLB_INT_FLG 0x54U // CAN Global Interrupt Flag Register
#define CAN_O_GLB_INT_CLR 0x58U // CAN Global Interrupt Clear Register
#define CAN_O_ABOTR 0x80U // Auto-Bus-On Time Register
#define CAN_O_TXRQ_X 0x84U // CAN Transmission Request Register
#define CAN_O_TXRQ_21 0x88U // CAN Transmission Request 2_1 Register
#define CAN_O_NDAT_X 0x98U // CAN New Data Register
#define CAN_O_NDAT_21 0x9CU // CAN New Data 2_1 Register
#define CAN_O_IPEN_X 0xACU // CAN Interrupt Pending Register
#define CAN_O_IPEN_21 0xB0U // CAN Interrupt Pending 2_1 Register
#define CAN_O_MVAL_X 0xC0U // CAN Message Valid Register
#define CAN_O_MVAL_21 0xC4U // CAN Message Valid 2_1 Register
#define CAN_O_IP_MUX21 0xD8U // CAN Interrupt Multiplexer 2_1 Register
#define CAN_O_IF1CMD 0x100U // IF1 Command Register
#define CAN_O_IF1MSK 0x104U // IF1 Mask Register
#define CAN_O_IF1ARB 0x108U // IF1 Arbitration Register
#define CAN_O_IF1MCTL 0x10CU // IF1 Message Control Register
#define CAN_O_IF1DATA 0x110U // IF1 Data A Register
#define CAN_O_IF1DATB 0x114U // IF1 Data B Register
#define CAN_O_IF2CMD 0x120U // IF2 Command Register
#define CAN_O_IF2MSK 0x124U // IF2 Mask Register
#define CAN_O_IF2ARB 0x128U // IF2 Arbitration Register
#define CAN_O_IF2MCTL 0x12CU // IF2 Message Control Register
#define CAN_O_IF2DATA 0x130U // IF2 Data A Register
#define CAN_O_IF2DATB 0x134U // IF2 Data B Register
#define CAN_O_IF3OBS 0x140U // IF3 Observation Register
#define CAN_O_IF3MSK 0x144U // IF3 Mask Register
#define CAN_O_IF3ARB 0x148U // IF3 Arbitration Register
#define CAN_O_IF3MCTL 0x14CU // IF3 Message Control Register
#define CAN_O_IF3DATA 0x150U // IF3 Data A Register
#define CAN_O_IF3DATB 0x154U // IF3 Data B Register
#define CAN_O_IF3UPD 0x160U // IF3 Update Enable Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_CTL register
//
//*************************************************************************************************
#define CAN_CTL_INIT 0x1U // Initialization
#define CAN_CTL_IE0 0x2U // Interrupt line 0 Enable
#define CAN_CTL_SIE 0x4U // Status Change Interrupt Enable
#define CAN_CTL_EIE 0x8U // Error Interrupt Enable
#define CAN_CTL_DAR 0x20U // Disable Automatic Retransmission
#define CAN_CTL_CCE 0x40U // Configuration Change Enable
#define CAN_CTL_TEST 0x80U // Test Mode Enable
#define CAN_CTL_IDS 0x100U // Interruption Debug Support Enable
#define CAN_CTL_ABO 0x200U // Auto-Bus-On Enable
#define CAN_CTL_PMD_S 10U
#define CAN_CTL_PMD_M 0x3C00U // Parity on/off
#define CAN_CTL_SWR 0x8000U // SW Reset Enable
#define CAN_CTL_INITDBG 0x10000U // Debug Mode Status
#define CAN_CTL_IE1 0x20000U // Interrupt line 1 Enable Disabled
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_ES register
//
//*************************************************************************************************
#define CAN_ES_LEC_S 0U
#define CAN_ES_LEC_M 0x7U // Last Error Code
#define CAN_ES_TXOK 0x8U // Transmission status
#define CAN_ES_RXOK 0x10U // Reception status
#define CAN_ES_EPASS 0x20U // Error Passive State
#define CAN_ES_EWARN 0x40U // Warning State
#define CAN_ES_BOFF 0x80U // Bus-Off State
#define CAN_ES_PER 0x100U // Parity Error Detected
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_ERRC register
//
//*************************************************************************************************
#define CAN_ERRC_TEC_S 0U
#define CAN_ERRC_TEC_M 0xFFU // Transmit Error Counter
#define CAN_ERRC_REC_S 8U
#define CAN_ERRC_REC_M 0x7F00U // Receive Error Counter
#define CAN_ERRC_RP 0x8000U // Receive Error Passive
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_BTR register
//
//*************************************************************************************************
#define CAN_BTR_BRP_S 0U
#define CAN_BTR_BRP_M 0x3FU // Baud Rate Prescaler
#define CAN_BTR_SJW_S 6U
#define CAN_BTR_SJW_M 0xC0U // Synchronization Jump Width
#define CAN_BTR_TSEG1_S 8U
#define CAN_BTR_TSEG1_M 0xF00U // Time segment
#define CAN_BTR_TSEG2_S 12U
#define CAN_BTR_TSEG2_M 0x7000U // Time segment
#define CAN_BTR_BRPE_S 16U
#define CAN_BTR_BRPE_M 0xF0000U // Baud Rate Prescaler Extension
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_INT register
//
//*************************************************************************************************
#define CAN_INT_INT0ID_S 0U
#define CAN_INT_INT0ID_M 0xFFFFU // Interrupt Identifier
#define CAN_INT_INT1ID_S 16U
#define CAN_INT_INT1ID_M 0xFF0000U // Interrupt 1 Identifier
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_TEST register
//
//*************************************************************************************************
#define CAN_TEST_SILENT 0x8U // Silent Mode
#define CAN_TEST_LBACK 0x10U // Loopback Mode
#define CAN_TEST_TX_S 5U
#define CAN_TEST_TX_M 0x60U // CANTX Pin Control
#define CAN_TEST_RX 0x80U // CANRX Pin Status
#define CAN_TEST_EXL 0x100U // External Loopback Mode
#define CAN_TEST_RDA 0x200U // RAM Direct Access Enable:
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_PERR register
//
//*************************************************************************************************
#define CAN_PERR_MSG_NUM_S 0U
#define CAN_PERR_MSG_NUM_M 0xFFU // Message Number
#define CAN_PERR_WORD_NUM_S 8U
#define CAN_PERR_WORD_NUM_M 0x700U // Word Number
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_RAM_INIT register
//
//*************************************************************************************************
#define CAN_RAM_INIT_KEY0 0x1U // KEY0
#define CAN_RAM_INIT_KEY1 0x2U // KEY1
#define CAN_RAM_INIT_KEY2 0x4U // KEY2
#define CAN_RAM_INIT_KEY3 0x8U // KEY3
#define CAN_RAM_INIT_CAN_RAM_INIT 0x10U // Initialize CAN Mailbox RAM
#define CAN_RAM_INIT_RAM_INIT_DONE 0x20U // CAN RAM initialization complete
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_GLB_INT_EN register
//
//*************************************************************************************************
#define CAN_GLB_INT_EN_GLBINT0_EN 0x1U // Global Interrupt Enable for CANINT0
#define CAN_GLB_INT_EN_GLBINT1_EN 0x2U // Global Interrupt Enable for CANINT1
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_GLB_INT_FLG register
//
//*************************************************************************************************
#define CAN_GLB_INT_FLG_INT0_FLG 0x1U // Global Interrupt Flag for CANINT0
#define CAN_GLB_INT_FLG_INT1_FLG 0x2U // Global Interrupt Flag for CANINT1
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_GLB_INT_CLR register
//
//*************************************************************************************************
#define CAN_GLB_INT_CLR_INT0_FLG_CLR 0x1U // Global Interrupt flag clear for CANINT0
#define CAN_GLB_INT_CLR_INT1_FLG_CLR 0x2U // Global Interrupt flag clear for CANINT1
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_TXRQ_X register
//
//*************************************************************************************************
#define CAN_TXRQ_X_TXRQSTREG1_S 0U
#define CAN_TXRQ_X_TXRQSTREG1_M 0x3U // Transmit Request Register 1
#define CAN_TXRQ_X_TXRQSTREG2_S 2U
#define CAN_TXRQ_X_TXRQSTREG2_M 0xCU // Transmit Request Register 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_NDAT_X register
//
//*************************************************************************************************
#define CAN_NDAT_X_NEWDATREG1_S 0U
#define CAN_NDAT_X_NEWDATREG1_M 0x3U // New Data Register 1
#define CAN_NDAT_X_NEWDATREG2_S 2U
#define CAN_NDAT_X_NEWDATREG2_M 0xCU // New Data Register 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IPEN_X register
//
//*************************************************************************************************
#define CAN_IPEN_X_INTPNDREG1_S 0U
#define CAN_IPEN_X_INTPNDREG1_M 0x3U // Interrupt Pending Register 1
#define CAN_IPEN_X_INTPNDREG2_S 2U
#define CAN_IPEN_X_INTPNDREG2_M 0xCU // Interrupt Pending Register 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_MVAL_X register
//
//*************************************************************************************************
#define CAN_MVAL_X_MSGVALREG1_S 0U
#define CAN_MVAL_X_MSGVALREG1_M 0x3U // Message Valid Register 1
#define CAN_MVAL_X_MSGVALREG2_S 2U
#define CAN_MVAL_X_MSGVALREG2_M 0xCU // Message Valid Register 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1CMD register
//
//*************************************************************************************************
#define CAN_IF1CMD_MSG_NUM_S 0U
#define CAN_IF1CMD_MSG_NUM_M 0xFFU // Message Number
#define CAN_IF1CMD_BUSY 0x8000U // Busy Flag
#define CAN_IF1CMD_DATA_B 0x10000U // Access Data Bytes 4-7
#define CAN_IF1CMD_DATA_A 0x20000U // Access Data Bytes 0-3
#define CAN_IF1CMD_TXRQST 0x40000U // Access Transmission Request Bit
#define CAN_IF1CMD_CLRINTPND 0x80000U // Clear Interrupt Pending Bit
#define CAN_IF1CMD_CONTROL 0x100000U // Access Control Bits
#define CAN_IF1CMD_ARB 0x200000U // Access Arbitration Bits
#define CAN_IF1CMD_MASK 0x400000U // Access Mask Bits
#define CAN_IF1CMD_DIR 0x800000U // Write/Read Direction
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1MSK register
//
//*************************************************************************************************
#define CAN_IF1MSK_MSK_S 0U
#define CAN_IF1MSK_MSK_M 0x1FFFFFFFU // Identifier Mask
#define CAN_IF1MSK_MDIR 0x40000000U // Mask Message Direction
#define CAN_IF1MSK_MXTD 0x80000000U // Mask Extended Identifier
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1ARB register
//
//*************************************************************************************************
#define CAN_IF1ARB_ID_S 0U
#define CAN_IF1ARB_ID_M 0x1FFFFFFFU // `
#define CAN_IF1ARB_DIR 0x20000000U // Message Direction
#define CAN_IF1ARB_XTD 0x40000000U // Extended Identifier
#define CAN_IF1ARB_MSGVAL 0x80000000U // Message Valid
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1MCTL register
//
//*************************************************************************************************
#define CAN_IF1MCTL_DLC_S 0U
#define CAN_IF1MCTL_DLC_M 0xFU // Data length code
#define CAN_IF1MCTL_EOB 0x80U // End of Block
#define CAN_IF1MCTL_TXRQST 0x100U // Transmit Request
#define CAN_IF1MCTL_RMTEN 0x200U // Remote Enable
#define CAN_IF1MCTL_RXIE 0x400U // Receive Interrupt Enable
#define CAN_IF1MCTL_TXIE 0x800U // Transmit Interrupt Enable
#define CAN_IF1MCTL_UMASK 0x1000U // Use Acceptance Mask
#define CAN_IF1MCTL_INTPND 0x2000U // Interrupt Pending
#define CAN_IF1MCTL_MSGLST 0x4000U // Message Lost
#define CAN_IF1MCTL_NEWDAT 0x8000U // New Data
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1DATA register
//
//*************************************************************************************************
#define CAN_IF1DATA_DATA_0_S 0U
#define CAN_IF1DATA_DATA_0_M 0xFFU // Data Byte 0
#define CAN_IF1DATA_DATA_1_S 8U
#define CAN_IF1DATA_DATA_1_M 0xFF00U // Data Byte 1
#define CAN_IF1DATA_DATA_2_S 16U
#define CAN_IF1DATA_DATA_2_M 0xFF0000U // Data Byte 2
#define CAN_IF1DATA_DATA_3_S 24U
#define CAN_IF1DATA_DATA_3_M 0xFF000000U // Data Byte 3
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF1DATB register
//
//*************************************************************************************************
#define CAN_IF1DATB_DATA_4_S 0U
#define CAN_IF1DATB_DATA_4_M 0xFFU // Data Byte 4
#define CAN_IF1DATB_DATA_5_S 8U
#define CAN_IF1DATB_DATA_5_M 0xFF00U // Data Byte 5
#define CAN_IF1DATB_DATA_6_S 16U
#define CAN_IF1DATB_DATA_6_M 0xFF0000U // Data Byte 6
#define CAN_IF1DATB_DATA_7_S 24U
#define CAN_IF1DATB_DATA_7_M 0xFF000000U // Data Byte 7
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2CMD register
//
//*************************************************************************************************
#define CAN_IF2CMD_MSG_NUM_S 0U
#define CAN_IF2CMD_MSG_NUM_M 0xFFU // Message Number
#define CAN_IF2CMD_BUSY 0x8000U // Busy Flag
#define CAN_IF2CMD_DATA_B 0x10000U // Access Data Bytes 4-7
#define CAN_IF2CMD_DATA_A 0x20000U // Access Data Bytes 0-3
#define CAN_IF2CMD_TXRQST 0x40000U // Access Transmission Request Bit
#define CAN_IF2CMD_CLRINTPND 0x80000U // Clear Interrupt Pending Bit
#define CAN_IF2CMD_CONTROL 0x100000U // Access Control Bits
#define CAN_IF2CMD_ARB 0x200000U // Access Arbitration Bits
#define CAN_IF2CMD_MASK 0x400000U // Access Mask Bits
#define CAN_IF2CMD_DIR 0x800000U // Write/Read Direction
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2MSK register
//
//*************************************************************************************************
#define CAN_IF2MSK_MSK_S 0U
#define CAN_IF2MSK_MSK_M 0x1FFFFFFFU // Identifier Mask
#define CAN_IF2MSK_MDIR 0x40000000U // Mask Message Direction
#define CAN_IF2MSK_MXTD 0x80000000U // Mask Extended Identifier
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2ARB register
//
//*************************************************************************************************
#define CAN_IF2ARB_ID_S 0U
#define CAN_IF2ARB_ID_M 0x1FFFFFFFU // Message Identifier
#define CAN_IF2ARB_DIR 0x20000000U // Message Direction
#define CAN_IF2ARB_XTD 0x40000000U // Extended Identifier
#define CAN_IF2ARB_MSGVAL 0x80000000U // Message Valid
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2MCTL register
//
//*************************************************************************************************
#define CAN_IF2MCTL_DLC_S 0U
#define CAN_IF2MCTL_DLC_M 0xFU // Data length code
#define CAN_IF2MCTL_EOB 0x80U // End of Block
#define CAN_IF2MCTL_TXRQST 0x100U // Transmit Request
#define CAN_IF2MCTL_RMTEN 0x200U // Remote Enable
#define CAN_IF2MCTL_RXIE 0x400U // Receive Interrupt Enable
#define CAN_IF2MCTL_TXIE 0x800U // Transmit Interrupt Enable
#define CAN_IF2MCTL_UMASK 0x1000U // Use Acceptance Mask
#define CAN_IF2MCTL_INTPND 0x2000U // Interrupt Pending
#define CAN_IF2MCTL_MSGLST 0x4000U // Message Lost
#define CAN_IF2MCTL_NEWDAT 0x8000U // New Data
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2DATA register
//
//*************************************************************************************************
#define CAN_IF2DATA_DATA_0_S 0U
#define CAN_IF2DATA_DATA_0_M 0xFFU // Data Byte 0
#define CAN_IF2DATA_DATA_1_S 8U
#define CAN_IF2DATA_DATA_1_M 0xFF00U // Data Byte 1
#define CAN_IF2DATA_DATA_2_S 16U
#define CAN_IF2DATA_DATA_2_M 0xFF0000U // Data Byte 2
#define CAN_IF2DATA_DATA_3_S 24U
#define CAN_IF2DATA_DATA_3_M 0xFF000000U // Data Byte 3
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF2DATB register
//
//*************************************************************************************************
#define CAN_IF2DATB_DATA_4_S 0U
#define CAN_IF2DATB_DATA_4_M 0xFFU // Data Byte 4
#define CAN_IF2DATB_DATA_5_S 8U
#define CAN_IF2DATB_DATA_5_M 0xFF00U // Data Byte 5
#define CAN_IF2DATB_DATA_6_S 16U
#define CAN_IF2DATB_DATA_6_M 0xFF0000U // Data Byte 6
#define CAN_IF2DATB_DATA_7_S 24U
#define CAN_IF2DATB_DATA_7_M 0xFF000000U // Data Byte 7
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3OBS register
//
//*************************************************************************************************
#define CAN_IF3OBS_MASK 0x1U // Mask data read observation
#define CAN_IF3OBS_ARB 0x2U // Arbitration data read observation
#define CAN_IF3OBS_CTRL 0x4U // Ctrl read observation
#define CAN_IF3OBS_DATA_A 0x8U // Data A read observation
#define CAN_IF3OBS_DATA_B 0x10U // Data B read observation
#define CAN_IF3OBS_IF3SM 0x100U // IF3 Status of Mask data read access
#define CAN_IF3OBS_IF3SA 0x200U // IF3 Status of Arbitration data read access
#define CAN_IF3OBS_IF3SC 0x400U // IF3 Status of Control bits read access
#define CAN_IF3OBS_IF3SDA 0x800U // IF3 Status of Data A read access
#define CAN_IF3OBS_IF3SDB 0x1000U // IF3 Status of Data B read access
#define CAN_IF3OBS_IF3UPD 0x8000U // IF3 Update Data
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3MSK register
//
//*************************************************************************************************
#define CAN_IF3MSK_MSK_S 0U
#define CAN_IF3MSK_MSK_M 0x1FFFFFFFU // Mask
#define CAN_IF3MSK_MDIR 0x40000000U // Mask Message Direction
#define CAN_IF3MSK_MXTD 0x80000000U // Mask Extended Identifier
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3ARB register
//
//*************************************************************************************************
#define CAN_IF3ARB_ID_S 0U
#define CAN_IF3ARB_ID_M 0x1FFFFFFFU // Message Identifier
#define CAN_IF3ARB_DIR 0x20000000U // Message Direction
#define CAN_IF3ARB_XTD 0x40000000U // Extended Identifier
#define CAN_IF3ARB_MSGVAL 0x80000000U // Message Valid
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3MCTL register
//
//*************************************************************************************************
#define CAN_IF3MCTL_DLC_S 0U
#define CAN_IF3MCTL_DLC_M 0xFU // Data length code
#define CAN_IF3MCTL_EOB 0x80U // End of Block
#define CAN_IF3MCTL_TXRQST 0x100U // Transmit Request
#define CAN_IF3MCTL_RMTEN 0x200U // Remote Enable
#define CAN_IF3MCTL_RXIE 0x400U // Receive Interrupt Enable
#define CAN_IF3MCTL_TXIE 0x800U // Transmit Interrupt Enable
#define CAN_IF3MCTL_UMASK 0x1000U // Use Acceptance Mask
#define CAN_IF3MCTL_INTPND 0x2000U // Interrupt Pending
#define CAN_IF3MCTL_MSGLST 0x4000U // Message Lost
#define CAN_IF3MCTL_NEWDAT 0x8000U // New Data
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3DATA register
//
//*************************************************************************************************
#define CAN_IF3DATA_DATA_0_S 0U
#define CAN_IF3DATA_DATA_0_M 0xFFU // Data Byte 0
#define CAN_IF3DATA_DATA_1_S 8U
#define CAN_IF3DATA_DATA_1_M 0xFF00U // Data Byte 1
#define CAN_IF3DATA_DATA_2_S 16U
#define CAN_IF3DATA_DATA_2_M 0xFF0000U // Data Byte 2
#define CAN_IF3DATA_DATA_3_S 24U
#define CAN_IF3DATA_DATA_3_M 0xFF000000U // Data Byte 3
//*************************************************************************************************
//
// The following are defines for the bit fields in the CAN_IF3DATB register
//
//*************************************************************************************************
#define CAN_IF3DATB_DATA_4_S 0U
#define CAN_IF3DATB_DATA_4_M 0xFFU // Data Byte 4
#define CAN_IF3DATB_DATA_5_S 8U
#define CAN_IF3DATB_DATA_5_M 0xFF00U // Data Byte 5
#define CAN_IF3DATB_DATA_6_S 16U
#define CAN_IF3DATB_DATA_6_M 0xFF0000U // Data Byte 6
#define CAN_IF3DATB_DATA_7_S 24U
#define CAN_IF3DATB_DATA_7_M 0xFF000000U // Data Byte 7
#endif
28379d_P_SFRA/device/driverlib/inc/hw_cla.h
+241
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//###########################################################################
//
// FILE: hw_cla.h
//
// TITLE: Definitions for the CLA registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_CLA_H
#define HW_CLA_H
//*************************************************************************************************
//
// The following are defines for the CLA register offsets
//
//*************************************************************************************************
#ifndef __TMS320C28XX_CLA__
#define CLA_O_MVECT1 0x0U // Task Interrupt Vector
#define CLA_O_MVECT2 0x1U // Task Interrupt Vector
#define CLA_O_MVECT3 0x2U // Task Interrupt Vector
#define CLA_O_MVECT4 0x3U // Task Interrupt Vector
#define CLA_O_MVECT5 0x4U // Task Interrupt Vector
#define CLA_O_MVECT6 0x5U // Task Interrupt Vector
#define CLA_O_MVECT7 0x6U // Task Interrupt Vector
#define CLA_O_MVECT8 0x7U // Task Interrupt Vector
#define CLA_O_MCTL 0x10U // Control Register
#define CLA_O_MIFR 0x20U // Interrupt Flag Register
#define CLA_O_MIOVF 0x21U // Interrupt Overflow Flag Register
#define CLA_O_MIFRC 0x22U // Interrupt Force Register
#define CLA_O_MICLR 0x23U // Interrupt Flag Clear Register
#define CLA_O_MICLROVF 0x24U // Interrupt Overflow Flag Clear Register
#define CLA_O_MIER 0x25U // Interrupt Enable Register
#define CLA_O_MIRUN 0x26U // Interrupt Run Status Register
#define CLA_O_MPC 0x28U // CLA Program Counter
#define CLA_O_MAR0 0x2AU // CLA Auxiliary Register 0
#define CLA_O_MAR1 0x2BU // CLA Auxiliary Register 1
#define CLA_O_MSTF 0x2EU // CLA Floating-Point Status Register
#define CLA_O_MR0 0x30U // CLA Floating-Point Result Register 0
#define CLA_O_MR1 0x34U // CLA Floating-Point Result Register 1
#define CLA_O_MR2 0x38U // CLA Floating-Point Result Register 2
#define CLA_O_MR3 0x3CU // CLA Floating-Point Result Register 3
#endif
#ifdef __TMS320C28XX_CLA__
#define CLA_O_SOFTINTEN 0x0U // CLA Software Interrupt Enable Register
#define CLA_O_SOFTINTFRC 0x2U // CLA Software Interrupt Force Register
#endif
#ifndef __TMS320C28XX_CLA__
//*************************************************************************************************
//
// The following are defines for the bit fields in the MCTL register
//
//*************************************************************************************************
#define CLA_MCTL_HARDRESET 0x1U // Hard Reset
#define CLA_MCTL_SOFTRESET 0x2U // Soft Reset
#define CLA_MCTL_IACKE 0x4U // IACK enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the MIFR register
//
//*************************************************************************************************
#define CLA_MIFR_INT1 0x1U // Task 1 Interrupt Flag
#define CLA_MIFR_INT2 0x2U // Task 2 Interrupt Flag
#define CLA_MIFR_INT3 0x4U // Task 3 Interrupt Flag
#define CLA_MIFR_INT4 0x8U // Task 4 Interrupt Flag
#define CLA_MIFR_INT5 0x10U // Task 5 Interrupt Flag
#define CLA_MIFR_INT6 0x20U // Task 6 Interrupt Flag
#define CLA_MIFR_INT7 0x40U // Task 7 Interrupt Flag
#define CLA_MIFR_INT8 0x80U // Task 8 Interrupt Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the MIOVF register
//
//*************************************************************************************************
#define CLA_MIOVF_INT1 0x1U // Task 1 Interrupt Overflow Flag
#define CLA_MIOVF_INT2 0x2U // Task 2 Interrupt Overflow Flag
#define CLA_MIOVF_INT3 0x4U // Task 3 Interrupt Overflow Flag
#define CLA_MIOVF_INT4 0x8U // Task 4 Interrupt Overflow Flag
#define CLA_MIOVF_INT5 0x10U // Task 5 Interrupt Overflow Flag
#define CLA_MIOVF_INT6 0x20U // Task 6 Interrupt Overflow Flag
#define CLA_MIOVF_INT7 0x40U // Task 7 Interrupt Overflow Flag
#define CLA_MIOVF_INT8 0x80U // Task 8 Interrupt Overflow Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the MIFRC register
//
//*************************************************************************************************
#define CLA_MIFRC_INT1 0x1U // Task 1 Interrupt Force
#define CLA_MIFRC_INT2 0x2U // Task 2 Interrupt Force
#define CLA_MIFRC_INT3 0x4U // Task 3 Interrupt Force
#define CLA_MIFRC_INT4 0x8U // Task 4 Interrupt Force
#define CLA_MIFRC_INT5 0x10U // Task 5 Interrupt Force
#define CLA_MIFRC_INT6 0x20U // Task 6 Interrupt Force
#define CLA_MIFRC_INT7 0x40U // Task 7 Interrupt Force
#define CLA_MIFRC_INT8 0x80U // Task 8 Interrupt Force
//*************************************************************************************************
//
// The following are defines for the bit fields in the MICLR register
//
//*************************************************************************************************
#define CLA_MICLR_INT1 0x1U // Task 1 Interrupt Flag Clear
#define CLA_MICLR_INT2 0x2U // Task 2 Interrupt Flag Clear
#define CLA_MICLR_INT3 0x4U // Task 3 Interrupt Flag Clear
#define CLA_MICLR_INT4 0x8U // Task 4 Interrupt Flag Clear
#define CLA_MICLR_INT5 0x10U // Task 5 Interrupt Flag Clear
#define CLA_MICLR_INT6 0x20U // Task 6 Interrupt Flag Clear
#define CLA_MICLR_INT7 0x40U // Task 7 Interrupt Flag Clear
#define CLA_MICLR_INT8 0x80U // Task 8 Interrupt Flag Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the MICLROVF register
//
//*************************************************************************************************
#define CLA_MICLROVF_INT1 0x1U // Task 1 Interrupt Overflow Flag Clear
#define CLA_MICLROVF_INT2 0x2U // Task 2 Interrupt Overflow Flag Clear
#define CLA_MICLROVF_INT3 0x4U // Task 3 Interrupt Overflow Flag Clear
#define CLA_MICLROVF_INT4 0x8U // Task 4 Interrupt Overflow Flag Clear
#define CLA_MICLROVF_INT5 0x10U // Task 5 Interrupt Overflow Flag Clear
#define CLA_MICLROVF_INT6 0x20U // Task 6 Interrupt Overflow Flag Clear
#define CLA_MICLROVF_INT7 0x40U // Task 7 Interrupt Overflow Flag Clear
#define CLA_MICLROVF_INT8 0x80U // Task 8 Interrupt Overflow Flag Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the MIER register
//
//*************************************************************************************************
#define CLA_MIER_INT1 0x1U // Task 1 Interrupt Enable
#define CLA_MIER_INT2 0x2U // Task 2 Interrupt Enable
#define CLA_MIER_INT3 0x4U // Task 3 Interrupt Enable
#define CLA_MIER_INT4 0x8U // Task 4 Interrupt Enable
#define CLA_MIER_INT5 0x10U // Task 5 Interrupt Enable
#define CLA_MIER_INT6 0x20U // Task 6 Interrupt Enable
#define CLA_MIER_INT7 0x40U // Task 7 Interrupt Enable
#define CLA_MIER_INT8 0x80U // Task 8 Interrupt Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the MIRUN register
//
//*************************************************************************************************
#define CLA_MIRUN_INT1 0x1U // Task 1 Run Status
#define CLA_MIRUN_INT2 0x2U // Task 2 Run Status
#define CLA_MIRUN_INT3 0x4U // Task 3 Run Status
#define CLA_MIRUN_INT4 0x8U // Task 4 Run Status
#define CLA_MIRUN_INT5 0x10U // Task 5 Run Status
#define CLA_MIRUN_INT6 0x20U // Task 6 Run Status
#define CLA_MIRUN_INT7 0x40U // Task 7 Run Status
#define CLA_MIRUN_INT8 0x80U // Task 8 Run Status
//*************************************************************************************************
//
// The following are defines for the bit fields in the _MSTF register
//
//*************************************************************************************************
#define CLA_MSTF_LVF 0x1U // Latched Overflow Flag
#define CLA_MSTF_LUF 0x2U // Latched Underflow Flag
#define CLA_MSTF_NF 0x4U // Negative Float Flag
#define CLA_MSTF_ZF 0x8U // Zero Float Flag
#define CLA_MSTF_TF 0x40U // Test Flag
#define CLA_MSTF_RNDF32 0x200U // Round 32-bit Floating-Point Mode
#define CLA_MSTF_MEALLOW 0x800U // MEALLOW Status
#define CLA_MSTF_RPC_S 12U
#define CLA_MSTF_RPC_M 0xFFFF000U // Return PC
#endif
#ifdef __TMS320C28XX_CLA__
//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTINTEN register
//
//*************************************************************************************************
#define CLA_SOFTINTEN_TASK1 0x1U // Configure Software Interrupt or End of Task interrupt.
#define CLA_SOFTINTEN_TASK2 0x2U // Configure Software Interrupt or End of Task interrupt.
#define CLA_SOFTINTEN_TASK3 0x4U // Configure Software Interrupt or End of Task interrupt.
#define CLA_SOFTINTEN_TASK4 0x8U // Configure Software Interrupt or End of Task interrupt.
#define CLA_SOFTINTEN_TASK5 0x10U // Configure Software Interrupt or End of Task interrupt.
#define CLA_SOFTINTEN_TASK6 0x20U // Configure Software Interrupt or End of Task interrupt.
#define CLA_SOFTINTEN_TASK7 0x40U // Configure Software Interrupt or End of Task interrupt.
#define CLA_SOFTINTEN_TASK8 0x80U // Configure Software Interrupt or End of Task interrupt.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SOFTINTFRC register
//
//*************************************************************************************************
#define CLA_SOFTINTFRC_TASK1 0x1U // Force CLA software interrupt for the corresponding task.
#define CLA_SOFTINTFRC_TASK2 0x2U // Force CLA software interrupt for the corresponding task.
#define CLA_SOFTINTFRC_TASK3 0x4U // Force CLA software interrupt for the corresponding task.
#define CLA_SOFTINTFRC_TASK4 0x8U // Force CLA software interrupt for the corresponding task.
#define CLA_SOFTINTFRC_TASK5 0x10U // Force CLA software interrupt for the corresponding task.
#define CLA_SOFTINTFRC_TASK6 0x20U // Force CLA software interrupt for the corresponding task.
#define CLA_SOFTINTFRC_TASK7 0x40U // Force CLA software interrupt for the corresponding task.
#define CLA_SOFTINTFRC_TASK8 0x80U // Force CLA software interrupt for the corresponding task.
#endif
#endif
28379d_P_SFRA/device/driverlib/inc/hw_clb.h
+661
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//###########################################################################
//
// FILE: hw_clb.h
//
// TITLE: Definitions for the CLB registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_CLB_H
#define HW_CLB_H
//*************************************************************************************************
//
// The following are defines for the CLB register offsets
//
//*************************************************************************************************
#define CLB_O_COUNT_RESET 0x2U // Counter Block RESET
#define CLB_O_COUNT_MODE_1 0x4U // Counter Block MODE_1
#define CLB_O_COUNT_MODE_0 0x6U // Counter Block MODE_0
#define CLB_O_COUNT_EVENT 0x8U // Counter Block EVENT
#define CLB_O_FSM_EXTRA_IN0 0xAU // FSM Extra EXT_IN0
#define CLB_O_FSM_EXTERNAL_IN0 0xCU // FSM EXT_IN0
#define CLB_O_FSM_EXTERNAL_IN1 0xEU // FSM_EXT_IN1
#define CLB_O_FSM_EXTRA_IN1 0x10U // FSM Extra_EXT_IN1
#define CLB_O_LUT4_IN0 0x12U // LUT4_0/1/2 IN0 input source
#define CLB_O_LUT4_IN1 0x14U // LUT4_0/1/2 IN1 input source
#define CLB_O_LUT4_IN2 0x16U // LUT4_0/1/2 IN2 input source
#define CLB_O_LUT4_IN3 0x18U // LUT4_0/1/2 IN3 input source
#define CLB_O_FSM_LUT_FN1_0 0x1CU // LUT function for FSM Unit 1 and Unit 0
#define CLB_O_FSM_LUT_FN2 0x1EU // LUT function for FSM Unit 2
#define CLB_O_LUT4_FN1_0 0x20U // LUT function for LUT4 block of Unit 1 and 0
#define CLB_O_LUT4_FN2 0x22U // LUT function for LUT4 block of Unit 2
#define CLB_O_FSM_NEXT_STATE_0 0x24U // FSM Next state equations for Unit 0
#define CLB_O_FSM_NEXT_STATE_1 0x26U // FSM Next state equations for Unit 1
#define CLB_O_FSM_NEXT_STATE_2 0x28U // FSM Next state equations for Unit 2
#define CLB_O_MISC_CONTROL 0x2AU // Static controls for Ctr,FSM
#define CLB_O_OUTPUT_LUT_0 0x2CU // Inp Sel, LUT fns for Out0
#define CLB_O_OUTPUT_LUT_1 0x2EU // Inp Sel, LUT fns for Out1
#define CLB_O_OUTPUT_LUT_2 0x30U // Inp Sel, LUT fns for Out2
#define CLB_O_OUTPUT_LUT_3 0x32U // Inp Sel, LUT fns for Out3
#define CLB_O_OUTPUT_LUT_4 0x34U // Inp Sel, LUT fns for Out4
#define CLB_O_OUTPUT_LUT_5 0x36U // Inp Sel, LUT fns for Out5
#define CLB_O_OUTPUT_LUT_6 0x38U // Inp Sel, LUT fns for Out6
#define CLB_O_OUTPUT_LUT_7 0x3AU // Inp Sel, LUT fns for Out7
#define CLB_O_HLC_EVENT_SEL 0x3CU // Event Selector register for the High Level controller
#define CLB_O_LOAD_EN 0x0U // Global enable & indirect load enable control
#define CLB_O_LOAD_ADDR 0x2U // Indirect address
#define CLB_O_LOAD_DATA 0x4U // Data for indirect loads
#define CLB_O_INPUT_FILTER 0x6U // Input filter selection for both edge detection and
// synchronizers
#define CLB_O_IN_MUX_SEL_0 0x8U // Input selection to decide between Signals and GP register
#define CLB_O_LCL_MUX_SEL_1 0xAU // Input Mux selection for local mux
#define CLB_O_LCL_MUX_SEL_2 0xCU // Input Mux selection for local mux
#define CLB_O_BUF_PTR 0xEU // PUSH and PULL pointers
#define CLB_O_GP_REG 0x10U // General purpose register for CELL inputs
#define CLB_O_OUT_EN 0x12U // CELL output enable register
#define CLB_O_GLBL_MUX_SEL_1 0x14U // Global Mux select for CELL inputs
#define CLB_O_GLBL_MUX_SEL_2 0x16U // Global Mux select for CELL inputs
#define CLB_O_INTR_TAG_REG 0x20U // Interrupt Tag register
#define CLB_O_LOCK 0x22U // Lock control register
#define CLB_O_DBG_R0 0x30U // R0 of High level Controller
#define CLB_O_DBG_R1 0x32U // R1 of High level Controller
#define CLB_O_DBG_R2 0x34U // R2 of High level Controller
#define CLB_O_DBG_R3 0x36U // R3 of High level Controller
#define CLB_O_DBG_C0 0x38U // Count of Unit 0
#define CLB_O_DBG_C1 0x3AU // Count of Unit 1
#define CLB_O_DBG_C2 0x3CU // Count of Unit 2
#define CLB_O_DBG_OUT 0x3EU // Outputs of various units in the Cell
#define CLB_O_PUSH(i) (0x0U + ((i) * 0x2U)) // (0 <= i < 4) CLB_PUSH FIFO Registers (from
// HLC)
#define CLB_O_PULL(i) (0x100U + ((i) * 0x2U)) // (0 <= i < 4) CLB_PULL FIFO Registers (TO HLC)
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_COUNT_RESET register
//
//*************************************************************************************************
#define CLB_COUNT_RESET_SEL_0_S 0U
#define CLB_COUNT_RESET_SEL_0_M 0x1FU // Count Reset Select 0
#define CLB_COUNT_RESET_SEL_1_S 5U
#define CLB_COUNT_RESET_SEL_1_M 0x3E0U // Count Reset Select 1
#define CLB_COUNT_RESET_SEL_2_S 10U
#define CLB_COUNT_RESET_SEL_2_M 0x7C00U // Count Reset Select 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_COUNT_MODE_1 register
//
//*************************************************************************************************
#define CLB_COUNT_MODE_1_SEL_0_S 0U
#define CLB_COUNT_MODE_1_SEL_0_M 0x1FU // Counter mode 1 select 0
#define CLB_COUNT_MODE_1_SEL_1_S 5U
#define CLB_COUNT_MODE_1_SEL_1_M 0x3E0U // Counter mode 1 select 1
#define CLB_COUNT_MODE_1_SEL_2_S 10U
#define CLB_COUNT_MODE_1_SEL_2_M 0x7C00U // Counter mode 1 select 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_COUNT_MODE_0 register
//
//*************************************************************************************************
#define CLB_COUNT_MODE_0_SEL_0_S 0U
#define CLB_COUNT_MODE_0_SEL_0_M 0x1FU // Counter mode 0 select 0
#define CLB_COUNT_MODE_0_SEL_1_S 5U
#define CLB_COUNT_MODE_0_SEL_1_M 0x3E0U // Counter mode 0 select 1
#define CLB_COUNT_MODE_0_SEL_2_S 10U
#define CLB_COUNT_MODE_0_SEL_2_M 0x7C00U // Counter mode 0 select 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_COUNT_EVENT register
//
//*************************************************************************************************
#define CLB_COUNT_EVENT_SEL_0_S 0U
#define CLB_COUNT_EVENT_SEL_0_M 0x1FU // Counter event select 0
#define CLB_COUNT_EVENT_SEL_1_S 5U
#define CLB_COUNT_EVENT_SEL_1_M 0x3E0U // Counter event select 1
#define CLB_COUNT_EVENT_SEL_2_S 10U
#define CLB_COUNT_EVENT_SEL_2_M 0x7C00U // Counter event select 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN0 register
//
//*************************************************************************************************
#define CLB_FSM_EXTRA_IN0_SEL_0_S 0U
#define CLB_FSM_EXTRA_IN0_SEL_0_M 0x1FU // FSM extra ext input select 0
#define CLB_FSM_EXTRA_IN0_SEL_1_S 5U
#define CLB_FSM_EXTRA_IN0_SEL_1_M 0x3E0U // FSM extra ext input select 1
#define CLB_FSM_EXTRA_IN0_SEL_2_S 10U
#define CLB_FSM_EXTRA_IN0_SEL_2_M 0x7C00U // FSM extra ext input select 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN0 register
//
//*************************************************************************************************
#define CLB_FSM_EXTERNAL_IN0_SEL_0_S 0U
#define CLB_FSM_EXTERNAL_IN0_SEL_0_M 0x1FU // FSM EXT_IN0 select input for unit 0
#define CLB_FSM_EXTERNAL_IN0_SEL_1_S 5U
#define CLB_FSM_EXTERNAL_IN0_SEL_1_M 0x3E0U // FSM EXT_IN0 select input for unit 1
#define CLB_FSM_EXTERNAL_IN0_SEL_2_S 10U
#define CLB_FSM_EXTERNAL_IN0_SEL_2_M 0x7C00U // FSM EXT_IN0 select input for unit 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN1 register
//
//*************************************************************************************************
#define CLB_FSM_EXTERNAL_IN1_SEL_0_S 0U
#define CLB_FSM_EXTERNAL_IN1_SEL_0_M 0x1FU // FSM EXT_IN1 select input for unit 0
#define CLB_FSM_EXTERNAL_IN1_SEL_1_S 5U
#define CLB_FSM_EXTERNAL_IN1_SEL_1_M 0x3E0U // FSM EXT_IN1 select input for unit 1
#define CLB_FSM_EXTERNAL_IN1_SEL_2_S 10U
#define CLB_FSM_EXTERNAL_IN1_SEL_2_M 0x7C00U // FSM EXT_IN1 select input for unit 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN1 register
//
//*************************************************************************************************
#define CLB_FSM_EXTRA_IN1_SEL_0_S 0U
#define CLB_FSM_EXTRA_IN1_SEL_0_M 0x1FU // FSM extra ext input select 0
#define CLB_FSM_EXTRA_IN1_SEL_1_S 5U
#define CLB_FSM_EXTRA_IN1_SEL_1_M 0x3E0U // FSM extra ext input select 1
#define CLB_FSM_EXTRA_IN1_SEL_2_S 10U
#define CLB_FSM_EXTRA_IN1_SEL_2_M 0x7C00U // FSM extra ext input select 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LUT4_IN0 register
//
//*************************************************************************************************
#define CLB_LUT4_IN0_SEL_0_S 0U
#define CLB_LUT4_IN0_SEL_0_M 0x1FU // Select inputs for unit 0
#define CLB_LUT4_IN0_SEL_1_S 5U
#define CLB_LUT4_IN0_SEL_1_M 0x3E0U // Select inputs for unit 1
#define CLB_LUT4_IN0_SEL_2_S 10U
#define CLB_LUT4_IN0_SEL_2_M 0x7C00U // Select inputs for unit 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LUT4_IN1 register
//
//*************************************************************************************************
#define CLB_LUT4_IN1_SEL_0_S 0U
#define CLB_LUT4_IN1_SEL_0_M 0x1FU // Select inputs for unit 0
#define CLB_LUT4_IN1_SEL_1_S 5U
#define CLB_LUT4_IN1_SEL_1_M 0x3E0U // Select inputs for unit 1
#define CLB_LUT4_IN1_SEL_2_S 10U
#define CLB_LUT4_IN1_SEL_2_M 0x7C00U // Select inputs for unit 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LUT4_IN2 register
//
//*************************************************************************************************
#define CLB_LUT4_IN2_SEL_0_S 0U
#define CLB_LUT4_IN2_SEL_0_M 0x1FU // Select inputs for unit 0
#define CLB_LUT4_IN2_SEL_1_S 5U
#define CLB_LUT4_IN2_SEL_1_M 0x3E0U // Select inputs for unit 1
#define CLB_LUT4_IN2_SEL_2_S 10U
#define CLB_LUT4_IN2_SEL_2_M 0x7C00U // Select inputs for unit 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LUT4_IN3 register
//
//*************************************************************************************************
#define CLB_LUT4_IN3_SEL_0_S 0U
#define CLB_LUT4_IN3_SEL_0_M 0x1FU // Select inputs for unit 0
#define CLB_LUT4_IN3_SEL_1_S 5U
#define CLB_LUT4_IN3_SEL_1_M 0x3E0U // Select inputs for unit 1
#define CLB_LUT4_IN3_SEL_2_S 10U
#define CLB_LUT4_IN3_SEL_2_M 0x7C00U // Select inputs for unit 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_LUT_FN1_0 register
//
//*************************************************************************************************
#define CLB_FSM_LUT_FN1_0_FN0_S 0U
#define CLB_FSM_LUT_FN1_0_FN0_M 0xFFFFU // FSM LUT output function for unit 0
#define CLB_FSM_LUT_FN1_0_FN1_S 16U
#define CLB_FSM_LUT_FN1_0_FN1_M 0xFFFF0000U // FSM LUT output function for unit 1
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_LUT_FN2 register
//
//*************************************************************************************************
#define CLB_FSM_LUT_FN2_FN1_S 0U
#define CLB_FSM_LUT_FN2_FN1_M 0xFFFFU // FSM LUT output function for unit 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LUT4_FN1_0 register
//
//*************************************************************************************************
#define CLB_LUT4_FN1_0_FN0_S 0U
#define CLB_LUT4_FN1_0_FN0_M 0xFFFFU // LUT4 output function for unit 0
#define CLB_LUT4_FN1_0_FN1_S 16U
#define CLB_LUT4_FN1_0_FN1_M 0xFFFF0000U // LUT4 output function for unit 1
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LUT4_FN2 register
//
//*************************************************************************************************
#define CLB_LUT4_FN2_FN1_S 0U
#define CLB_LUT4_FN2_FN1_M 0xFFFFU // LUT4 output function for unit 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_0 register
//
//*************************************************************************************************
#define CLB_FSM_NEXT_STATE_0_S0_S 0U
#define CLB_FSM_NEXT_STATE_0_S0_M 0xFFFFU // FSM next state function for S0
#define CLB_FSM_NEXT_STATE_0_S1_S 16U
#define CLB_FSM_NEXT_STATE_0_S1_M 0xFFFF0000U // FSM next state function for S1
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_1 register
//
//*************************************************************************************************
#define CLB_FSM_NEXT_STATE_1_S0_S 0U
#define CLB_FSM_NEXT_STATE_1_S0_M 0xFFFFU // FSM next state function for S0
#define CLB_FSM_NEXT_STATE_1_S1_S 16U
#define CLB_FSM_NEXT_STATE_1_S1_M 0xFFFF0000U // FSM next state function for S1
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_2 register
//
//*************************************************************************************************
#define CLB_FSM_NEXT_STATE_2_S0_S 0U
#define CLB_FSM_NEXT_STATE_2_S0_M 0xFFFFU // FSM next state function for S0
#define CLB_FSM_NEXT_STATE_2_S1_S 16U
#define CLB_FSM_NEXT_STATE_2_S1_M 0xFFFF0000U // FSM next state function for S1
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_MISC_CONTROL register
//
//*************************************************************************************************
#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_0 0x1U // Add/Shift for counter 0
#define CLB_MISC_CONTROL_COUNT_DIR_0 0x2U // Direction for counter 0
#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_0 0x4U // Event control for counter 0
#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_1 0x8U // Add/Shift for counter 1
#define CLB_MISC_CONTROL_COUNT_DIR_1 0x10U // Direction for counter 1
#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_1 0x20U // Event control for counter 1
#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_2 0x40U // Add/Shift for counter 2
#define CLB_MISC_CONTROL_COUNT_DIR_2 0x80U // Direction for counter 2
#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_2 0x100U // Event control for counter 2
#define CLB_MISC_CONTROL_COUNT_SERIALIZER_0 0x200U // Serializer enable 0
#define CLB_MISC_CONTROL_COUNT_SERIALIZER_1 0x400U // Serializer enable 1
#define CLB_MISC_CONTROL_COUNT_SERIALIZER_2 0x800U // Serializer enable 2
#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_0 0x1000U // FSM extra_sel0 for 0
#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_0 0x2000U // FSM extra_sel1 for 0
#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_1 0x4000U // FSM extra_sel0 for 1
#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_1 0x8000U // FSM extra_sel1 for 1
#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_2 0x10000U // FSM extra_sel0 for 2
#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_2 0x20000U // FSM extra_sel1 for 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_0 register
//
//*************************************************************************************************
#define CLB_OUTPUT_LUT_0_IN0_S 0U
#define CLB_OUTPUT_LUT_0_IN0_M 0x1FU // Select value for IN0 of output LUT
#define CLB_OUTPUT_LUT_0_IN1_S 5U
#define CLB_OUTPUT_LUT_0_IN1_M 0x3E0U // Select value for IN1 of output LUT
#define CLB_OUTPUT_LUT_0_IN2_S 10U
#define CLB_OUTPUT_LUT_0_IN2_M 0x7C00U // Select value for IN2 of output LUT
#define CLB_OUTPUT_LUT_0_FN_S 15U
#define CLB_OUTPUT_LUT_0_FN_M 0x7F8000U // Output function for output LUT
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_1 register
//
//*************************************************************************************************
#define CLB_OUTPUT_LUT_1_IN0_S 0U
#define CLB_OUTPUT_LUT_1_IN0_M 0x1FU // Select value for IN0 of output LUT
#define CLB_OUTPUT_LUT_1_IN1_S 5U
#define CLB_OUTPUT_LUT_1_IN1_M 0x3E0U // Select value for IN1 of output LUT
#define CLB_OUTPUT_LUT_1_IN2_S 10U
#define CLB_OUTPUT_LUT_1_IN2_M 0x7C00U // Select value for IN2 of output LUT
#define CLB_OUTPUT_LUT_1_FN_S 15U
#define CLB_OUTPUT_LUT_1_FN_M 0x7F8000U // Output function for output LUT
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_2 register
//
//*************************************************************************************************
#define CLB_OUTPUT_LUT_2_IN0_S 0U
#define CLB_OUTPUT_LUT_2_IN0_M 0x1FU // Select value for IN0 of output LUT
#define CLB_OUTPUT_LUT_2_IN1_S 5U
#define CLB_OUTPUT_LUT_2_IN1_M 0x3E0U // Select value for IN1 of output LUT
#define CLB_OUTPUT_LUT_2_IN2_S 10U
#define CLB_OUTPUT_LUT_2_IN2_M 0x7C00U // Select value for IN2 of output LUT
#define CLB_OUTPUT_LUT_2_FN_S 15U
#define CLB_OUTPUT_LUT_2_FN_M 0x7F8000U // Output function for output LUT
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_3 register
//
//*************************************************************************************************
#define CLB_OUTPUT_LUT_3_IN0_S 0U
#define CLB_OUTPUT_LUT_3_IN0_M 0x1FU // Select value for IN0 of output LUT
#define CLB_OUTPUT_LUT_3_IN1_S 5U
#define CLB_OUTPUT_LUT_3_IN1_M 0x3E0U // Select value for IN1 of output LUT
#define CLB_OUTPUT_LUT_3_IN2_S 10U
#define CLB_OUTPUT_LUT_3_IN2_M 0x7C00U // Select value for IN2 of output LUT
#define CLB_OUTPUT_LUT_3_FN_S 15U
#define CLB_OUTPUT_LUT_3_FN_M 0x7F8000U // Output function for output LUT
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_4 register
//
//*************************************************************************************************
#define CLB_OUTPUT_LUT_4_IN0_S 0U
#define CLB_OUTPUT_LUT_4_IN0_M 0x1FU // Select value for IN0 of output LUT
#define CLB_OUTPUT_LUT_4_IN1_S 5U
#define CLB_OUTPUT_LUT_4_IN1_M 0x3E0U // Select value for IN1 of output LUT
#define CLB_OUTPUT_LUT_4_IN2_S 10U
#define CLB_OUTPUT_LUT_4_IN2_M 0x7C00U // Select value for IN2 of output LUT
#define CLB_OUTPUT_LUT_4_FN_S 15U
#define CLB_OUTPUT_LUT_4_FN_M 0x7F8000U // Output function for output LUT
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_5 register
//
//*************************************************************************************************
#define CLB_OUTPUT_LUT_5_IN0_S 0U
#define CLB_OUTPUT_LUT_5_IN0_M 0x1FU // Select value for IN0 of output LUT
#define CLB_OUTPUT_LUT_5_IN1_S 5U
#define CLB_OUTPUT_LUT_5_IN1_M 0x3E0U // Select value for IN1 of output LUT
#define CLB_OUTPUT_LUT_5_IN2_S 10U
#define CLB_OUTPUT_LUT_5_IN2_M 0x7C00U // Select value for IN2 of output LUT
#define CLB_OUTPUT_LUT_5_FN_S 15U
#define CLB_OUTPUT_LUT_5_FN_M 0x7F8000U // Output function for output LUT
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_6 register
//
//*************************************************************************************************
#define CLB_OUTPUT_LUT_6_IN0_S 0U
#define CLB_OUTPUT_LUT_6_IN0_M 0x1FU // Select value for IN0 of output LUT
#define CLB_OUTPUT_LUT_6_IN1_S 5U
#define CLB_OUTPUT_LUT_6_IN1_M 0x3E0U // Select value for IN1 of output LUT
#define CLB_OUTPUT_LUT_6_IN2_S 10U
#define CLB_OUTPUT_LUT_6_IN2_M 0x7C00U // Select value for IN2 of output LUT
#define CLB_OUTPUT_LUT_6_FN_S 15U
#define CLB_OUTPUT_LUT_6_FN_M 0x7F8000U // Output function for output LUT
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_OUTPUT_LUT_7 register
//
//*************************************************************************************************
#define CLB_OUTPUT_LUT_7_IN0_S 0U
#define CLB_OUTPUT_LUT_7_IN0_M 0x1FU // Select value for IN0 of output LUT
#define CLB_OUTPUT_LUT_7_IN1_S 5U
#define CLB_OUTPUT_LUT_7_IN1_M 0x3E0U // Select value for IN1 of output LUT
#define CLB_OUTPUT_LUT_7_IN2_S 10U
#define CLB_OUTPUT_LUT_7_IN2_M 0x7C00U // Select value for IN2 of output LUT
#define CLB_OUTPUT_LUT_7_FN_S 15U
#define CLB_OUTPUT_LUT_7_FN_M 0x7F8000U // Output function for output LUT
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_HLC_EVENT_SEL register
//
//*************************************************************************************************
#define CLB_HLC_EVENT_SEL_EVENT0_SEL_S 0U
#define CLB_HLC_EVENT_SEL_EVENT0_SEL_M 0x1FU // Event Select 0
#define CLB_HLC_EVENT_SEL_EVENT1_SEL_S 5U
#define CLB_HLC_EVENT_SEL_EVENT1_SEL_M 0x3E0U // Event Select 1
#define CLB_HLC_EVENT_SEL_EVENT2_SEL_S 10U
#define CLB_HLC_EVENT_SEL_EVENT2_SEL_M 0x7C00U // Event Select 2
#define CLB_HLC_EVENT_SEL_EVENT3_SEL_S 15U
#define CLB_HLC_EVENT_SEL_EVENT3_SEL_M 0xF8000U // Event Select 3
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LOAD_EN register
//
//*************************************************************************************************
#define CLB_LOAD_EN_LOAD_EN 0x1U // Load Enable
#define CLB_LOAD_EN_GLOBAL_EN 0x2U // Global Enable
#define CLB_LOAD_EN_STOP 0x4U // Debug stop control
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LOAD_ADDR register
//
//*************************************************************************************************
#define CLB_LOAD_ADDR_ADDR_S 0U
#define CLB_LOAD_ADDR_ADDR_M 0x3FU // Indirect Address
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_INPUT_FILTER register
//
//*************************************************************************************************
#define CLB_INPUT_FILTER_FIN0_S 0U
#define CLB_INPUT_FILTER_FIN0_M 0x3U // Input filter control 0
#define CLB_INPUT_FILTER_FIN1_S 2U
#define CLB_INPUT_FILTER_FIN1_M 0xCU // Input filter control 1
#define CLB_INPUT_FILTER_FIN2_S 4U
#define CLB_INPUT_FILTER_FIN2_M 0x30U // Input filter control 2
#define CLB_INPUT_FILTER_FIN3_S 6U
#define CLB_INPUT_FILTER_FIN3_M 0xC0U // Input filter control 3
#define CLB_INPUT_FILTER_FIN4_S 8U
#define CLB_INPUT_FILTER_FIN4_M 0x300U // Input filter control 4
#define CLB_INPUT_FILTER_FIN5_S 10U
#define CLB_INPUT_FILTER_FIN5_M 0xC00U // Input filter control 5
#define CLB_INPUT_FILTER_FIN6_S 12U
#define CLB_INPUT_FILTER_FIN6_M 0x3000U // Input filter control 6
#define CLB_INPUT_FILTER_FIN7_S 14U
#define CLB_INPUT_FILTER_FIN7_M 0xC000U // Input filter control 7
#define CLB_INPUT_FILTER_SYNC0 0x10000U // Synchronizer control 0
#define CLB_INPUT_FILTER_SYNC1 0x20000U // Synchronizer control 1
#define CLB_INPUT_FILTER_SYNC2 0x40000U // Synchronizer control 2
#define CLB_INPUT_FILTER_SYNC3 0x80000U // Synchronizer control 3
#define CLB_INPUT_FILTER_SYNC4 0x100000U // Synchronizer control 4
#define CLB_INPUT_FILTER_SYNC5 0x200000U // Synchronizer control 5
#define CLB_INPUT_FILTER_SYNC6 0x400000U // Synchronizer control 6
#define CLB_INPUT_FILTER_SYNC7 0x800000U // Synchronizer control 7
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_IN_MUX_SEL_0 register
//
//*************************************************************************************************
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_0 0x1U // Select GP register 0
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_1 0x2U // Select GP register 1
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_2 0x4U // Select GP register 2
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_3 0x8U // Select GP register 3
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_4 0x10U // Select GP register 4
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_5 0x20U // Select GP register 5
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_6 0x40U // Select GP register 6
#define CLB_IN_MUX_SEL_0_SEL_GP_IN_7 0x80U // Select GP register 7
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_1 register
//
//*************************************************************************************************
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_S 0U
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M 0x1FU // Local Mux select 0
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S 5U
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_M 0x3E0U // Local Mux select 1
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_2_S 10U
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_2_M 0x7C00U // Local Mux select 2
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_3_S 15U
#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_3_M 0xF8000U // Local Mux select 3
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_2 register
//
//*************************************************************************************************
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_4_S 0U
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_4_M 0x1FU // Local Mux select 4
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_5_S 5U
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_5_M 0x3E0U // Local Mux select 5
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_6_S 10U
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_6_M 0x7C00U // Local Mux select 6
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_7_S 15U
#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_7_M 0xF8000U // Local Mux select 7
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_BUF_PTR register
//
//*************************************************************************************************
#define CLB_BUF_PTR_PULL_S 0U
#define CLB_BUF_PTR_PULL_M 0xFFU // Data pointer for pull
#define CLB_BUF_PTR_PUSH_S 16U
#define CLB_BUF_PTR_PUSH_M 0xFF0000U // Data pointer for pull
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_GP_REG register
//
//*************************************************************************************************
#define CLB_GP_REG_REG_S 0U
#define CLB_GP_REG_REG_M 0xFFU // General Purpose bit register
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_1 register
//
//*************************************************************************************************
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_S 0U
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M 0x7FU // Global Mux select 0
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S 7U
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_M 0x3F80U // Global Mux select 1
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_2_S 14U
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_2_M 0x1FC000U // Global Mux select 2
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_3_S 21U
#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_3_M 0xFE00000U // Global Mux select 3
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_2 register
//
//*************************************************************************************************
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_4_S 0U
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_4_M 0x7FU // Global Mux select 4
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_5_S 7U
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_5_M 0x3F80U // Global Mux select 5
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_6_S 14U
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_6_M 0x1FC000U // Global Mux select 6
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_7_S 21U
#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_7_M 0xFE00000U // Global Mux select 7
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_INTR_TAG_REG register
//
//*************************************************************************************************
#define CLB_INTR_TAG_REG_TAG_S 0U
#define CLB_INTR_TAG_REG_TAG_M 0x3FU // Interrupt tag
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_LOCK register
//
//*************************************************************************************************
#define CLB_LOCK_LOCK 0x1U // LOCK enable
#define CLB_LOCK_KEY_S 16U
#define CLB_LOCK_KEY_M 0xFFFF0000U // Key for enabling write
//*************************************************************************************************
//
// The following are defines for the bit fields in the CLB_DBG_OUT register
//
//*************************************************************************************************
#define CLB_DBG_OUT_COUNT0_MATCH2 0x2U // COUNT_MATCH2 UNIT 0
#define CLB_DBG_OUT_COUNT0_ZERO 0x4U // COUNT_ZERO UNIT 0
#define CLB_DBG_OUT_COUNT0_MATCH1 0x8U // COUNT_MATCH1 UNIT 0
#define CLB_DBG_OUT_FSM0_S0 0x10U // FSM_S0 UNIT 0
#define CLB_DBG_OUT_FSM0_S1 0x20U // FSM_S1 UNIT 0
#define CLB_DBG_OUT_FSM0_LUTOUT 0x40U // FSM_LUT_OUT UNIT 0
#define CLB_DBG_OUT_LUT40_OUT 0x80U // LUT4_OUT UNIT 0
#define CLB_DBG_OUT_COUNT1_MATCH2 0x200U // COUNT_MATCH2 UNIT 1
#define CLB_DBG_OUT_COUNT1_ZERO 0x400U // COUNT_ZERO UNIT 1
#define CLB_DBG_OUT_COUNT1_MATCH1 0x800U // COUNT_MATCH1 UNIT 1
#define CLB_DBG_OUT_FSM1_S0 0x1000U // FSM_S0 UNIT 1
#define CLB_DBG_OUT_FSM1_S1 0x2000U // FSM_S1 UNIT 1
#define CLB_DBG_OUT_FSM1_LUTOUT 0x4000U // FSM_LUT_OUT UNIT 1
#define CLB_DBG_OUT_LUT41_OUT 0x8000U // LUT4_OUT UNIT 1
#define CLB_DBG_OUT_COUNT2_MATCH2 0x20000U // COUNT_MATCH2 UNIT 2
#define CLB_DBG_OUT_COUNT2_ZERO 0x40000U // COUNT_ZERO UNIT 2
#define CLB_DBG_OUT_COUNT2_MATCH1 0x80000U // COUNT_MATCH1 UNIT 2
#define CLB_DBG_OUT_FSM2_S0 0x100000U // FSM_S0 UNIT 2
#define CLB_DBG_OUT_FSM2_S1 0x200000U // FSM_S1 UNIT 2
#define CLB_DBG_OUT_FSM2_LUTOUT 0x400000U // FSM_LUT_OUT UNIT 2
#define CLB_DBG_OUT_LUT42_OUT 0x800000U // LUT4_OUT UNIT 2
#define CLB_DBG_OUT_OUT0 0x1000000U // CELL Output 0
#define CLB_DBG_OUT_OUT1 0x2000000U // CELL Output 1
#define CLB_DBG_OUT_OUT2 0x4000000U // CELL Output 2
#define CLB_DBG_OUT_OUT3 0x8000000U // CELL Output 3
#define CLB_DBG_OUT_OUT4 0x10000000U // CELL Output 4
#define CLB_DBG_OUT_OUT5 0x20000000U // CELL Output 5
#define CLB_DBG_OUT_OUT6 0x40000000U // CELL Output 6
#define CLB_DBG_OUT_OUT7 0x80000000U // CELL Output 7
#endif
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//###########################################################################
//
// FILE: hw_cmpss.h
//
// TITLE: Definitions for the CMPSS registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_CMPSS_H
#define HW_CMPSS_H
//*************************************************************************************************
//
// The following are defines for the CMPSS register offsets
//
//*************************************************************************************************
#define CMPSS_O_COMPCTL 0x0U // CMPSS Comparator Control Register
#define CMPSS_O_COMPHYSCTL 0x1U // CMPSS Comparator Hysteresis Control Register
#define CMPSS_O_COMPSTS 0x2U // CMPSS Comparator Status Register
#define CMPSS_O_COMPSTSCLR 0x3U // CMPSS Comparator Status Clear Register
#define CMPSS_O_COMPDACCTL 0x4U // CMPSS DAC Control Register
#define CMPSS_O_DACHVALS 0x6U // CMPSS High DAC Value Shadow Register
#define CMPSS_O_DACHVALA 0x7U // CMPSS High DAC Value Active Register
#define CMPSS_O_RAMPMAXREFA 0x8U // CMPSS Ramp Max Reference Active Register
#define CMPSS_O_RAMPMAXREFS 0xAU // CMPSS Ramp Max Reference Shadow Register
#define CMPSS_O_RAMPDECVALA 0xCU // CMPSS Ramp Decrement Value Active Register
#define CMPSS_O_RAMPDECVALS 0xEU // CMPSS Ramp Decrement Value Shadow Register
#define CMPSS_O_RAMPSTS 0x10U // CMPSS Ramp Status Register
#define CMPSS_O_DACLVALS 0x12U // CMPSS Low DAC Value Shadow Register
#define CMPSS_O_DACLVALA 0x13U // CMPSS Low DAC Value Active Register
#define CMPSS_O_RAMPDLYA 0x14U // CMPSS Ramp Delay Active Register
#define CMPSS_O_RAMPDLYS 0x15U // CMPSS Ramp Delay Shadow Register
#define CMPSS_O_CTRIPLFILCTL 0x16U // CTRIPL Filter Control Register
#define CMPSS_O_CTRIPLFILCLKCTL 0x17U // CTRIPL Filter Clock Control Register
#define CMPSS_O_CTRIPHFILCTL 0x18U // CTRIPH Filter Control Register
#define CMPSS_O_CTRIPHFILCLKCTL 0x19U // CTRIPH Filter Clock Control Register
#define CMPSS_O_COMPLOCK 0x1AU // CMPSS Lock Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPCTL register
//
//*************************************************************************************************
#define CMPSS_COMPCTL_COMPHSOURCE 0x1U // High Comparator Source Select
#define CMPSS_COMPCTL_COMPHINV 0x2U // High Comparator Invert Select
#define CMPSS_COMPCTL_CTRIPHSEL_S 2U
#define CMPSS_COMPCTL_CTRIPHSEL_M 0xCU // High Comparator Trip Select
#define CMPSS_COMPCTL_CTRIPOUTHSEL_S 4U
#define CMPSS_COMPCTL_CTRIPOUTHSEL_M 0x30U // High Comparator Trip Output Select
#define CMPSS_COMPCTL_ASYNCHEN 0x40U // High Comparator Asynchronous Path Enable
#define CMPSS_COMPCTL_COMPLSOURCE 0x100U // Low Comparator Source Select
#define CMPSS_COMPCTL_COMPLINV 0x200U // Low Comparator Invert Select
#define CMPSS_COMPCTL_CTRIPLSEL_S 10U
#define CMPSS_COMPCTL_CTRIPLSEL_M 0xC00U // Low Comparator Trip Select
#define CMPSS_COMPCTL_CTRIPOUTLSEL_S 12U
#define CMPSS_COMPCTL_CTRIPOUTLSEL_M 0x3000U // Low Comparator Trip Output Select
#define CMPSS_COMPCTL_ASYNCLEN 0x4000U // Low Comparator Asynchronous Path Enable
#define CMPSS_COMPCTL_COMPDACE 0x8000U // Comparator/DAC Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPHYSCTL register
//
//*************************************************************************************************
#define CMPSS_COMPHYSCTL_COMPHYS_S 0U
#define CMPSS_COMPHYSCTL_COMPHYS_M 0x7U // Comparator Hysteresis Trim
//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPSTS register
//
//*************************************************************************************************
#define CMPSS_COMPSTS_COMPHSTS 0x1U // High Comparator Status
#define CMPSS_COMPSTS_COMPHLATCH 0x2U // High Comparator Latched Status
#define CMPSS_COMPSTS_COMPLSTS 0x100U // Low Comparator Status
#define CMPSS_COMPSTS_COMPLLATCH 0x200U // Low Comparator Latched Status
//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPSTSCLR register
//
//*************************************************************************************************
#define CMPSS_COMPSTSCLR_HLATCHCLR 0x2U // High Comparator Latched Status Clear
#define CMPSS_COMPSTSCLR_HSYNCCLREN 0x4U // High Comparator EPWMSYNCPER Clear Enable
#define CMPSS_COMPSTSCLR_LLATCHCLR 0x200U // Low Comparator Latched Status Clear
#define CMPSS_COMPSTSCLR_LSYNCCLREN 0x400U // Low Comparator EPWMSYNCPER Clear Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPDACCTL register
//
//*************************************************************************************************
#define CMPSS_COMPDACCTL_DACSOURCE 0x1U // DAC Source Control
#define CMPSS_COMPDACCTL_RAMPSOURCE_S 1U
#define CMPSS_COMPDACCTL_RAMPSOURCE_M 0x1EU // Ramp Generator Source Control
#define CMPSS_COMPDACCTL_SELREF 0x20U // DAC Reference Select
#define CMPSS_COMPDACCTL_RAMPLOADSEL 0x40U // Ramp Load Select
#define CMPSS_COMPDACCTL_SWLOADSEL 0x80U // Software Load Select
#define CMPSS_COMPDACCTL_FREESOFT_S 14U
#define CMPSS_COMPDACCTL_FREESOFT_M 0xC000U // Free/Soft Emulation Bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the DACHVALS register
//
//*************************************************************************************************
#define CMPSS_DACHVALS_DACVAL_S 0U
#define CMPSS_DACHVALS_DACVAL_M 0xFFFU // DAC Value Control
//*************************************************************************************************
//
// The following are defines for the bit fields in the DACHVALA register
//
//*************************************************************************************************
#define CMPSS_DACHVALA_DACVAL_S 0U
#define CMPSS_DACHVALA_DACVAL_M 0xFFFU // DAC Value Control
//*************************************************************************************************
//
// The following are defines for the bit fields in the DACLVALS register
//
//*************************************************************************************************
#define CMPSS_DACLVALS_DACVAL_S 0U
#define CMPSS_DACLVALS_DACVAL_M 0xFFFU // DAC Value Control
//*************************************************************************************************
//
// The following are defines for the bit fields in the DACLVALA register
//
//*************************************************************************************************
#define CMPSS_DACLVALA_DACVAL_S 0U
#define CMPSS_DACLVALA_DACVAL_M 0xFFFU // DAC Value Control
//*************************************************************************************************
//
// The following are defines for the bit fields in the RAMPDLYA register
//
//*************************************************************************************************
#define CMPSS_RAMPDLYA_DELAY_S 0U
#define CMPSS_RAMPDLYA_DELAY_M 0x1FFFU // Ramp Delay Value
//*************************************************************************************************
//
// The following are defines for the bit fields in the RAMPDLYS register
//
//*************************************************************************************************
#define CMPSS_RAMPDLYS_DELAY_S 0U
#define CMPSS_RAMPDLYS_DELAY_M 0x1FFFU // Ramp Delay Value
//*************************************************************************************************
//
// The following are defines for the bit fields in the CTRIPLFILCTL register
//
//*************************************************************************************************
#define CMPSS_CTRIPLFILCTL_SAMPWIN_S 4U
#define CMPSS_CTRIPLFILCTL_SAMPWIN_M 0x1F0U // Sample Window
#define CMPSS_CTRIPLFILCTL_THRESH_S 9U
#define CMPSS_CTRIPLFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold
#define CMPSS_CTRIPLFILCTL_FILINIT 0x8000U // Filter Initialization Bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the CTRIPLFILCLKCTL register
//
//*************************************************************************************************
#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_S 0U
#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale
//*************************************************************************************************
//
// The following are defines for the bit fields in the CTRIPHFILCTL register
//
//*************************************************************************************************
#define CMPSS_CTRIPHFILCTL_SAMPWIN_S 4U
#define CMPSS_CTRIPHFILCTL_SAMPWIN_M 0x1F0U // Sample Window
#define CMPSS_CTRIPHFILCTL_THRESH_S 9U
#define CMPSS_CTRIPHFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold
#define CMPSS_CTRIPHFILCTL_FILINIT 0x8000U // Filter Initialization Bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the CTRIPHFILCLKCTL register
//
//*************************************************************************************************
#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_S 0U
#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale
//*************************************************************************************************
//
// The following are defines for the bit fields in the COMPLOCK register
//
//*************************************************************************************************
#define CMPSS_COMPLOCK_COMPCTL 0x1U // COMPCTL Lock
#define CMPSS_COMPLOCK_COMPHYSCTL 0x2U // COMPHYSCTL Lock
#define CMPSS_COMPLOCK_DACCTL 0x4U // DACCTL Lock
#define CMPSS_COMPLOCK_CTRIP 0x8U // CTRIP Lock
#endif
28379d_P_SFRA/device/driverlib/inc/hw_cputimer.h
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//###########################################################################
//
// FILE: hw_cputimer.h
//
// TITLE: Definitions for the CPUTIMER registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_CPUTIMER_H
#define HW_CPUTIMER_H
//*************************************************************************************************
//
// The following are defines for the CPUTIMER register offsets
//
//*************************************************************************************************
#define CPUTIMER_O_TIM 0x0U // CPU-Timer, Counter Register
#define CPUTIMER_O_PRD 0x2U // CPU-Timer, Period Register
#define CPUTIMER_O_TCR 0x4U // CPU-Timer, Control Register
#define CPUTIMER_O_TPR 0x6U // CPU-Timer, Prescale Register
#define CPUTIMER_O_TPRH 0x7U // CPU-Timer, Prescale Register High
//*************************************************************************************************
//
// The following are defines for the bit fields in the TIM register
//
//*************************************************************************************************
#define CPUTIMER_TIM_LSW_S 0U
#define CPUTIMER_TIM_LSW_M 0xFFFFU // CPU-Timer Counter Registers
#define CPUTIMER_TIM_MSW_S 16U
#define CPUTIMER_TIM_MSW_M 0xFFFF0000U // CPU-Timer Counter Registers High
//*************************************************************************************************
//
// The following are defines for the bit fields in the PRD register
//
//*************************************************************************************************
#define CPUTIMER_PRD_LSW_S 0U
#define CPUTIMER_PRD_LSW_M 0xFFFFU // CPU-Timer Period Registers
#define CPUTIMER_PRD_MSW_S 16U
#define CPUTIMER_PRD_MSW_M 0xFFFF0000U // CPU-Timer Period Registers High
//*************************************************************************************************
//
// The following are defines for the bit fields in the TCR register
//
//*************************************************************************************************
#define CPUTIMER_TCR_TSS 0x10U // CPU-Timer stop status bit.
#define CPUTIMER_TCR_TRB 0x20U // Timer reload
#define CPUTIMER_TCR_SOFT 0x400U // Emulation modes
#define CPUTIMER_TCR_FREE 0x800U // Emulation modes
#define CPUTIMER_TCR_TIE 0x4000U // CPU-Timer Interrupt Enable.
#define CPUTIMER_TCR_TIF 0x8000U // CPU-Timer Interrupt Flag.
//*************************************************************************************************
//
// The following are defines for the bit fields in the TPR register
//
//*************************************************************************************************
#define CPUTIMER_TPR_TDDR_S 0U
#define CPUTIMER_TPR_TDDR_M 0xFFU // CPU-Timer Divide-Down.
#define CPUTIMER_TPR_PSC_S 8U
#define CPUTIMER_TPR_PSC_M 0xFF00U // CPU-Timer Prescale Counter.
//*************************************************************************************************
//
// The following are defines for the bit fields in the TPRH register
//
//*************************************************************************************************
#define CPUTIMER_TPRH_TDDRH_S 0U
#define CPUTIMER_TPRH_TDDRH_M 0xFFU // CPU-Timer Divide-Down.
#define CPUTIMER_TPRH_PSCH_S 8U
#define CPUTIMER_TPRH_PSCH_M 0xFF00U // CPU-Timer Prescale Counter.
#endif
28379d_P_SFRA/device/driverlib/inc/hw_dac.h
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//###########################################################################
//
// FILE: hw_dac.h
//
// TITLE: Definitions for the DAC registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_DAC_H
#define HW_DAC_H
//*************************************************************************************************
//
// The following are defines for the DAC register offsets
//
//*************************************************************************************************
#define DAC_O_REV 0x0U // DAC Revision Register
#define DAC_O_CTL 0x1U // DAC Control Register
#define DAC_O_VALA 0x2U // DAC Value Register - Active
#define DAC_O_VALS 0x3U // DAC Value Register - Shadow
#define DAC_O_OUTEN 0x4U // DAC Output Enable Register
#define DAC_O_LOCK 0x5U // DAC Lock Register
#define DAC_O_TRIM 0x6U // DAC Trim Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the DACREV register
//
//*************************************************************************************************
#define DAC_REV_REV_S 0U
#define DAC_REV_REV_M 0xFFU // DAC Revision Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the DACCTL register
//
//*************************************************************************************************
#define DAC_CTL_DACREFSEL 0x1U // DAC Reference Select
#define DAC_CTL_LOADMODE 0x4U // DACVALA Load Mode
#define DAC_CTL_SYNCSEL_S 4U
#define DAC_CTL_SYNCSEL_M 0xF0U // DAC EPWMSYNCPER Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the DACVALA register
//
//*************************************************************************************************
#define DAC_VALA_DACVALA_S 0U
#define DAC_VALA_DACVALA_M 0xFFFU // DAC Active Output Code
//*************************************************************************************************
//
// The following are defines for the bit fields in the DACVALS register
//
//*************************************************************************************************
#define DAC_VALS_DACVALS_S 0U
#define DAC_VALS_DACVALS_M 0xFFFU // DAC Shadow Output Code
//*************************************************************************************************
//
// The following are defines for the bit fields in the DACOUTEN register
//
//*************************************************************************************************
#define DAC_OUTEN_DACOUTEN 0x1U // DAC Output Code
//*************************************************************************************************
//
// The following are defines for the bit fields in the DACLOCK register
//
//*************************************************************************************************
#define DAC_LOCK_DACCTL 0x1U // DAC Control Register Lock
#define DAC_LOCK_DACVAL 0x2U // DAC Value Register Lock
#define DAC_LOCK_DACOUTEN 0x4U // DAC Output Enable Register Lock
#define DAC_LOCK_KEY_S 12U
#define DAC_LOCK_KEY_M 0xF000U // DAC Register Lock Key
//*************************************************************************************************
//
// The following are defines for the bit fields in the DACTRIM register
//
//*************************************************************************************************
#define DAC_TRIM_OFFSET_TRIM_S 0U
#define DAC_TRIM_OFFSET_TRIM_M 0xFFU // DAC Offset Trim
#endif
28379d_P_SFRA/device/driverlib/inc/hw_dcsm.h
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//###########################################################################
//
// FILE: hw_dcsm.h
//
// TITLE: Definitions for the DCSM registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_DCSM_H
#define HW_DCSM_H
//*************************************************************************************************
//
// The following are defines for the DCSM register offsets
//
//*************************************************************************************************
#define DCSM_O_Z1OTP_LINKPOINTER1 0x0U // Zone 1 Link Pointer1 in Z1 OTP
#define DCSM_O_Z1OTP_LINKPOINTER2 0x4U // Zone 1 Link Pointer2 in Z1 OTP
#define DCSM_O_Z1OTP_LINKPOINTER3 0x8U // Zone 1 Link Pointer3 in Z1 OTP
#define DCSM_O_Z1OTP_PSWDLOCK 0x10U // Secure Password Lock in Z1 OTP
#define DCSM_O_Z1OTP_CRCLOCK 0x14U // Secure CRC Lock in Z1 OTP
#define DCSM_O_Z1OTP_BOOTCTRL 0x1EU // Boot Mode in Z1 OTP
#define DCSM_O_Z2OTP_LINKPOINTER1 0x0U // Zone 2 Link Pointer1 in Z2 OTP
#define DCSM_O_Z2OTP_LINKPOINTER2 0x4U // Zone 2 Link Pointer2 in Z2 OTP
#define DCSM_O_Z2OTP_LINKPOINTER3 0x8U // Zone 2 Link Pointer3 in Z2 OTP
#define DCSM_O_Z2OTP_PSWDLOCK 0x10U // Secure Password Lock in Z2 OTP
#define DCSM_O_Z2OTP_CRCLOCK 0x14U // Secure CRC Lock in Z2 OTP
#define DCSM_O_Z2OTP_BOOTCTRL 0x1EU // Boot Mode in Z2 OTP
#define DCSM_O_Z1_LINKPOINTER 0x0U // Zone 1 Link Pointer
#define DCSM_O_Z1_OTPSECLOCK 0x2U // Zone 1 OTP Secure JTAG lock
#define DCSM_O_Z1_BOOTCTRL 0x4U // Boot Mode
#define DCSM_O_Z1_LINKPOINTERERR 0x6U // Link Pointer Error
#define DCSM_O_Z1_CSMKEY0 0x10U // Zone 1 CSM Key 0
#define DCSM_O_Z1_CSMKEY1 0x12U // Zone 1 CSM Key 1
#define DCSM_O_Z1_CSMKEY2 0x14U // Zone 1 CSM Key 2
#define DCSM_O_Z1_CSMKEY3 0x16U // Zone 1 CSM Key 3
#define DCSM_O_Z1_CR 0x19U // Zone 1 CSM Control Register
#define DCSM_O_Z1_GRABSECTR 0x1AU // Zone 1 Grab Flash Sectors Register
#define DCSM_O_Z1_GRABRAMR 0x1CU // Zone 1 Grab RAM Blocks Register
#define DCSM_O_Z1_EXEONLYSECTR 0x1EU // Zone 1 Flash Execute_Only Sector Register
#define DCSM_O_Z1_EXEONLYRAMR 0x20U // Zone 1 RAM Execute_Only Block Register
#define DCSM_O_Z2_LINKPOINTER 0x0U // Zone 2 Link Pointer
#define DCSM_O_Z2_OTPSECLOCK 0x2U // Zone 2 OTP Secure JTAG lock
#define DCSM_O_Z2_BOOTCTRL 0x4U // Boot Mode
#define DCSM_O_Z2_LINKPOINTERERR 0x6U // Link Pointer Error
#define DCSM_O_Z2_CSMKEY0 0x10U // Zone 2 CSM Key 0
#define DCSM_O_Z2_CSMKEY1 0x12U // Zone 2 CSM Key 1
#define DCSM_O_Z2_CSMKEY2 0x14U // Zone 2 CSM Key 2
#define DCSM_O_Z2_CSMKEY3 0x16U // Zone 2 CSM Key 3
#define DCSM_O_Z2_CR 0x19U // Zone 2 CSM Control Register
#define DCSM_O_Z2_GRABSECTR 0x1AU // Zone 2 Grab Flash Sectors Register
#define DCSM_O_Z2_GRABRAMR 0x1CU // Zone 2 Grab RAM Blocks Register
#define DCSM_O_Z2_EXEONLYSECTR 0x1EU // Zone 2 Flash Execute_Only Sector Register
#define DCSM_O_Z2_EXEONLYRAMR 0x20U // Zone 2 RAM Execute_Only Block Register
#define DCSM_O_FLSEM 0x0U // Flash Wrapper Semaphore Register
#define DCSM_O_SECTSTAT 0x2U // Sectors Status Register
#define DCSM_O_RAMSTAT 0x4U // RAM Status Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z1_LINKPOINTER register
//
//*************************************************************************************************
#define DCSM_Z1_LINKPOINTER_LINKPOINTER_S 0U
#define DCSM_Z1_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone1 LINK Pointer.
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z1_OTPSECLOCK register
//
//*************************************************************************************************
#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_S 4U
#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone1 Password Lock.
#define DCSM_Z1_OTPSECLOCK_CRCLOCK_S 8U
#define DCSM_Z1_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone1 CRC Lock.
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z1_BOOTCTRL register
//
//*************************************************************************************************
#define DCSM_Z1_BOOTCTRL_KEY_S 0U
#define DCSM_Z1_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key
#define DCSM_Z1_BOOTCTRL_BMODE_S 8U
#define DCSM_Z1_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode
#define DCSM_Z1_BOOTCTRL_BOOTPIN0_S 16U
#define DCSM_Z1_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping
#define DCSM_Z1_BOOTCTRL_BOOTPIN1_S 24U
#define DCSM_Z1_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z1_CR register
//
//*************************************************************************************************
#define DCSM_Z1_CR_ALLZERO 0x8U // CSMPSWD All Zeros
#define DCSM_Z1_CR_ALLONE 0x10U // CSMPSWD All Ones
#define DCSM_Z1_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY
#define DCSM_Z1_CR_ARMED 0x40U // CSM Armed
#define DCSM_Z1_CR_FORCESEC 0x8000U // Force Secure
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z1_GRABSECTR register
//
//*************************************************************************************************
#define DCSM_Z1_GRABSECTR_GRAB_SECTA_S 0U
#define DCSM_Z1_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A
#define DCSM_Z1_GRABSECTR_GRAB_SECTB_S 2U
#define DCSM_Z1_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B
#define DCSM_Z1_GRABSECTR_GRAB_SECTC_S 4U
#define DCSM_Z1_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C
#define DCSM_Z1_GRABSECTR_GRAB_SECTD_S 6U
#define DCSM_Z1_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D
#define DCSM_Z1_GRABSECTR_GRAB_SECTE_S 8U
#define DCSM_Z1_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E
#define DCSM_Z1_GRABSECTR_GRAB_SECTF_S 10U
#define DCSM_Z1_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F
#define DCSM_Z1_GRABSECTR_GRAB_SECTG_S 12U
#define DCSM_Z1_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G
#define DCSM_Z1_GRABSECTR_GRAB_SECTH_S 14U
#define DCSM_Z1_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H
#define DCSM_Z1_GRABSECTR_GRAB_SECTI_S 16U
#define DCSM_Z1_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I
#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_S 18U
#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J
#define DCSM_Z1_GRABSECTR_GRAB_SECTK_S 20U
#define DCSM_Z1_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K
#define DCSM_Z1_GRABSECTR_GRAB_SECTL_S 22U
#define DCSM_Z1_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L
#define DCSM_Z1_GRABSECTR_GRAB_SECTM_S 24U
#define DCSM_Z1_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M
#define DCSM_Z1_GRABSECTR_GRAB_SECTN_S 26U
#define DCSM_Z1_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z1_GRABRAMR register
//
//*************************************************************************************************
#define DCSM_Z1_GRABRAMR_GRAB_RAM0_S 0U
#define DCSM_Z1_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0
#define DCSM_Z1_GRABRAMR_GRAB_RAM1_S 2U
#define DCSM_Z1_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1
#define DCSM_Z1_GRABRAMR_GRAB_RAM2_S 4U
#define DCSM_Z1_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2
#define DCSM_Z1_GRABRAMR_GRAB_RAM3_S 6U
#define DCSM_Z1_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3
#define DCSM_Z1_GRABRAMR_GRAB_RAM4_S 8U
#define DCSM_Z1_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4
#define DCSM_Z1_GRABRAMR_GRAB_RAM5_S 10U
#define DCSM_Z1_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5
#define DCSM_Z1_GRABRAMR_GRAB_RAM6_S 12U
#define DCSM_Z1_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0
#define DCSM_Z1_GRABRAMR_GRAB_RAM7_S 14U
#define DCSM_Z1_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1
#define DCSM_Z1_GRABRAMR_GRAB_CLA1_S 28U
#define DCSM_Z1_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z1_EXEONLYSECTR register
//
//*************************************************************************************************
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M
#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z1_EXEONLYRAMR register
//
//*************************************************************************************************
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0
#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z2_LINKPOINTER register
//
//*************************************************************************************************
#define DCSM_Z2_LINKPOINTER_LINKPOINTER_S 0U
#define DCSM_Z2_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone2 LINK Pointer.
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z2_OTPSECLOCK register
//
//*************************************************************************************************
#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_S 4U
#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone2 Password Lock.
#define DCSM_Z2_OTPSECLOCK_CRCLOCK_S 8U
#define DCSM_Z2_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone2 CRC Lock.
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z2_BOOTCTRL register
//
//*************************************************************************************************
#define DCSM_Z2_BOOTCTRL_KEY_S 0U
#define DCSM_Z2_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key
#define DCSM_Z2_BOOTCTRL_BMODE_S 8U
#define DCSM_Z2_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode
#define DCSM_Z2_BOOTCTRL_BOOTPIN0_S 16U
#define DCSM_Z2_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping
#define DCSM_Z2_BOOTCTRL_BOOTPIN1_S 24U
#define DCSM_Z2_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z2_CR register
//
//*************************************************************************************************
#define DCSM_Z2_CR_ALLZERO 0x8U // CSMPSWD All Zeros
#define DCSM_Z2_CR_ALLONE 0x10U // CSMPSWD All Ones
#define DCSM_Z2_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY
#define DCSM_Z2_CR_ARMED 0x40U // CSM Armed
#define DCSM_Z2_CR_FORCESEC 0x8000U // Force Secure
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z2_GRABSECTR register
//
//*************************************************************************************************
#define DCSM_Z2_GRABSECTR_GRAB_SECTA_S 0U
#define DCSM_Z2_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A
#define DCSM_Z2_GRABSECTR_GRAB_SECTB_S 2U
#define DCSM_Z2_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B
#define DCSM_Z2_GRABSECTR_GRAB_SECTC_S 4U
#define DCSM_Z2_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C
#define DCSM_Z2_GRABSECTR_GRAB_SECTD_S 6U
#define DCSM_Z2_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D
#define DCSM_Z2_GRABSECTR_GRAB_SECTE_S 8U
#define DCSM_Z2_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E
#define DCSM_Z2_GRABSECTR_GRAB_SECTF_S 10U
#define DCSM_Z2_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F
#define DCSM_Z2_GRABSECTR_GRAB_SECTG_S 12U
#define DCSM_Z2_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G
#define DCSM_Z2_GRABSECTR_GRAB_SECTH_S 14U
#define DCSM_Z2_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H
#define DCSM_Z2_GRABSECTR_GRAB_SECTI_S 16U
#define DCSM_Z2_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I
#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_S 18U
#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J
#define DCSM_Z2_GRABSECTR_GRAB_SECTK_S 20U
#define DCSM_Z2_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K
#define DCSM_Z2_GRABSECTR_GRAB_SECTL_S 22U
#define DCSM_Z2_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L
#define DCSM_Z2_GRABSECTR_GRAB_SECTM_S 24U
#define DCSM_Z2_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M
#define DCSM_Z2_GRABSECTR_GRAB_SECTN_S 26U
#define DCSM_Z2_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z2_GRABRAMR register
//
//*************************************************************************************************
#define DCSM_Z2_GRABRAMR_GRAB_RAM0_S 0U
#define DCSM_Z2_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0
#define DCSM_Z2_GRABRAMR_GRAB_RAM1_S 2U
#define DCSM_Z2_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1
#define DCSM_Z2_GRABRAMR_GRAB_RAM2_S 4U
#define DCSM_Z2_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2
#define DCSM_Z2_GRABRAMR_GRAB_RAM3_S 6U
#define DCSM_Z2_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3
#define DCSM_Z2_GRABRAMR_GRAB_RAM4_S 8U
#define DCSM_Z2_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4
#define DCSM_Z2_GRABRAMR_GRAB_RAM5_S 10U
#define DCSM_Z2_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5
#define DCSM_Z2_GRABRAMR_GRAB_RAM6_S 12U
#define DCSM_Z2_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0
#define DCSM_Z2_GRABRAMR_GRAB_RAM7_S 14U
#define DCSM_Z2_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1
#define DCSM_Z2_GRABRAMR_GRAB_CLA1_S 28U
#define DCSM_Z2_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z2_EXEONLYSECTR register
//
//*************************************************************************************************
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M
#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N
//*************************************************************************************************
//
// The following are defines for the bit fields in the Z2_EXEONLYRAMR register
//
//*************************************************************************************************
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0
#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1
//*************************************************************************************************
//
// The following are defines for the bit fields in the FLSEM register
//
//*************************************************************************************************
#define DCSM_FLSEM_SEM_S 0U
#define DCSM_FLSEM_SEM_M 0x3U // Flash Semaphore Bit
#define DCSM_FLSEM_KEY_S 8U
#define DCSM_FLSEM_KEY_M 0xFF00U // Semaphore Key
//*************************************************************************************************
//
// The following are defines for the bit fields in the SECTSTAT register
//
//*************************************************************************************************
#define DCSM_SECTSTAT_STATUS_SECTA_S 0U
#define DCSM_SECTSTAT_STATUS_SECTA_M 0x3U // Zone Status Flash Sector A
#define DCSM_SECTSTAT_STATUS_SECTB_S 2U
#define DCSM_SECTSTAT_STATUS_SECTB_M 0xCU // Zone Status Flash Sector B
#define DCSM_SECTSTAT_STATUS_SECTC_S 4U
#define DCSM_SECTSTAT_STATUS_SECTC_M 0x30U // Zone Status Flash Sector C
#define DCSM_SECTSTAT_STATUS_SECTD_S 6U
#define DCSM_SECTSTAT_STATUS_SECTD_M 0xC0U // Zone Status Flash Sector D
#define DCSM_SECTSTAT_STATUS_SECTE_S 8U
#define DCSM_SECTSTAT_STATUS_SECTE_M 0x300U // Zone Status Flash Sector E
#define DCSM_SECTSTAT_STATUS_SECTF_S 10U
#define DCSM_SECTSTAT_STATUS_SECTF_M 0xC00U // Zone Status Flash Sector F
#define DCSM_SECTSTAT_STATUS_SECTG_S 12U
#define DCSM_SECTSTAT_STATUS_SECTG_M 0x3000U // Zone Status Flash Sector G
#define DCSM_SECTSTAT_STATUS_SECTH_S 14U
#define DCSM_SECTSTAT_STATUS_SECTH_M 0xC000U // Zone Status Flash Sector H
#define DCSM_SECTSTAT_STATUS_SECTI_S 16U
#define DCSM_SECTSTAT_STATUS_SECTI_M 0x30000U // Zone Status Flash Sector I
#define DCSM_SECTSTAT_STATUS_SECTJ_S 18U
#define DCSM_SECTSTAT_STATUS_SECTJ_M 0xC0000U // Zone Status Flash Sector J
#define DCSM_SECTSTAT_STATUS_SECTK_S 20U
#define DCSM_SECTSTAT_STATUS_SECTK_M 0x300000U // Zone Status Flash Sector K
#define DCSM_SECTSTAT_STATUS_SECTL_S 22U
#define DCSM_SECTSTAT_STATUS_SECTL_M 0xC00000U // Zone Status Flash Sector L
#define DCSM_SECTSTAT_STATUS_SECTM_S 24U
#define DCSM_SECTSTAT_STATUS_SECTM_M 0x3000000U // Zone Status Flash Sector M
#define DCSM_SECTSTAT_STATUS_SECTN_S 26U
#define DCSM_SECTSTAT_STATUS_SECTN_M 0xC000000U // Zone Status Flash Sector N
//*************************************************************************************************
//
// The following are defines for the bit fields in the RAMSTAT register
//
//*************************************************************************************************
#define DCSM_RAMSTAT_STATUS_RAM0_S 0U
#define DCSM_RAMSTAT_STATUS_RAM0_M 0x3U // Zone Status RAM LS0
#define DCSM_RAMSTAT_STATUS_RAM1_S 2U
#define DCSM_RAMSTAT_STATUS_RAM1_M 0xCU // Zone Status RAM LS1
#define DCSM_RAMSTAT_STATUS_RAM2_S 4U
#define DCSM_RAMSTAT_STATUS_RAM2_M 0x30U // Zone Status RAM LS2
#define DCSM_RAMSTAT_STATUS_RAM3_S 6U
#define DCSM_RAMSTAT_STATUS_RAM3_M 0xC0U // Zone Status RAM LS3
#define DCSM_RAMSTAT_STATUS_RAM4_S 8U
#define DCSM_RAMSTAT_STATUS_RAM4_M 0x300U // Zone Status RAM LS4
#define DCSM_RAMSTAT_STATUS_RAM5_S 10U
#define DCSM_RAMSTAT_STATUS_RAM5_M 0xC00U // Zone Status RAM LS5
#define DCSM_RAMSTAT_STATUS_RAM6_S 12U
#define DCSM_RAMSTAT_STATUS_RAM6_M 0x3000U // Zone Status RAM D0
#define DCSM_RAMSTAT_STATUS_RAM7_S 14U
#define DCSM_RAMSTAT_STATUS_RAM7_M 0xC000U // Zone Status RAM D1
#define DCSM_RAMSTAT_STATUS_CLA1_S 28U
#define DCSM_RAMSTAT_STATUS_CLA1_M 0x30000000U // Zone Status CLA1
#endif
28379d_P_SFRA/device/driverlib/inc/hw_dma.h
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//###########################################################################
//
// FILE: hw_dma.h
//
// TITLE: Definitions for the DMA registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_DMA_H
#define HW_DMA_H
//*************************************************************************************************
//
// The following are defines for the DMA register offsets
//
//*************************************************************************************************
#define DMA_O_CTRL 0x0U // DMA Control Register
#define DMA_O_DEBUGCTRL 0x1U // Debug Control Register
#define DMA_O_PRIORITYCTRL1 0x4U // Priority Control 1 Register
#define DMA_O_PRIORITYSTAT 0x6U // Priority Status Register
#define DMA_O_MODE 0x0U // Mode Register
#define DMA_O_CONTROL 0x1U // Control Register
#define DMA_O_BURST_SIZE 0x2U // Burst Size Register
#define DMA_O_BURST_COUNT 0x3U // Burst Count Register
#define DMA_O_SRC_BURST_STEP 0x4U // Source Burst Step Register
#define DMA_O_DST_BURST_STEP 0x5U // Destination Burst Step Register
#define DMA_O_TRANSFER_SIZE 0x6U // Transfer Size Register
#define DMA_O_TRANSFER_COUNT 0x7U // Transfer Count Register
#define DMA_O_SRC_TRANSFER_STEP 0x8U // Source Transfer Step Register
#define DMA_O_DST_TRANSFER_STEP 0x9U // Destination Transfer Step Register
#define DMA_O_SRC_WRAP_SIZE 0xAU // Source Wrap Size Register
#define DMA_O_SRC_WRAP_COUNT 0xBU // Source Wrap Count Register
#define DMA_O_SRC_WRAP_STEP 0xCU // Source Wrap Step Register
#define DMA_O_DST_WRAP_SIZE 0xDU // Destination Wrap Size Register
#define DMA_O_DST_WRAP_COUNT 0xEU // Destination Wrap Count Register
#define DMA_O_DST_WRAP_STEP 0xFU // Destination Wrap Step Register
#define DMA_O_SRC_BEG_ADDR_SHADOW 0x10U // Source Begin Address Shadow Register
#define DMA_O_SRC_ADDR_SHADOW 0x12U // Source Address Shadow Register
#define DMA_O_SRC_BEG_ADDR_ACTIVE 0x14U // Source Begin Address Active Register
#define DMA_O_SRC_ADDR_ACTIVE 0x16U // Source Address Active Register
#define DMA_O_DST_BEG_ADDR_SHADOW 0x18U // Destination Begin Address Shadow Register
#define DMA_O_DST_ADDR_SHADOW 0x1AU // Destination Address Shadow Register
#define DMA_O_DST_BEG_ADDR_ACTIVE 0x1CU // Destination Begin Address Active Register
#define DMA_O_DST_ADDR_ACTIVE 0x1EU // Destination Address Active Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the DMACTRL register
//
//*************************************************************************************************
#define DMA_CTRL_HARDRESET 0x1U // Hard Reset Bit
#define DMA_CTRL_PRIORITYRESET 0x2U // Priority Reset Bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the DEBUGCTRL register
//
//*************************************************************************************************
#define DMA_DEBUGCTRL_FREE 0x8000U // Debug Mode Bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the PRIORITYCTRL1 register
//
//*************************************************************************************************
#define DMA_PRIORITYCTRL1_CH1PRIORITY 0x1U // Ch1 Priority Bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the PRIORITYSTAT register
//
//*************************************************************************************************
#define DMA_PRIORITYSTAT_ACTIVESTS_S 0U
#define DMA_PRIORITYSTAT_ACTIVESTS_M 0x7U // Active Channel Status Bits
#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_S 4U
#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_M 0x70U // Active Channel Status Shadow Bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the MODE register
//
//*************************************************************************************************
#define DMA_MODE_PERINTSEL_S 0U
#define DMA_MODE_PERINTSEL_M 0x1FU // Peripheral Interrupt and Sync Select
#define DMA_MODE_OVRINTE 0x80U // Overflow Interrupt Enable
#define DMA_MODE_PERINTE 0x100U // Peripheral Interrupt Enable
#define DMA_MODE_CHINTMODE 0x200U // Channel Interrupt Mode
#define DMA_MODE_ONESHOT 0x400U // One Shot Mode Bit
#define DMA_MODE_CONTINUOUS 0x800U // Continuous Mode Bit
#define DMA_MODE_DATASIZE 0x4000U // Data Size Mode Bit
#define DMA_MODE_CHINTE 0x8000U // Channel Interrupt Enable Bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the CONTROL register
//
//*************************************************************************************************
#define DMA_CONTROL_RUN 0x1U // Run Bit
#define DMA_CONTROL_HALT 0x2U // Halt Bit
#define DMA_CONTROL_SOFTRESET 0x4U // Soft Reset Bit
#define DMA_CONTROL_PERINTFRC 0x8U // Interrupt Force Bit
#define DMA_CONTROL_PERINTCLR 0x10U // Interrupt Clear Bit
#define DMA_CONTROL_ERRCLR 0x80U // Error Clear Bit
#define DMA_CONTROL_PERINTFLG 0x100U // Interrupt Flag Bit
#define DMA_CONTROL_TRANSFERSTS 0x800U // Transfer Status Bit
#define DMA_CONTROL_BURSTSTS 0x1000U // Burst Status Bit
#define DMA_CONTROL_RUNSTS 0x2000U // Run Status Bit
#define DMA_CONTROL_OVRFLG 0x4000U // Overflow Flag Bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the BURST_SIZE register
//
//*************************************************************************************************
#define DMA_BURST_SIZE_BURSTSIZE_S 0U
#define DMA_BURST_SIZE_BURSTSIZE_M 0x1FU // Burst Transfer Size
//*************************************************************************************************
//
// The following are defines for the bit fields in the BURST_COUNT register
//
//*************************************************************************************************
#define DMA_BURST_COUNT_BURSTCOUNT_S 0U
#define DMA_BURST_COUNT_BURSTCOUNT_M 0x1FU // Burst Transfer Size
#endif
28379d_P_SFRA/device/driverlib/inc/hw_ecap.h
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//###########################################################################
//
// FILE: hw_ecap.h
//
// TITLE: Definitions for the ECAP registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_ECAP_H
#define HW_ECAP_H
//*************************************************************************************************
//
// The following are defines for the ECAP register offsets
//
//*************************************************************************************************
#define ECAP_O_TSCTR 0x0U // Time-Stamp Counter
#define ECAP_O_CTRPHS 0x2U // Counter Phase Offset Value Register
#define ECAP_O_CAP1 0x4U // Capture 1 Register
#define ECAP_O_CAP2 0x6U // Capture 2 Register
#define ECAP_O_CAP3 0x8U // Capture 3 Register
#define ECAP_O_CAP4 0xAU // Capture 4 Register
#define ECAP_O_ECCTL1 0x14U // Capture Control Register 1
#define ECAP_O_ECCTL2 0x15U // Capture Control Register 2
#define ECAP_O_ECEINT 0x16U // Capture Interrupt Enable Register
#define ECAP_O_ECFLG 0x17U // Capture Interrupt Flag Register
#define ECAP_O_ECCLR 0x18U // Capture Interrupt Clear Register
#define ECAP_O_ECFRC 0x19U // Capture Interrupt Force Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL1 register
//
//*************************************************************************************************
#define ECAP_ECCTL1_CAP1POL 0x1U // Capture Event 1 Polarity select
#define ECAP_ECCTL1_CTRRST1 0x2U // Counter Reset on Capture Event 1
#define ECAP_ECCTL1_CAP2POL 0x4U // Capture Event 2 Polarity select
#define ECAP_ECCTL1_CTRRST2 0x8U // Counter Reset on Capture Event 2
#define ECAP_ECCTL1_CAP3POL 0x10U // Capture Event 3 Polarity select
#define ECAP_ECCTL1_CTRRST3 0x20U // Counter Reset on Capture Event 3
#define ECAP_ECCTL1_CAP4POL 0x40U // Capture Event 4 Polarity select
#define ECAP_ECCTL1_CTRRST4 0x80U // Counter Reset on Capture Event 4
#define ECAP_ECCTL1_CAPLDEN 0x100U // Enable Loading CAP1-4 regs on a Cap Event
#define ECAP_ECCTL1_PRESCALE_S 9U
#define ECAP_ECCTL1_PRESCALE_M 0x3E00U // Event Filter prescale select
#define ECAP_ECCTL1_FREE_SOFT_S 14U
#define ECAP_ECCTL1_FREE_SOFT_M 0xC000U // Emulation mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCTL2 register
//
//*************************************************************************************************
#define ECAP_ECCTL2_CONT_ONESHT 0x1U // Continuous or one-shot
#define ECAP_ECCTL2_STOP_WRAP_S 1U
#define ECAP_ECCTL2_STOP_WRAP_M 0x6U // Stop value for one-shot, Wrap for continuous
#define ECAP_ECCTL2_REARM 0x8U // One-shot re-arm
#define ECAP_ECCTL2_TSCTRSTOP 0x10U // TSCNT counter stop
#define ECAP_ECCTL2_SYNCI_EN 0x20U // Counter sync-in select
#define ECAP_ECCTL2_SYNCO_SEL_S 6U
#define ECAP_ECCTL2_SYNCO_SEL_M 0xC0U // Sync-out mode
#define ECAP_ECCTL2_SWSYNC 0x100U // SW forced counter sync
#define ECAP_ECCTL2_CAP_APWM 0x200U // CAP/APWM operating mode select
#define ECAP_ECCTL2_APWMPOL 0x400U // APWM output polarity select
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECEINT register
//
//*************************************************************************************************
#define ECAP_ECEINT_CEVT1 0x2U // Capture Event 1 Interrupt Enable
#define ECAP_ECEINT_CEVT2 0x4U // Capture Event 2 Interrupt Enable
#define ECAP_ECEINT_CEVT3 0x8U // Capture Event 3 Interrupt Enable
#define ECAP_ECEINT_CEVT4 0x10U // Capture Event 4 Interrupt Enable
#define ECAP_ECEINT_CTROVF 0x20U // Counter Overflow Interrupt Enable
#define ECAP_ECEINT_CTR_EQ_PRD 0x40U // Period Equal Interrupt Enable
#define ECAP_ECEINT_CTR_EQ_CMP 0x80U // Compare Equal Interrupt Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECFLG register
//
//*************************************************************************************************
#define ECAP_ECFLG_INT 0x1U // Global Flag
#define ECAP_ECFLG_CEVT1 0x2U // Capture Event 1 Interrupt Flag
#define ECAP_ECFLG_CEVT2 0x4U // Capture Event 2 Interrupt Flag
#define ECAP_ECFLG_CEVT3 0x8U // Capture Event 3 Interrupt Flag
#define ECAP_ECFLG_CEVT4 0x10U // Capture Event 4 Interrupt Flag
#define ECAP_ECFLG_CTROVF 0x20U // Counter Overflow Interrupt Flag
#define ECAP_ECFLG_CTR_PRD 0x40U // Period Equal Interrupt Flag
#define ECAP_ECFLG_CTR_CMP 0x80U // Compare Equal Interrupt Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECCLR register
//
//*************************************************************************************************
#define ECAP_ECCLR_INT 0x1U // ECAP Global Interrupt Status Clear
#define ECAP_ECCLR_CEVT1 0x2U // Capture Event 1 Status Clear
#define ECAP_ECCLR_CEVT2 0x4U // Capture Event 2 Status Clear
#define ECAP_ECCLR_CEVT3 0x8U // Capture Event 3 Status Clear
#define ECAP_ECCLR_CEVT4 0x10U // Capture Event 4 Status Clear
#define ECAP_ECCLR_CTROVF 0x20U // Counter Overflow Status Clear
#define ECAP_ECCLR_CTR_PRD 0x40U // Period Equal Status Clear
#define ECAP_ECCLR_CTR_CMP 0x80U // Compare Equal Status Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECFRC register
//
//*************************************************************************************************
#define ECAP_ECFRC_CEVT1 0x2U // Capture Event 1 Force Interrupt
#define ECAP_ECFRC_CEVT2 0x4U // Capture Event 2 Force Interrupt
#define ECAP_ECFRC_CEVT3 0x8U // Capture Event 3 Force Interrupt
#define ECAP_ECFRC_CEVT4 0x10U // Capture Event 4 Force Interrupt
#define ECAP_ECFRC_CTROVF 0x20U // Counter Overflow Force Interrupt
#define ECAP_ECFRC_CTR_PRD 0x40U // Period Equal Force Interrupt
#define ECAP_ECFRC_CTR_CMP 0x80U // Compare Equal Force Interrupt
#endif
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//###########################################################################
//
// FILE: hw_emif.h
//
// TITLE: Definitions for the EMIF registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_EMIF_H
#define HW_EMIF_H
//*************************************************************************************************
//
// The following are defines for the EMIF register offsets
//
//*************************************************************************************************
#define EMIF_O_RCSR 0x0U // Revision Code and Status Register
#define EMIF_O_ASYNC_WCCR 0x2U // Async Wait Cycle Config Register
#define EMIF_O_SDRAM_CR 0x4U // SDRAM (EMxCS0n) Config Register
#define EMIF_O_SDRAM_RCR 0x6U // SDRAM Refresh Control Register
#define EMIF_O_ASYNC_CS2_CR 0x8U // Async 1 (EMxCS2n) Config Register
#define EMIF_O_ASYNC_CS3_CR 0xAU // Async 2 (EMxCS3n) Config Register
#define EMIF_O_ASYNC_CS4_CR 0xCU // Async 3 (EMxCS4n) Config Register
#define EMIF_O_SDRAM_TR 0x10U // SDRAM Timing Register
#define EMIF_O_TOTAL_SDRAM_AR 0x18U // Total SDRAM Accesses Register
#define EMIF_O_TOTAL_SDRAM_ACTR 0x1AU // Total SDRAM Activate Register
#define EMIF_O_SDR_EXT_TMNG 0x1EU // SDRAM SR/PD Exit Timing Register
#define EMIF_O_INT_RAW 0x20U // Interrupt Raw Register
#define EMIF_O_INT_MSK 0x22U // Interrupt Masked Register
#define EMIF_O_INT_MSK_SET 0x24U // Interrupt Mask Set Register
#define EMIF_O_INT_MSK_CLR 0x26U // Interrupt Mask Clear Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the RCSR register
//
//*************************************************************************************************
#define EMIF_RCSR_MINOR_REVISION_S 0U
#define EMIF_RCSR_MINOR_REVISION_M 0xFFU // Minor Revision.
#define EMIF_RCSR_MAJOR_REVISION_S 8U
#define EMIF_RCSR_MAJOR_REVISION_M 0xFF00U // Major Revision.
#define EMIF_RCSR_MODULE_ID_S 16U
#define EMIF_RCSR_MODULE_ID_M 0x3FFF0000U // EMIF module ID.
#define EMIF_RCSR_FR 0x40000000U // EMIF is running in full rate or half rate.
#define EMIF_RCSR_BE 0x80000000U // EMIF endian mode.
//*************************************************************************************************
//
// The following are defines for the bit fields in the ASYNC_WCCR register
//
//*************************************************************************************************
#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_S 0U
#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M 0xFFU // Maximum Extended Wait cycles.
#define EMIF_ASYNC_WCCR_WP0 0x10000000U // Polarity for EMxWAIT.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDRAM_CR register
//
//*************************************************************************************************
#define EMIF_SDRAM_CR_PAGESIGE_S 0U
#define EMIF_SDRAM_CR_PAGESIGE_M 0x7U // Page Size.
#define EMIF_SDRAM_CR_IBANK_S 4U
#define EMIF_SDRAM_CR_IBANK_M 0x70U // Internal Bank setup of SDRAM devices.
#define EMIF_SDRAM_CR_BIT_11_9_LOCK 0x100U // Bits 11 to 9 are writable only if this bit
// is set.
#define EMIF_SDRAM_CR_CL_S 9U
#define EMIF_SDRAM_CR_CL_M 0xE00U // CAS Latency.
#define EMIF_SDRAM_CR_NM 0x4000U // Narrow Mode.
#define EMIF_SDRAM_CR_PDWR 0x20000000U // Perform refreshes during Power Down.
#define EMIF_SDRAM_CR_PD 0x40000000U // Power Down.
#define EMIF_SDRAM_CR_SR 0x80000000U // Self Refresh.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDRAM_RCR register
//
//*************************************************************************************************
#define EMIF_SDRAM_RCR_REFRESH_RATE_S 0U
#define EMIF_SDRAM_RCR_REFRESH_RATE_M 0x1FFFU // Refresh Rate.
//*************************************************************************************************
//
// The following are defines for the bit fields in the ASYNC_CS2_CR register
//
//*************************************************************************************************
#define EMIF_ASYNC_CS2_CR_ASIZE_S 0U
#define EMIF_ASYNC_CS2_CR_ASIZE_M 0x3U // Asynchronous Memory Size.
#define EMIF_ASYNC_CS2_CR_TA_S 2U
#define EMIF_ASYNC_CS2_CR_TA_M 0xCU // Turn Around cycles.
#define EMIF_ASYNC_CS2_CR_R_HOLD_S 4U
#define EMIF_ASYNC_CS2_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles.
#define EMIF_ASYNC_CS2_CR_R_STROBE_S 7U
#define EMIF_ASYNC_CS2_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles.
#define EMIF_ASYNC_CS2_CR_R_SETUP_S 13U
#define EMIF_ASYNC_CS2_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles.
#define EMIF_ASYNC_CS2_CR_W_HOLD_S 17U
#define EMIF_ASYNC_CS2_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles.
#define EMIF_ASYNC_CS2_CR_W_STROBE_S 20U
#define EMIF_ASYNC_CS2_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles.
#define EMIF_ASYNC_CS2_CR_W_SETUP_S 26U
#define EMIF_ASYNC_CS2_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles.
#define EMIF_ASYNC_CS2_CR_EW 0x40000000U // Extend Wait mode.
#define EMIF_ASYNC_CS2_CR_SS 0x80000000U // Select Strobe mode.
//*************************************************************************************************
//
// The following are defines for the bit fields in the ASYNC_CS3_CR register
//
//*************************************************************************************************
#define EMIF_ASYNC_CS3_CR_ASIZE_S 0U
#define EMIF_ASYNC_CS3_CR_ASIZE_M 0x3U // Asynchronous Memory Size.
#define EMIF_ASYNC_CS3_CR_TA_S 2U
#define EMIF_ASYNC_CS3_CR_TA_M 0xCU // Turn Around cycles.
#define EMIF_ASYNC_CS3_CR_R_HOLD_S 4U
#define EMIF_ASYNC_CS3_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles.
#define EMIF_ASYNC_CS3_CR_R_STROBE_S 7U
#define EMIF_ASYNC_CS3_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles.
#define EMIF_ASYNC_CS3_CR_R_SETUP_S 13U
#define EMIF_ASYNC_CS3_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles.
#define EMIF_ASYNC_CS3_CR_W_HOLD_S 17U
#define EMIF_ASYNC_CS3_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles.
#define EMIF_ASYNC_CS3_CR_W_STROBE_S 20U
#define EMIF_ASYNC_CS3_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles.
#define EMIF_ASYNC_CS3_CR_W_SETUP_S 26U
#define EMIF_ASYNC_CS3_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles.
#define EMIF_ASYNC_CS3_CR_EW 0x40000000U // Extend Wait mode.
#define EMIF_ASYNC_CS3_CR_SS 0x80000000U // Select Strobe mode.
//*************************************************************************************************
//
// The following are defines for the bit fields in the ASYNC_CS4_CR register
//
//*************************************************************************************************
#define EMIF_ASYNC_CS4_CR_ASIZE_S 0U
#define EMIF_ASYNC_CS4_CR_ASIZE_M 0x3U // Asynchronous Memory Size.
#define EMIF_ASYNC_CS4_CR_TA_S 2U
#define EMIF_ASYNC_CS4_CR_TA_M 0xCU // Turn Around cycles.
#define EMIF_ASYNC_CS4_CR_R_HOLD_S 4U
#define EMIF_ASYNC_CS4_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles.
#define EMIF_ASYNC_CS4_CR_R_STROBE_S 7U
#define EMIF_ASYNC_CS4_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles.
#define EMIF_ASYNC_CS4_CR_R_SETUP_S 13U
#define EMIF_ASYNC_CS4_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles.
#define EMIF_ASYNC_CS4_CR_W_HOLD_S 17U
#define EMIF_ASYNC_CS4_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles.
#define EMIF_ASYNC_CS4_CR_W_STROBE_S 20U
#define EMIF_ASYNC_CS4_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles.
#define EMIF_ASYNC_CS4_CR_W_SETUP_S 26U
#define EMIF_ASYNC_CS4_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles.
#define EMIF_ASYNC_CS4_CR_EW 0x40000000U // Extend Wait mode.
#define EMIF_ASYNC_CS4_CR_SS 0x80000000U // Select Strobe mode.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDRAM_TR register
//
//*************************************************************************************************
#define EMIF_SDRAM_TR_T_RRD_S 4U
#define EMIF_SDRAM_TR_T_RRD_M 0x70U // Activate to Activate timing for different bank.
#define EMIF_SDRAM_TR_T_RC_S 8U
#define EMIF_SDRAM_TR_T_RC_M 0xF00U // Activate to Activate timing .
#define EMIF_SDRAM_TR_T_RAS_S 12U
#define EMIF_SDRAM_TR_T_RAS_M 0xF000U // Activate to Precharge timing.
#define EMIF_SDRAM_TR_T_WR_S 16U
#define EMIF_SDRAM_TR_T_WR_M 0x70000U // Last Write to Precharge timing.
#define EMIF_SDRAM_TR_T_RCD_S 20U
#define EMIF_SDRAM_TR_T_RCD_M 0x700000U // Activate to Read/Write timing.
#define EMIF_SDRAM_TR_T_RP_S 24U
#define EMIF_SDRAM_TR_T_RP_M 0x7000000U // Precharge to Activate/Refresh timing.
#define EMIF_SDRAM_TR_T_RFC_S 27U
#define EMIF_SDRAM_TR_T_RFC_M 0xF8000000U // Refresh/Load Mode to Refresh/Activate timing
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDR_EXT_TMNG register
//
//*************************************************************************************************
#define EMIF_SDR_EXT_TMNG_T_XS_S 0U
#define EMIF_SDR_EXT_TMNG_T_XS_M 0x1FU // Self Refresh exit to new command timing.
//*************************************************************************************************
//
// The following are defines for the bit fields in the INT_RAW register
//
//*************************************************************************************************
#define EMIF_INT_RAW_AT 0x1U // Asynchronous Timeout.
#define EMIF_INT_RAW_LT 0x2U // Line Trap.
#define EMIF_INT_RAW_WR_S 2U
#define EMIF_INT_RAW_WR_M 0x3CU // Wait Rise.
//*************************************************************************************************
//
// The following are defines for the bit fields in the INT_MSK register
//
//*************************************************************************************************
#define EMIF_INT_MSK_AT_MASKED 0x1U // Asynchronous Timeout.
#define EMIF_INT_MSK_LT_MASKED 0x2U // Line Trap.
#define EMIF_INT_MSK_WR_MASKED_S 2U
#define EMIF_INT_MSK_WR_MASKED_M 0x3CU // Wait Rise.
//*************************************************************************************************
//
// The following are defines for the bit fields in the INT_MSK_SET register
//
//*************************************************************************************************
#define EMIF_INT_MSK_SET_AT_MASK_SET 0x1U // Asynchronous Timeout.
#define EMIF_INT_MSK_SET_LT_MASK_SET 0x2U // Line Trap.
#define EMIF_INT_MSK_SET_WR_MASK_SET_S 2U
#define EMIF_INT_MSK_SET_WR_MASK_SET_M 0x3CU // Wait Rise.
//*************************************************************************************************
//
// The following are defines for the bit fields in the INT_MSK_CLR register
//
//*************************************************************************************************
#define EMIF_INT_MSK_CLR_AT_MASK_CLR 0x1U // Asynchronous Timeout.
#define EMIF_INT_MSK_CLR_LT_MASK_CLR 0x2U // Line Trap.
#define EMIF_INT_MSK_CLR_WR_MASK_CLR_S 2U
#define EMIF_INT_MSK_CLR_WR_MASK_CLR_M 0x3CU // Wait Rise.
#endif
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//###########################################################################
//
// FILE: hw_eqep.h
//
// TITLE: Definitions for the EQEP registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_EQEP_H
#define HW_EQEP_H
//*************************************************************************************************
//
// The following are defines for the EQEP register offsets
//
//*************************************************************************************************
#define EQEP_O_QPOSCNT 0x0U // Position Counter
#define EQEP_O_QPOSINIT 0x2U // Position Counter Init
#define EQEP_O_QPOSMAX 0x4U // Maximum Position Count
#define EQEP_O_QPOSCMP 0x6U // Position Compare
#define EQEP_O_QPOSILAT 0x8U // Index Position Latch
#define EQEP_O_QPOSSLAT 0xAU // Strobe Position Latch
#define EQEP_O_QPOSLAT 0xCU // Position Latch
#define EQEP_O_QUTMR 0xEU // QEP Unit Timer
#define EQEP_O_QUPRD 0x10U // QEP Unit Period
#define EQEP_O_QWDTMR 0x12U // QEP Watchdog Timer
#define EQEP_O_QWDPRD 0x13U // QEP Watchdog Period
#define EQEP_O_QDECCTL 0x14U // Quadrature Decoder Control
#define EQEP_O_QEPCTL 0x15U // QEP Control
#define EQEP_O_QCAPCTL 0x16U // Qaudrature Capture Control
#define EQEP_O_QPOSCTL 0x17U // Position Compare Control
#define EQEP_O_QEINT 0x18U // QEP Interrupt Control
#define EQEP_O_QFLG 0x19U // QEP Interrupt Flag
#define EQEP_O_QCLR 0x1AU // QEP Interrupt Clear
#define EQEP_O_QFRC 0x1BU // QEP Interrupt Force
#define EQEP_O_QEPSTS 0x1CU // QEP Status
#define EQEP_O_QCTMR 0x1DU // QEP Capture Timer
#define EQEP_O_QCPRD 0x1EU // QEP Capture Period
#define EQEP_O_QCTMRLAT 0x1FU // QEP Capture Latch
#define EQEP_O_QCPRDLAT 0x20U // QEP Capture Period Latch
//*************************************************************************************************
//
// The following are defines for the bit fields in the QDECCTL register
//
//*************************************************************************************************
#define EQEP_QDECCTL_QSP 0x20U // QEPS input polarity
#define EQEP_QDECCTL_QIP 0x40U // QEPI input polarity
#define EQEP_QDECCTL_QBP 0x80U // QEPB input polarity
#define EQEP_QDECCTL_QAP 0x100U // QEPA input polarity
#define EQEP_QDECCTL_IGATE 0x200U // Index pulse gating option
#define EQEP_QDECCTL_SWAP 0x400U // CLK/DIR Signal Source for Position Counter
#define EQEP_QDECCTL_XCR 0x800U // External Clock Rate
#define EQEP_QDECCTL_SPSEL 0x1000U // Sync output pin selection
#define EQEP_QDECCTL_SOEN 0x2000U // Sync output-enable
#define EQEP_QDECCTL_QSRC_S 14U
#define EQEP_QDECCTL_QSRC_M 0xC000U // Position-counter source selection
//*************************************************************************************************
//
// The following are defines for the bit fields in the QEPCTL register
//
//*************************************************************************************************
#define EQEP_QEPCTL_WDE 0x1U // QEP watchdog enable
#define EQEP_QEPCTL_UTE 0x2U // QEP unit timer enable
#define EQEP_QEPCTL_QCLM 0x4U // QEP capture latch mode
#define EQEP_QEPCTL_QPEN 0x8U // Quadrature postotion counter enable
#define EQEP_QEPCTL_IEL_S 4U
#define EQEP_QEPCTL_IEL_M 0x30U // Index event latch
#define EQEP_QEPCTL_SEL 0x40U // Strobe event latch
#define EQEP_QEPCTL_SWI 0x80U // Software init position counter
#define EQEP_QEPCTL_IEI_S 8U
#define EQEP_QEPCTL_IEI_M 0x300U // Index event init of position count
#define EQEP_QEPCTL_SEI_S 10U
#define EQEP_QEPCTL_SEI_M 0xC00U // Strobe event init
#define EQEP_QEPCTL_PCRM_S 12U
#define EQEP_QEPCTL_PCRM_M 0x3000U // Postion counter reset
#define EQEP_QEPCTL_FREE_SOFT_S 14U
#define EQEP_QEPCTL_FREE_SOFT_M 0xC000U // Emulation mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the QCAPCTL register
//
//*************************************************************************************************
#define EQEP_QCAPCTL_UPPS_S 0U
#define EQEP_QCAPCTL_UPPS_M 0xFU // Unit position event prescaler
#define EQEP_QCAPCTL_CCPS_S 4U
#define EQEP_QCAPCTL_CCPS_M 0x70U // eQEP capture timer clock prescaler
#define EQEP_QCAPCTL_CEN 0x8000U // Enable eQEP capture
//*************************************************************************************************
//
// The following are defines for the bit fields in the QPOSCTL register
//
//*************************************************************************************************
#define EQEP_QPOSCTL_PCSPW_S 0U
#define EQEP_QPOSCTL_PCSPW_M 0xFFFU // Position compare sync pulse width
#define EQEP_QPOSCTL_PCE 0x1000U // Position compare enable/disable
#define EQEP_QPOSCTL_PCPOL 0x2000U // Polarity of sync output
#define EQEP_QPOSCTL_PCLOAD 0x4000U // Position compare of shadow load
#define EQEP_QPOSCTL_PCSHDW 0x8000U // Position compare of shadow enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the QEINT register
//
//*************************************************************************************************
#define EQEP_QEINT_PCE 0x2U // Position counter error interrupt enable
#define EQEP_QEINT_QPE 0x4U // Quadrature phase error interrupt enable
#define EQEP_QEINT_QDC 0x8U // Quadrature direction change interrupt enable
#define EQEP_QEINT_WTO 0x10U // Watchdog time out interrupt enable
#define EQEP_QEINT_PCU 0x20U // Position counter underflow interrupt enable
#define EQEP_QEINT_PCO 0x40U // Position counter overflow interrupt enable
#define EQEP_QEINT_PCR 0x80U // Position-compare ready interrupt enable
#define EQEP_QEINT_PCM 0x100U // Position-compare match interrupt enable
#define EQEP_QEINT_SEL 0x200U // Strobe event latch interrupt enable
#define EQEP_QEINT_IEL 0x400U // Index event latch interrupt enable
#define EQEP_QEINT_UTO 0x800U // Unit time out interrupt enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the QFLG register
//
//*************************************************************************************************
#define EQEP_QFLG_INT 0x1U // Global interrupt status flag
#define EQEP_QFLG_PCE 0x2U // Position counter error interrupt flag
#define EQEP_QFLG_PHE 0x4U // Quadrature phase error interrupt flag
#define EQEP_QFLG_QDC 0x8U // Quadrature direction change interrupt flag
#define EQEP_QFLG_WTO 0x10U // Watchdog timeout interrupt flag
#define EQEP_QFLG_PCU 0x20U // Position counter underflow interrupt flag
#define EQEP_QFLG_PCO 0x40U // Position counter overflow interrupt flag
#define EQEP_QFLG_PCR 0x80U // Position-compare ready interrupt flag
#define EQEP_QFLG_PCM 0x100U // eQEP compare match event interrupt flag
#define EQEP_QFLG_SEL 0x200U // Strobe event latch interrupt flag
#define EQEP_QFLG_IEL 0x400U // Index event latch interrupt flag
#define EQEP_QFLG_UTO 0x800U // Unit time out interrupt flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the QCLR register
//
//*************************************************************************************************
#define EQEP_QCLR_INT 0x1U // Global interrupt clear flag
#define EQEP_QCLR_PCE 0x2U // Clear position counter error interrupt flag
#define EQEP_QCLR_PHE 0x4U // Clear quadrature phase error interrupt flag
#define EQEP_QCLR_QDC 0x8U // Clear quadrature direction change interrupt flag
#define EQEP_QCLR_WTO 0x10U // Clear watchdog timeout interrupt flag
#define EQEP_QCLR_PCU 0x20U // Clear position counter underflow interrupt flag
#define EQEP_QCLR_PCO 0x40U // Clear position counter overflow interrupt flag
#define EQEP_QCLR_PCR 0x80U // Clear position-compare ready interrupt flag
#define EQEP_QCLR_PCM 0x100U // Clear eQEP compare match event interrupt flag
#define EQEP_QCLR_SEL 0x200U // Clear strobe event latch interrupt flag
#define EQEP_QCLR_IEL 0x400U // Clear index event latch interrupt flag
#define EQEP_QCLR_UTO 0x800U // Clear unit time out interrupt flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the QFRC register
//
//*************************************************************************************************
#define EQEP_QFRC_PCE 0x2U // Force position counter error interrupt
#define EQEP_QFRC_PHE 0x4U // Force quadrature phase error interrupt
#define EQEP_QFRC_QDC 0x8U // Force quadrature direction change interrupt
#define EQEP_QFRC_WTO 0x10U // Force watchdog time out interrupt
#define EQEP_QFRC_PCU 0x20U // Force position counter underflow interrupt
#define EQEP_QFRC_PCO 0x40U // Force position counter overflow interrupt
#define EQEP_QFRC_PCR 0x80U // Force position-compare ready interrupt
#define EQEP_QFRC_PCM 0x100U // Force position-compare match interrupt
#define EQEP_QFRC_SEL 0x200U // Force strobe event latch interrupt
#define EQEP_QFRC_IEL 0x400U // Force index event latch interrupt
#define EQEP_QFRC_UTO 0x800U // Force unit time out interrupt
//*************************************************************************************************
//
// The following are defines for the bit fields in the QEPSTS register
//
//*************************************************************************************************
#define EQEP_QEPSTS_PCEF 0x1U // Position counter error flag.
#define EQEP_QEPSTS_FIMF 0x2U // First index marker flag
#define EQEP_QEPSTS_CDEF 0x4U // Capture direction error flag
#define EQEP_QEPSTS_COEF 0x8U // Capture overflow error flag
#define EQEP_QEPSTS_QDLF 0x10U // eQEP direction latch flag
#define EQEP_QEPSTS_QDF 0x20U // Quadrature direction flag
#define EQEP_QEPSTS_FIDF 0x40U // The first index marker
#define EQEP_QEPSTS_UPEVNT 0x80U // Unit position event flag
#endif
28379d_P_SFRA/device/driverlib/inc/hw_flash.h
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//###########################################################################
//
// FILE: hw_flash.h
//
// TITLE: Definitions for the FLASH registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_FLASH_H
#define HW_FLASH_H
//*************************************************************************************************
//
// The following are defines for the FLASH register offsets
//
//*************************************************************************************************
#define FLASH_O_FRDCNTL 0x0U // Flash Read Control Register
#define FLASH_O_FBAC 0x1EU // Flash Bank Access Control Register
#define FLASH_O_FBFALLBACK 0x20U // Flash Bank Fallback Power Register
#define FLASH_O_FBPRDY 0x22U // Flash Bank Pump Ready Register
#define FLASH_O_FPAC1 0x24U // Flash Pump Access Control Register 1
#define FLASH_O_FMSTAT 0x2AU // Flash Module Status Register
#define FLASH_O_FRD_INTF_CTRL 0x180U // Flash Read Interface Control Register
#define FLASH_O_ECC_ENABLE 0x0U // ECC Enable
#define FLASH_O_SINGLE_ERR_ADDR_LOW 0x2U // Single Error Address Low
#define FLASH_O_SINGLE_ERR_ADDR_HIGH 0x4U // Single Error Address High
#define FLASH_O_UNC_ERR_ADDR_LOW 0x6U // Uncorrectable Error Address Low
#define FLASH_O_UNC_ERR_ADDR_HIGH 0x8U // Uncorrectable Error Address High
#define FLASH_O_ERR_STATUS 0xAU // Error Status
#define FLASH_O_ERR_POS 0xCU // Error Position
#define FLASH_O_ERR_STATUS_CLR 0xEU // Error Status Clear
#define FLASH_O_ERR_CNT 0x10U // Error Control
#define FLASH_O_ERR_THRESHOLD 0x12U // Error Threshold
#define FLASH_O_ERR_INTFLG 0x14U // Error Interrupt Flag
#define FLASH_O_ERR_INTCLR 0x16U // Error Interrupt Flag Clear
#define FLASH_O_FDATAH_TEST 0x18U // Data High Test
#define FLASH_O_FDATAL_TEST 0x1AU // Data Low Test
#define FLASH_O_FADDR_TEST 0x1CU // ECC Test Address
#define FLASH_O_FECC_TEST 0x1EU // ECC Test Address
#define FLASH_O_FECC_CTRL 0x20U // ECC Control
#define FLASH_O_FOUTH_TEST 0x22U // Test Data Out High
#define FLASH_O_FOUTL_TEST 0x24U // Test Data Out Low
#define FLASH_O_FECC_STATUS 0x26U // ECC Status
#define FLASH_O_PUMPREQUEST 0x0U // Flash programming semaphore PUMP request register
//*************************************************************************************************
//
// The following are defines for the bit fields in the FRDCNTL register
//
//*************************************************************************************************
#define FLASH_FRDCNTL_RWAIT_S 8U
#define FLASH_FRDCNTL_RWAIT_M 0xF00U // Random Read Waitstate
//*************************************************************************************************
//
// The following are defines for the bit fields in the FBAC register
//
//*************************************************************************************************
#define FLASH_FBAC_VREADST_S 0U
#define FLASH_FBAC_VREADST_M 0xFFU // VREAD Setup Time Count
//*************************************************************************************************
//
// The following are defines for the bit fields in the FBFALLBACK register
//
//*************************************************************************************************
#define FLASH_FBFALLBACK_BNKPWR0_S 0U
#define FLASH_FBFALLBACK_BNKPWR0_M 0x3U // Bank Power Mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the FBPRDY register
//
//*************************************************************************************************
#define FLASH_FBPRDY_BANKRDY 0x1U // Flash Bank Active Power State
#define FLASH_FBPRDY_PUMPRDY 0x8000U // Flash Pump Active Power Mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the FPAC1 register
//
//*************************************************************************************************
#define FLASH_FPAC1_PMPPWR 0x1U // Charge Pump Fallback Power Mode
#define FLASH_FPAC1_PSLEEP_S 16U
#define FLASH_FPAC1_PSLEEP_M 0xFFF0000U // Pump Sleep Down Count
//*************************************************************************************************
//
// The following are defines for the bit fields in the FMSTAT register
//
//*************************************************************************************************
#define FLASH_FMSTAT_PSUSP 0x2U // Program Suspend.
#define FLASH_FMSTAT_ESUSP 0x4U // Erase Suspend.
#define FLASH_FMSTAT_VOLTSTAT 0x8U // Flash Pump Power Status
#define FLASH_FMSTAT_CSTAT 0x10U // Command Fail Status
#define FLASH_FMSTAT_INVDAT 0x20U // Invalid Data
#define FLASH_FMSTAT_PGM 0x40U // Program Operation Status
#define FLASH_FMSTAT_ERS 0x80U // Erase Operation Status
#define FLASH_FMSTAT_BUSY 0x100U // Busy Bit
#define FLASH_FMSTAT_EV 0x400U // Erase Verify Status
#define FLASH_FMSTAT_PGV 0x1000U // Programming Verify Status
//*************************************************************************************************
//
// The following are defines for the bit fields in the FRD_INTF_CTRL register
//
//*************************************************************************************************
#define FLASH_FRD_INTF_CTRL_PREFETCH_EN 0x1U // Prefetch Enable
#define FLASH_FRD_INTF_CTRL_DATA_CACHE_EN 0x2U // Data Cache Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the ECC_ENABLE register
//
//*************************************************************************************************
#define FLASH_ECC_ENABLE_ENABLE_S 0U
#define FLASH_ECC_ENABLE_ENABLE_M 0xFU // Enable ECC
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_STATUS register
//
//*************************************************************************************************
#define FLASH_ERR_STATUS_FAIL_0_L 0x1U // Lower 64bits Single Bit Error Corrected Value 0
#define FLASH_ERR_STATUS_FAIL_1_L 0x2U // Lower 64bits Single Bit Error Corrected Value 1
#define FLASH_ERR_STATUS_UNC_ERR_L 0x4U // Lower 64 bits Uncorrectable error occurred
#define FLASH_ERR_STATUS_FAIL_0_H 0x10000U // Upper 64bits Single Bit Error Corrected Value 0
#define FLASH_ERR_STATUS_FAIL_1_H 0x20000U // Upper 64bits Single Bit Error Corrected Value 1
#define FLASH_ERR_STATUS_UNC_ERR_H 0x40000U // Upper 64 bits Uncorrectable error occurred
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_POS register
//
//*************************************************************************************************
#define FLASH_ERR_POS_ERR_POS_L_S 0U
#define FLASH_ERR_POS_ERR_POS_L_M 0x3FU // Bit Position of Single bit Error in lower 64
// bits
#define FLASH_ERR_POS_ERR_TYPE_L 0x100U // Error Type in lower 64 bits
#define FLASH_ERR_POS_ERR_POS_H_S 16U
#define FLASH_ERR_POS_ERR_POS_H_M 0x3F0000U // Bit Position of Single bit Error in upper 64
// bits
#define FLASH_ERR_POS_ERR_TYPE_H 0x1000000U // Error Type in upper 64 bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_STATUS_CLR register
//
//*************************************************************************************************
#define FLASH_ERR_STATUS_CLR_FAIL_0_L_CLR 0x1U // Lower 64bits Single Bit Error Corrected
// Value 0 Clear
#define FLASH_ERR_STATUS_CLR_FAIL_1_L_CLR 0x2U // Lower 64bits Single Bit Error Corrected
// Value 1 Clear
#define FLASH_ERR_STATUS_CLR_UNC_ERR_L_CLR 0x4U // Lower 64 bits Uncorrectable error
// occurred Clear
#define FLASH_ERR_STATUS_CLR_FAIL_0_H_CLR 0x10000U // Upper 64bits Single Bit Error Corrected
// Value 0 Clear
#define FLASH_ERR_STATUS_CLR_FAIL_1_H_CLR 0x20000U // Upper 64bits Single Bit Error Corrected
// Value 1 Clear
#define FLASH_ERR_STATUS_CLR_UNC_ERR_H_CLR 0x40000U // Upper 64 bits Uncorrectable error
// occurred Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_CNT register
//
//*************************************************************************************************
#define FLASH_ERR_CNT_ERR_CNT_S 0U
#define FLASH_ERR_CNT_ERR_CNT_M 0xFFFFU // Error counter
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_THRESHOLD register
//
//*************************************************************************************************
#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_S 0U
#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_M 0xFFFFU // Error Threshold
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_INTFLG register
//
//*************************************************************************************************
#define FLASH_ERR_INTFLG_SINGLE_ERR_INTFLG 0x1U // Single Error Interrupt Flag
#define FLASH_ERR_INTFLG_UNC_ERR_INTFLG 0x2U // Uncorrectable Interrupt Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the ERR_INTCLR register
//
//*************************************************************************************************
#define FLASH_ERR_INTCLR_SINGLE_ERR_INTCLR 0x1U // Single Error Interrupt Flag Clear
#define FLASH_ERR_INTCLR_UNC_ERR_INTCLR 0x2U // Uncorrectable Interrupt Flag Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the FADDR_TEST register
//
//*************************************************************************************************
#define FLASH_FADDR_TEST_ADDRL_S 3U
#define FLASH_FADDR_TEST_ADDRL_M 0xFFF8U // ECC Address Low
#define FLASH_FADDR_TEST_ADDRH_S 16U
#define FLASH_FADDR_TEST_ADDRH_M 0x3F0000U // ECC Address High
//*************************************************************************************************
//
// The following are defines for the bit fields in the FECC_TEST register
//
//*************************************************************************************************
#define FLASH_FECC_TEST_ECC_S 0U
#define FLASH_FECC_TEST_ECC_M 0xFFU // ECC Control Bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the FECC_CTRL register
//
//*************************************************************************************************
#define FLASH_FECC_CTRL_ECC_TEST_EN 0x1U // Enable ECC Test Logic
#define FLASH_FECC_CTRL_ECC_SELECT 0x2U // ECC Bit Select
#define FLASH_FECC_CTRL_DO_ECC_CALC 0x4U // Enable ECC Calculation
//*************************************************************************************************
//
// The following are defines for the bit fields in the FECC_STATUS register
//
//*************************************************************************************************
#define FLASH_FECC_STATUS_SINGLE_ERR 0x1U // Test Result is Single Bit Error
#define FLASH_FECC_STATUS_UNC_ERR 0x2U // Test Result is Uncorrectable Error
#define FLASH_FECC_STATUS_DATA_ERR_POS_S 2U
#define FLASH_FECC_STATUS_DATA_ERR_POS_M 0xFCU // Holds Bit Position of Error
#define FLASH_FECC_STATUS_ERR_TYPE 0x100U // Holds Bit Position of 8 Check Bits of Error
//*************************************************************************************************
//
// The following are defines for the bit fields in the PUMPREQUEST register
//
//*************************************************************************************************
#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_S 0U
#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_M 0x3U // Flash Pump Request Semaphore between
// CPU1 and CPU2
#define FLASH_PUMPREQUEST_KEY_S 16U
#define FLASH_PUMPREQUEST_KEY_M 0xFFFF0000U // Key Qualifier for writes to this
// register
#endif
28379d_P_SFRA/device/driverlib/inc/hw_gpio.h
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28379d_P_SFRA/device/driverlib/inc/hw_hic.h
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//###########################################################################
//
// FILE: hw_hic.h
//
// TITLE: Definitions for the HIC registers.
//
//###########################################################################
// $TI Release: $
// $Release Date: $
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_HIC_H
#define HW_HIC_H
//*************************************************************************************************
//
// The following are defines for the HIC register offsets
//
//*************************************************************************************************
#define HIC_O_REV 0x0U // Module Revision Register
#define HIC_O_GCR 0x2U // Global Control Register
#define HIC_O_LOCK 0x4U // Lock Register
#define HIC_O_MODECR 0x6U // Mode Control Register
#define HIC_O_PINPOLCR 0x8U // Pin Polarity Control Register
#define HIC_O_BASESEL 0xAU // Base Select Register
#define HIC_O_HOSTCR 0xCU // Host Control Register
#define HIC_O_ERRADDR 0xEU // Host Error Address register
#define HIC_O_H2DTOKEN 0x10U // Host to Device Token Register
#define HIC_O_D2HTOKEN 0x12U // Devie to Host Token Register
#define HIC_O_DBADDR0 0x14U // Device Base Address Register 0
#define HIC_O_DBADDR1 0x16U // Device Base Address Register 1
#define HIC_O_DBADDR2 0x18U // Device Base Address Register 2
#define HIC_O_DBADDR3 0x1AU // Device Base Address Register 3
#define HIC_O_DBADDR4 0x1CU // Device Base Address Register 4
#define HIC_O_DBADDR5 0x1EU // Device Base Address Register 5
#define HIC_O_DBADDR6 0x20U // Device Base Address Register 6
#define HIC_O_DBADDR7 0x22U // Device Base Address Register 7
#define HIC_O_H2DINTEN 0x28U // H2D Interrupt Enable
#define HIC_O_H2DINTFLG 0x2AU // H2D Interrupt status Flag
#define HIC_O_H2DINTCLR 0x2CU // H2D Interrupt status Clear
#define HIC_O_H2DINTFRC 0x2EU // H2D Interrupt Set Force
#define HIC_O_D2HINTEN 0x30U // D2H Interrupt Enable
#define HIC_O_D2HINTFLG 0x32U // D2H Interrupt status Flag
#define HIC_O_D2HINTCLR 0x34U // D2H Interrupt status Clear
#define HIC_O_D2HINTFRC 0x36U // D2H Interrupt Set Force
#define HIC_O_ACCVIOADDR 0x38U // Access Violation Address
#define HIC_O_H2D_BUF0 0x40U // Host to Device Buffer 0
#define HIC_O_H2D_BUF1 0x42U // Host to Device Buffer 1
#define HIC_O_H2D_BUF2 0x44U // Host to Device Buffer 2
#define HIC_O_H2D_BUF3 0x46U // Host to Device Buffer 3
#define HIC_O_H2D_BUF4 0x48U // Host to Device Buffer 4
#define HIC_O_H2D_BUF5 0x4AU // Host to Device Buffer 5
#define HIC_O_H2D_BUF6 0x4CU // Host to Device Buffer 6
#define HIC_O_H2D_BUF7 0x4EU // Host to Device Buffer 7
#define HIC_O_H2D_BUF8 0x50U // Host to Device Buffer 8
#define HIC_O_H2D_BUF9 0x52U // Host to Device Buffer 9
#define HIC_O_H2D_BUF10 0x54U // Host to Device Buffer 10
#define HIC_O_H2D_BUF11 0x56U // Host to Device Buffer 11
#define HIC_O_H2D_BUF12 0x58U // Host to Device Buffer 12
#define HIC_O_H2D_BUF13 0x5AU // Host to Device Buffer 13
#define HIC_O_H2D_BUF14 0x5CU // Host to Device Buffer 14
#define HIC_O_H2D_BUF15 0x5EU // Host to Device Buffer 15
#define HIC_O_D2H_BUF0 0x60U // Device to Host Buffer 0
#define HIC_O_D2H_BUF1 0x62U // Device to Host Buffer 1
#define HIC_O_D2H_BUF2 0x64U // Device to Host Buffer 2
#define HIC_O_D2H_BUF3 0x66U // Device to Host Buffer 3
#define HIC_O_D2H_BUF4 0x68U // Device to Host Buffer 4
#define HIC_O_D2H_BUF5 0x6AU // Device to Host Buffer 5
#define HIC_O_D2H_BUF6 0x6CU // Device to Host Buffer 6
#define HIC_O_D2H_BUF7 0x6EU // Device to Host Buffer 7
#define HIC_O_D2H_BUF8 0x70U // Device to Host Buffer 8
#define HIC_O_D2H_BUF9 0x72U // Device to Host Buffer 9
#define HIC_O_D2H_BUF10 0x74U // Device to Host Buffer 10
#define HIC_O_D2H_BUF11 0x76U // Device to Host Buffer 11
#define HIC_O_D2H_BUF12 0x78U // Device to Host Buffer 12
#define HIC_O_D2H_BUF13 0x7AU // Device to Host Buffer 13
#define HIC_O_D2H_BUF14 0x7CU // Device to Host Buffer 14
#define HIC_O_D2H_BUF15 0x7EU // Device to Host Buffer 15
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICREV register
//
//*************************************************************************************************
#define HIC_REV_MINOR_S 0U
#define HIC_REV_MINOR_M 0x3FU // Minor Revision Number
#define HIC_REV_CUSTOM_S 6U
#define HIC_REV_CUSTOM_M 0xC0U // Custom Module Number
#define HIC_REV_MAJOR_S 8U
#define HIC_REV_MAJOR_M 0x700U // Major Revision Number
#define HIC_REV_RTL_S 11U
#define HIC_REV_RTL_M 0xF800U // Design Release Number
#define HIC_REV_FUNC_S 16U
#define HIC_REV_FUNC_M 0xFFF0000U // Functional Release Number
#define HIC_REV_SCHEME_S 30U
#define HIC_REV_SCHEME_M 0xC0000000U // Defines Scheme for Module
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICGCR register
//
//*************************************************************************************************
#define HIC_GCR_HICEN_S 0U
#define HIC_GCR_HICEN_M 0xFU // Host Interface Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICLOCK register
//
//*************************************************************************************************
#define HIC_LOCK_LOCK 0x1U // LOCK enable
#define HIC_LOCK_WRITE_ENABLE_KEY_S 16U
#define HIC_LOCK_WRITE_ENABLE_KEY_M 0xFFFF0000U // Key for enabling write
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICMODECR register
//
//*************************************************************************************************
#define HIC_MODECR_DW_MODE_S 0U
#define HIC_MODECR_DW_MODE_M 0x3U // Data Width Mode
#define HIC_MODECR_RW_MODE 0x10U // Read-Write Mode
#define HIC_MODECR_BEN_PRESENT 0x20U // Byte Enable Pins are present
#define HIC_MODECR_RDY_PRESENT 0x40U // Ready pin present
#define HIC_MODECR_H2DBUF_DEVWREN 0x100U // Write Enable for Device to H2D Buffer
#define HIC_MODECR_D2HBUF_HOSTWREN 0x200U // Write Enable for Host to D2H Buffer
#define HIC_MODECR_EN_DEVACC 0x400U // Enable Host access to Device region
#define HIC_MODECR_EN_HOSTWREALLOW 0x800U // Enable Host Write to EALLOWCTL register
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICPINPOLCR register
//
//*************************************************************************************************
#define HIC_PINPOLCR_CS_POL 0x1U // Chip Select Polarity
#define HIC_PINPOLCR_BEN_POL 0x2U // Byte Enable Polarity
#define HIC_PINPOLCR_OE_POL 0x4U // Output Enable Polarity
#define HIC_PINPOLCR_WE_POL 0x8U // Write Enable Polarity
#define HIC_PINPOLCR_RDY_POL 0x10U // Ready Polarity
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICBASESEL register
//
//*************************************************************************************************
#define HIC_BASESEL_BASE_SELECT_S 0U
#define HIC_BASESEL_BASE_SELECT_M 0x7U // Base Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICHOSTCR register
//
//*************************************************************************************************
#define HIC_HOSTCR_EALLOW_EN 0x1U // EALLOW Enable
#define HIC_HOSTCR_ACCSIZE 0x2U // Access Size
#define HIC_HOSTCR_PAGESEL 0x4U // Page Select
#define HIC_HOSTCR_HKEY_S 8U
#define HIC_HOSTCR_HKEY_M 0xFF00U // Host Key
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICERRADDR register
//
//*************************************************************************************************
#define HIC_ERRADDR_H2D_ERR_ADDR_S 0U
#define HIC_ERRADDR_H2D_ERR_ADDR_M 0xFFU // Address of the Host bus captured upon an
// error for Device
#define HIC_ERRADDR_H2D_BASE_SEL_S 12U
#define HIC_ERRADDR_H2D_BASE_SEL_M 0x7000U // Base Select corresponding to H2D error event
#define HIC_ERRADDR_D2H_ERR_ADDR_S 16U
#define HIC_ERRADDR_D2H_ERR_ADDR_M 0xFF0000U // Address of the Host bus captured upon an
// error for Host
#define HIC_ERRADDR_D2H_BASE_SEL_S 28U
#define HIC_ERRADDR_D2H_BASE_SEL_M 0x70000000U // Base Select corresponding to D2H error event
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR0 register
//
//*************************************************************************************************
#define HIC_DBADDR0_BASE_ADDR_S 7U
#define HIC_DBADDR0_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR1 register
//
//*************************************************************************************************
#define HIC_DBADDR1_BASE_ADDR_S 7U
#define HIC_DBADDR1_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR2 register
//
//*************************************************************************************************
#define HIC_DBADDR2_BASE_ADDR_S 7U
#define HIC_DBADDR2_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR3 register
//
//*************************************************************************************************
#define HIC_DBADDR3_BASE_ADDR_S 7U
#define HIC_DBADDR3_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR4 register
//
//*************************************************************************************************
#define HIC_DBADDR4_BASE_ADDR_S 7U
#define HIC_DBADDR4_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR5 register
//
//*************************************************************************************************
#define HIC_DBADDR5_BASE_ADDR_S 7U
#define HIC_DBADDR5_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR6 register
//
//*************************************************************************************************
#define HIC_DBADDR6_BASE_ADDR_S 7U
#define HIC_DBADDR6_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICDBADDR7 register
//
//*************************************************************************************************
#define HIC_DBADDR7_BASE_ADDR_S 7U
#define HIC_DBADDR7_BASE_ADDR_M 0xFFFFFF80U // Base address of device region
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICH2DINTEN register
//
//*************************************************************************************************
#define HIC_H2DINTEN_H2D_INTEN 0x1U // Host To Device Interrupt Enable
#define HIC_H2DINTEN_BUSERR_INTEN 0x2U // BusError Interrupt Enable
#define HIC_H2DINTEN_ILLWR_INTEN 0x4U // Illegal Write event interrupt enable
#define HIC_H2DINTEN_ILLRD_INTEN 0x8U // Illegal Read event interrupt enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICH2DINTFLG register
//
//*************************************************************************************************
#define HIC_H2DINTFLG_H2D_FLG 0x1U // Host To Device Interrupt Flag
#define HIC_H2DINTFLG_BUSERR_FLG 0x2U // BusError Interrupt Flag
#define HIC_H2DINTFLG_ILLWR_FLG 0x4U // Illegal write event interrupt flag
#define HIC_H2DINTFLG_ILLRD_FLG 0x8U // Illegal read event interrupt flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICH2DINTCLR register
//
//*************************************************************************************************
#define HIC_H2DINTCLR_H2D_CLR 0x1U // Host To Device Interrupt Clear
#define HIC_H2DINTCLR_BUSERR_CLR 0x2U // BusError Interrupt Clear
#define HIC_H2DINTCLR_ILLWR_CLR 0x4U // Illegal Write Interrupt Clear
#define HIC_H2DINTCLR_ILLRD_CLR 0x8U // Illegal Read Interrupt Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICH2DINTFRC register
//
//*************************************************************************************************
#define HIC_H2DINTFRC_H2D_INTFRC 0x1U // Host To Device Force Set
#define HIC_H2DINTFRC_BUSERR_INTFRC 0x2U // BusError Interrupt Force Set
#define HIC_H2DINTFRC_ILLWR_INTFRC 0x4U // Illegal Write Interrupt Force Set
#define HIC_H2DINTFRC_ILLRD_INTFRC 0x8U // Illegal Read Interrupt Force Set
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICD2HINTEN register
//
//*************************************************************************************************
#define HIC_D2HINTEN_D2H_INTEN 0x1U // Device to Host Data Ready Interrupt Enable
#define HIC_D2HINTEN_BUSERR_INTEN 0x2U // BusError Interrupt Enable
#define HIC_D2HINTEN_ILLWR_INTEN 0x4U // Illegal Write event Interrupt Enable
#define HIC_D2HINTEN_ILLRD_INTEN 0x8U // Illegal Read event Interrupt Enable
#define HIC_D2HINTEN_ACCVIO_INTEN 0x10U // Access Violation Interrupt Enable
#define HIC_D2HINTEN_EVTRIG_INTEN_S 16U
#define HIC_D2HINTEN_EVTRIG_INTEN_M 0xFFFF0000U // Event Trigger Interrupt Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICD2HINTFLG register
//
//*************************************************************************************************
#define HIC_D2HINTFLG_D2H_FLG 0x1U // Device to Host Data Ready Flag
#define HIC_D2HINTFLG_BUSERR_FLG 0x2U // BusError Flag
#define HIC_D2HINTFLG_ILLWR_FLG 0x4U // Illegal Write event Flag
#define HIC_D2HINTFLG_ILLRD_FLG 0x8U // Illegal Read event Flag
#define HIC_D2HINTFLG_ACCVIO_FLG 0x10U // Access Violation Flag
#define HIC_D2HINTFLG_EVTRIG_FLG_S 16U
#define HIC_D2HINTFLG_EVTRIG_FLG_M 0xFFFF0000U // Event Trigger Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICD2HINTCLR register
//
//*************************************************************************************************
#define HIC_D2HINTCLR_D2H_CLR 0x1U // Device to Host Interrupt Clear
#define HIC_D2HINTCLR_BUSERR_CLR 0x2U // BusError Interrupt Clear
#define HIC_D2HINTCLR_ILLWR_CLR 0x4U // Illegal Write Interrupt Clear
#define HIC_D2HINTCLR_ILLRD_CLR 0x8U // Illegal Read Interrupt Clear
#define HIC_D2HINTCLR_ACCVIO_CLR 0x10U // Access Violation Interrupt Clear
#define HIC_D2HINTCLR_EVTRIG_CLR_S 16U
#define HIC_D2HINTCLR_EVTRIG_CLR_M 0xFFFF0000U // Event Trigger Interrupt Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the HICD2HINTFRC register
//
//*************************************************************************************************
#define HIC_D2HINTFRC_D2H_INTFRC 0x1U // Device to Host Force Set
#define HIC_D2HINTFRC_BUSERR_INTFRC 0x2U // BusError Interrupt Force Set
#define HIC_D2HINTFRC_ILLWR_INTFRC 0x4U // Illegal Write Interrupt Force Set
#define HIC_D2HINTFRC_ILLRD_INTFRC 0x8U // Illegal Read Interrupt Force Set
#define HIC_D2HINTFRC_ACCVIO_INTFRC 0x10U // Access Violation Interrupt Force Set
#define HIC_D2HINTFRC_EVTRIG_INTFRC_S 16U
#define HIC_D2HINTFRC_EVTRIG_INTFRC_M 0xFFFF0000U // Event Trigger Interrupt Force Set
#endif
28379d_P_SFRA/device/driverlib/inc/hw_hrpwm.h
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28379d_P_SFRA/device/driverlib/inc/hw_i2c.h
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//###########################################################################
//
// FILE: hw_i2c.h
//
// TITLE: Definitions for the I2C registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_I2C_H
#define HW_I2C_H
//*************************************************************************************************
//
// The following are defines for the I2C register offsets
//
//*************************************************************************************************
#define I2C_O_OAR 0x0U // I2C Own address
#define I2C_O_IER 0x1U // I2C Interrupt Enable
#define I2C_O_STR 0x2U // I2C Status
#define I2C_O_CLKL 0x3U // I2C Clock low-time divider
#define I2C_O_CLKH 0x4U // I2C Clock high-time divider
#define I2C_O_CNT 0x5U // I2C Data count
#define I2C_O_DRR 0x6U // I2C Data receive
#define I2C_O_SAR 0x7U // I2C Slave address
#define I2C_O_DXR 0x8U // I2C Data Transmit
#define I2C_O_MDR 0x9U // I2C Mode
#define I2C_O_ISRC 0xAU // I2C Interrupt Source
#define I2C_O_EMDR 0xBU // I2C Extended Mode
#define I2C_O_PSC 0xCU // I2C Prescaler
#define I2C_O_FFTX 0x20U // I2C FIFO Transmit
#define I2C_O_FFRX 0x21U // I2C FIFO Receive
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2COAR register
//
//*************************************************************************************************
#define I2C_OAR_OAR_S 0U
#define I2C_OAR_OAR_M 0x3FFU // I2C Own address
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CIER register
//
//*************************************************************************************************
#define I2C_IER_ARBL 0x1U // Arbitration-lost interrupt enable
#define I2C_IER_NACK 0x2U // No-acknowledgment interrupt enable
#define I2C_IER_ARDY 0x4U // Register-access-ready interrupt enable
#define I2C_IER_RRDY 0x8U // Receive-data-ready interrupt enable
#define I2C_IER_XRDY 0x10U // Transmit-data-ready interrupt enable
#define I2C_IER_SCD 0x20U // Stop condition detected interrupt enable
#define I2C_IER_AAS 0x40U // Addressed as slave interrupt enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CSTR register
//
//*************************************************************************************************
#define I2C_STR_ARBL 0x1U // Arbitration-lost interrupt flag bit
#define I2C_STR_NACK 0x2U // No-acknowledgment interrupt flag bit.
#define I2C_STR_ARDY 0x4U // Register-access-ready interrupt flag bit
#define I2C_STR_RRDY 0x8U // Receive-data-ready interrupt flag bit.
#define I2C_STR_XRDY 0x10U // Transmit-data-ready interrupt flag bit.
#define I2C_STR_SCD 0x20U // Stop condition detected bit.
#define I2C_STR_AD0 0x100U // Address 0 bits
#define I2C_STR_AAS 0x200U // Addressed-as-slave bit
#define I2C_STR_XSMT 0x400U // Transmit shift register empty bit.
#define I2C_STR_RSFULL 0x800U // Receive shift register full bit.
#define I2C_STR_BB 0x1000U // Bus busy bit.
#define I2C_STR_NACKSNT 0x2000U // NACK sent bit.
#define I2C_STR_SDIR 0x4000U // Slave direction bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CDRR register
//
//*************************************************************************************************
#define I2C_DRR_DATA_S 0U
#define I2C_DRR_DATA_M 0xFFU // Receive data
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CSAR register
//
//*************************************************************************************************
#define I2C_SAR_SAR_S 0U
#define I2C_SAR_SAR_M 0x3FFU // Slave Address
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CDXR register
//
//*************************************************************************************************
#define I2C_DXR_DATA_S 0U
#define I2C_DXR_DATA_M 0xFFU // Transmit data
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CMDR register
//
//*************************************************************************************************
#define I2C_MDR_BC_S 0U
#define I2C_MDR_BC_M 0x7U // Bit count bits.
#define I2C_MDR_FDF 0x8U // Free Data Format
#define I2C_MDR_STB 0x10U // START Byte Mode
#define I2C_MDR_IRS 0x20U // I2C Module Reset
#define I2C_MDR_DLB 0x40U // Digital Loopback Mode
#define I2C_MDR_RM 0x80U // Repeat Mode
#define I2C_MDR_XA 0x100U // Expanded Address Mode
#define I2C_MDR_TRX 0x200U // Transmitter Mode
#define I2C_MDR_MST 0x400U // Master Mode
#define I2C_MDR_STP 0x800U // STOP Condition
#define I2C_MDR_STT 0x2000U // START condition bit
#define I2C_MDR_FREE 0x4000U // Debug Action
#define I2C_MDR_NACKMOD 0x8000U // NACK mode bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CISRC register
//
//*************************************************************************************************
#define I2C_ISRC_INTCODE_S 0U
#define I2C_ISRC_INTCODE_M 0x7U // Interrupt code bits.
#define I2C_ISRC_WRITE_ZEROS_S 8U
#define I2C_ISRC_WRITE_ZEROS_M 0xF00U // Always write all 0s to this field
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CEMDR register
//
//*************************************************************************************************
#define I2C_EMDR_BC 0x1U // Backwards compatibility mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CPSC register
//
//*************************************************************************************************
#define I2C_PSC_IPSC_S 0U
#define I2C_PSC_IPSC_M 0xFFU // I2C Prescaler Divide Down
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CFFTX register
//
//*************************************************************************************************
#define I2C_FFTX_TXFFIL_S 0U
#define I2C_FFTX_TXFFIL_M 0x1FU // Transmit FIFO Interrupt Level
#define I2C_FFTX_TXFFIENA 0x20U // Transmit FIFO Interrupt Enable
#define I2C_FFTX_TXFFINTCLR 0x40U // Transmit FIFO Interrupt Flag Clear
#define I2C_FFTX_TXFFINT 0x80U // Transmit FIFO Interrupt Flag
#define I2C_FFTX_TXFFST_S 8U
#define I2C_FFTX_TXFFST_M 0x1F00U // Transmit FIFO Status
#define I2C_FFTX_TXFFRST 0x2000U // Transmit FIFO Reset
#define I2C_FFTX_I2CFFEN 0x4000U // Transmit FIFO Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the I2CFFRX register
//
//*************************************************************************************************
#define I2C_FFRX_RXFFIL_S 0U
#define I2C_FFRX_RXFFIL_M 0x1FU // Receive FIFO Interrupt Level
#define I2C_FFRX_RXFFIENA 0x20U // Receive FIFO Interrupt Enable
#define I2C_FFRX_RXFFINTCLR 0x40U // Receive FIFO Interrupt Flag Clear
#define I2C_FFRX_RXFFINT 0x80U // Receive FIFO Interrupt Flag
#define I2C_FFRX_RXFFST_S 8U
#define I2C_FFRX_RXFFST_M 0x1F00U // Receive FIFO Status
#define I2C_FFRX_RXFFRST 0x2000U // Receive FIFO Reset
#endif
28379d_P_SFRA/device/driverlib/inc/hw_inputxbar.h
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//###########################################################################
//
// FILE: hw_inputxbar.h
//
// TITLE: Definitions for the XBAR registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_INPUTXBAR_H
#define HW_INPUTXBAR_H
//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************
#define XBAR_O_INPUT1SELECT 0x0U // INPUT1 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT2SELECT 0x1U // INPUT2 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT3SELECT 0x2U // INPUT3 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT4SELECT 0x3U // INPUT4 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT5SELECT 0x4U // INPUT5 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT6SELECT 0x5U // INPUT6 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT7SELECT 0x6U // INPUT7 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT8SELECT 0x7U // INPUT8 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT9SELECT 0x8U // INPUT9 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT10SELECT 0x9U // INPUT10 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT11SELECT 0xAU // INPUT11 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT12SELECT 0xBU // INPUT12 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT13SELECT 0xCU // INPUT13 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUT14SELECT 0xDU // INPUT14 Input Select Register (GPIO0 to x)
#define XBAR_O_INPUTSELECTLOCK 0x1EU // Input Select Lock Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the INPUTSELECTLOCK register
//
//*************************************************************************************************
#define XBAR_INPUTSELECTLOCK_INPUT1SELECT 0x1U // Lock bit for INPUT1SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT2SELECT 0x2U // Lock bit for INPUT2SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT3SELECT 0x4U // Lock bit for INPUT3SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT4SELECT 0x8U // Lock bit for INPUT4SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT5SELECT 0x10U // Lock bit for INPUT5SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT6SELECT 0x20U // Lock bit for INPUT6SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT7SELECT 0x40U // Lock bit for INPUT7SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT8SELECT 0x80U // Lock bit for INPUT8SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT9SELECT 0x100U // Lock bit for INPUT9SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT10SELECT 0x200U // Lock bit for INPUT10SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT11SELECT 0x400U // Lock bit for INPUT11SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT12SELECT 0x800U // Lock bit for INPUT12SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT13SELECT 0x1000U // Lock bit for INPUT13SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT14SELECT 0x2000U // Lock bit for INPUT14SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT15SELECT 0x4000U // Lock bit for INPUT15SELECT Register
#define XBAR_INPUTSELECTLOCK_INPUT16SELECT 0x8000U // Lock bit for INPUT16SELECT Register
#endif
28379d_P_SFRA/device/driverlib/inc/hw_ints.h
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//###########################################################################
//
// FILE: hw_ints.h
//
// TITLE: Definitions of interrupt numbers for use with interrupt.c.
//
//###########################################################################
//
//
//###########################################################################
#ifndef HW_INTS_H
#define HW_INTS_H
//*****************************************************************************
//
// PIE Interrupt Numbers
//
// 0x00FF = PIE Table Row #
// 0xFF00 = PIE Table Column #
// 0xFFFF0000 = PIE Vector ID
//
//*****************************************************************************
// Lower PIE Group 1
#define INT_ADCA1 0x00200101U // 1.1 - ADCA Interrupt 1
#define INT_ADCB1 0x00210102U // 1.2 - ADCB Interrupt 1
#define INT_ADCC1 0x00220103U // 1.3 - ADCC Interrupt 1
#define INT_XINT1 0x00230104U // 1.4 - XINT1 Interrupt
#define INT_XINT2 0x00240105U // 1.5 - XINT2 Interrupt
#define INT_ADCD1 0x00250106U // 1.6 - ADCD Interrupt 1
#define INT_TIMER0 0x00260107U // 1.7 - Timer 0 Interrupt
#define INT_WAKE 0x00270108U // 1.8 - Standby and Halt Wakeup Interrupt
// Lower PIE Group 2
#define INT_EPWM1_TZ 0x00280201U // 2.1 - ePWM1 Trip Zone Interrupt
#define INT_EPWM2_TZ 0x00290202U // 2.2 - ePWM2 Trip Zone Interrupt
#define INT_EPWM3_TZ 0x002A0203U // 2.3 - ePWM3 Trip Zone Interrupt
#define INT_EPWM4_TZ 0x002B0204U // 2.4 - ePWM4 Trip Zone Interrupt
#define INT_EPWM5_TZ 0x002C0205U // 2.5 - ePWM5 Trip Zone Interrupt
#define INT_EPWM6_TZ 0x002D0206U // 2.6 - ePWM6 Trip Zone Interrupt
#define INT_EPWM7_TZ 0x002E0207U // 2.7 - ePWM7 Trip Zone Interrupt
#define INT_EPWM8_TZ 0x002F0208U // 2.8 - ePWM8 Trip Zone Interrupt
// Lower PIE Group 3
#define INT_EPWM1 0x00300301U // 3.1 - ePWM1 Interrupt
#define INT_EPWM2 0x00310302U // 3.2 - ePWM2 Interrupt
#define INT_EPWM3 0x00320303U // 3.3 - ePWM3 Interrupt
#define INT_EPWM4 0x00330304U // 3.4 - ePWM4 Interrupt
#define INT_EPWM5 0x00340305U // 3.5 - ePWM5 Interrupt
#define INT_EPWM6 0x00350306U // 3.6 - ePWM6 Interrupt
#define INT_EPWM7 0x00360307U // 3.7 - ePWM7 Interrupt
#define INT_EPWM8 0x00370308U // 3.8 - ePWM8 Interrupt
// Lower PIE Group 4
#define INT_ECAP1 0x00380401U // 4.1 - eCAP1 Interrupt
#define INT_ECAP2 0x00390402U // 4.2 - eCAP2 Interrupt
#define INT_ECAP3 0x003A0403U // 4.3 - eCAP3 Interrupt
#define INT_ECAP4 0x003B0404U // 4.4 - eCAP4 Interrupt
#define INT_ECAP5 0x003C0405U // 4.5 - eCAP5 Interrupt
#define INT_ECAP6 0x003D0406U // 4.6 - eCAP6 Interrupt
// Lower PIE Group 5
#define INT_EQEP1 0x00400501U // 5.1 - eQEP1 Interrupt
#define INT_EQEP2 0x00410502U // 5.2 - eQEP2 Interrupt
#define INT_EQEP3 0x00420503U // 5.3 - eQEP3 Interrupt
#define INT_CLB1 0x00440505U // 5.5 - CLB1 (Reconfigurable Logic) Interrupt
#define INT_CLB2 0x00450506U // 5.6 - CLB2 (Reconfigurable Logic) Interrupt
#define INT_CLB3 0x00460507U // 5.7 - CLB3 (Reconfigurable Logic) Interrupt
#define INT_CLB4 0x00470508U // 5.8 - CLB4 (Reconfigurable Logic) Interrupt
// Lower PIE Group 6
#define INT_SPIA_RX 0x00480601U // 6.1 - SPIA Receive Interrupt
#define INT_SPIA_TX 0x00490602U // 6.2 - SPIA Transmit Interrupt
#define INT_SPIB_RX 0x004A0603U // 6.3 - SPIB Receive Interrupt
#define INT_SPIB_TX 0x004B0604U // 6.4 - SPIB Transmit Interrupt
#define INT_MCBSPA_RX 0x004C0605U // 6.5 - McBSPA Receive Interrupt
#define INT_MCBSPA_TX 0x004D0606U // 6.6 - McBSPA Transmit Interrupt
#define INT_MCBSPB_RX 0x004E0607U // 6.7 - McBSPB Receive Interrupt
#define INT_MCBSPB_TX 0x004F0608U // 6.8 - McBSPB Transmit Interrupt
// Lower PIE Group 7
#define INT_DMA_CH1 0x00500701U // 7.1 - DMA Channel 1 Interrupt
#define INT_DMA_CH2 0x00510702U // 7.2 - DMA Channel 2 Interrupt
#define INT_DMA_CH3 0x00520703U // 7.3 - DMA Channel 3 Interrupt
#define INT_DMA_CH4 0x00530704U // 7.4 - DMA Channel 4 Interrupt
#define INT_DMA_CH5 0x00540705U // 7.5 - DMA Channel 5 Interrupt
#define INT_DMA_CH6 0x00550706U // 7.6 - DMA Channel 6 Interrupt
// Lower PIE Group 8
#define INT_I2CA 0x00580801U // 8.1 - I2CA Interrupt 1
#define INT_I2CA_FIFO 0x00590802U // 8.2 - I2CA Interrupt 2
#define INT_I2CB 0x005A0803U // 8.3 - I2CB Interrupt 1
#define INT_I2CB_FIFO 0x005B0804U // 8.4 - I2CB Interrupt 2
#define INT_SCIC_RX 0x005C0805U // 8.5 - SCIC Receive Interrupt
#define INT_SCIC_TX 0x005D0806U // 8.6 - SCIC Transmit Interrupt
#define INT_SCID_RX 0x005E0807U // 8.7 - SCID Receive Interrupt
#define INT_SCID_TX 0x005F0808U // 8.8 - SCID Transmit Interrupt
// Lower PIE Group 9
#define INT_SCIA_RX 0x00600901U // 9.1 - SCIA Receive Interrupt
#define INT_SCIA_TX 0x00610902U // 9.2 - SCIA Transmit Interrupt
#define INT_SCIB_RX 0x00620903U // 9.3 - SCIB Receive Interrupt
#define INT_SCIB_TX 0x00630904U // 9.4 - SCIB Transmit Interrupt
#define INT_CANA0 0x00640905U // 9.5 - CANA Interrupt 0
#define INT_CANA1 0x00650906U // 9.6 - CANA Interrupt 1
#define INT_CANB0 0x00660907U // 9.7 - CANB Interrupt 0
#define INT_CANB1 0x00670908U // 9.8 - CANB Interrupt 1
// Lower PIE Group 10
#define INT_ADCA_EVT 0x00680A01U // 10.1 - ADCA Event Interrupt
#define INT_ADCA2 0x00690A02U // 10.2 - ADCA Interrupt 2
#define INT_ADCA3 0x006A0A03U // 10.3 - ADCA Interrupt 3
#define INT_ADCA4 0x006B0A04U // 10.4 - ADCA Interrupt 4
#define INT_ADCB_EVT 0x006C0A05U // 10.5 - ADCB Event Interrupt
#define INT_ADCB2 0x006D0A06U // 10.6 - ADCB Interrupt 2
#define INT_ADCB3 0x006E0A07U // 10.7 - ADCB Interrupt 3
#define INT_ADCB4 0x006F0A08U // 10.8 - ADCB Interrupt 4
// Lower PIE Group 11
#define INT_CLA1_1 0x00700B01U // 11.1 - CLA1 Interrupt 1
#define INT_CLA1_2 0x00710B02U // 11.2 - CLA1 Interrupt 2
#define INT_CLA1_3 0x00720B03U // 11.3 - CLA1 Interrupt 3
#define INT_CLA1_4 0x00730B04U // 11.4 - CLA1 Interrupt 4
#define INT_CLA1_5 0x00740B05U // 11.5 - CLA1 Interrupt 5
#define INT_CLA1_6 0x00750B06U // 11.6 - CLA1 Interrupt 6
#define INT_CLA1_7 0x00760B07U // 11.7 - CLA1 Interrupt 7
#define INT_CLA1_8 0x00770B08U // 11.8 - CLA1 Interrupt 8
// Lower PIE Group 12
#define INT_XINT3 0x00780C01U // 12.1 - XINT3 Interrupt
#define INT_XINT4 0x00790C02U // 12.2 - XINT4 Interrupt
#define INT_XINT5 0x007A0C03U // 12.3 - XINT5 Interrupt
#define INT_PBIST 0x007B0C04U // 12.4 - PBIST Interrupt
#define INT_FMC 0x007C0C05U // 12.5 - Flash Wrapper Operation Done Interrupt
#define INT_VCU 0x007D0C06U // 12.6 - VCU Interrupt
#define INT_FPU_OVERFLOW 0x007E0C07U // 12.7 - FPU Overflow Interrupt
#define INT_FPU_UNDERFLOW 0x007F0C08U // 12.8 - FPU Underflow Interrupt
// Upper PIE Group 1
#define INT_IPC_0 0x0084010DU // 1.13 - IPC Interrupt 1
#define INT_IPC_1 0x0085010EU // 1.14 - IPC Interrupt 2
#define INT_IPC_2 0x0086010FU // 1.15 - IPC Interrupt 3
#define INT_IPC_3 0x00870110U // 1.16 - IPC Interrupt 4
// Upper PIE Group 2
#define INT_EPWM9_TZ 0x00880209U // 2.9 - ePWM9 Trip Zone Interrupt
#define INT_EPWM10_TZ 0x0089020AU // 2.10 - ePWM10 Trip Zone Interrupt
#define INT_EPWM11_TZ 0x008A020BU // 2.11 - ePWM11 Trip Zone Interrupt
#define INT_EPWM12_TZ 0x008B020CU // 2.12 - ePWM12 Trip Zone Interrupt
// Upper PIE Group 3
#define INT_EPWM9 0x00900309U // 3.9 - ePWM9 Interrupt
#define INT_EPWM10 0x0091030AU // 3.10 - ePWM10 Interrupt
#define INT_EPWM11 0x0092030BU // 3.11 - ePWM11 Interrupt
#define INT_EPWM12 0x0093030CU // 3.12 - ePWM12 Interrupt
// Upper PIE Group 5
#define INT_SD1 0x00A00509U // 5.9 - SD1 Interrupt
#define INT_SD2 0x00A1050AU // 5.10 - SD2 Interrupt
// Upper PIE Group 6
#define INT_SPIC_RX 0x00A80609U // 6.9 - SPIC Receive Interrupt
#define INT_SPIC_TX 0x00A9060AU // 6.10 - SPIC Transmit Interrupt
// Upper PIE Group 8
#define INT_UPPA 0x00BE080FU // 8.15 - uPPA Interrupt
// Upper PIE Group 9
#define INT_USBA 0x00C6090FU // 9.15 - USBA Interrupt
// Upper PIE Group 10
#define INT_ADCC_EVT 0x00C80A09U // 10.9 - ADCC Event Interrupt
#define INT_ADCC2 0x00C90A0AU // 10.10 - ADCC Interrupt 2
#define INT_ADCC3 0x00CA0A0BU // 10.11 - ADCC Interrupt 3
#define INT_ADCC4 0x00CB0A0CU // 10.12 - ADCC Interrupt 4
#define INT_ADCD_EVT 0x00CC0A0DU // 10.13 - ADCD Event Interrupt
#define INT_ADCD2 0x00CD0A0EU // 10.14 - ADCD Interrupt 2
#define INT_ADCD3 0x00CE0A0FU // 10.15 - ADCD Interrupt 3
#define INT_ADCD4 0x00CF0A10U // 10.16 - ADCD Interrupt 4
// Upper PIE Group 12
#define INT_EMIF_ERROR 0x00D80C09U // 12.9 - EMIF Error Interrupt
#define INT_RAM_CORR_ERR 0x00D90C0AU // 12.10 - RAM Correctable Error Interrupt
#define INT_FLASH_CORR_ERR 0x00DA0C0BU // 12.11 - Flash Correctable Error Interrupt
#define INT_RAM_ACC_VIOL 0x00DB0C0CU // 12.12 - RAM Access Violation Interrupt
#define INT_SYS_PLL_SLIP 0x00DC0C0DU // 12.13 - System PLL Slip Interrupt
#define INT_AUX_PLL_SLIP 0x00DD0C0EU // 12.14 - Auxiliary PLL Slip Interrupt
#define INT_CLA_OVERFLOW 0x00DE0C0FU // 12.15 - CLA Overflow Interrupt
#define INT_CLA_UNDERFLOW 0x00DF0C10U // 12.16 - CLA Underflow Interrupt
// Other interrupts
#define INT_TIMER1 0x000D0000U // CPU Timer 1 Interrupt
#define INT_TIMER2 0x000E0000U // CPU Timer 2 Interrupt
#define INT_DATALOG 0x000F0000U // Datalogging Interrupt
#define INT_RTOS 0x00100000U // RTOS Interrupt
#define INT_EMU 0x00110000U // Emulation Interrupt
#define INT_NMI 0x00120000U // Non-Maskable Interrupt
#define INT_ILLEGAL 0x00130000U // Illegal Operation Trap
#define INT_USER1 0x00140000U // User Defined Trap 1
#define INT_USER2 0x00150000U // User Defined Trap 2
#define INT_USER3 0x00160000U // User Defined Trap 3
#define INT_USER4 0x00170000U // User Defined Trap 4
#define INT_USER5 0x00180000U // User Defined Trap 5
#define INT_USER6 0x00190000U // User Defined Trap 6
#define INT_USER7 0x001A0000U // User Defined Trap 7
#define INT_USER8 0x001B0000U // User Defined Trap 8
#define INT_USER9 0x001C0000U // User Defined Trap 9
#define INT_USER10 0x001D0000U // User Defined Trap 10
#define INT_USER11 0x001E0000U // User Defined Trap 11
#define INT_USER12 0x001F0000U // User Defined Trap 12
#endif // HW_INTS_H
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//###########################################################################
//
// FILE: hw_ipc.h
//
// TITLE: Definitions for the IPC registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_IPC_H
#define HW_IPC_H
//*****************************************************************************
//
// The following are defines for the IPC register offsets
//
//*****************************************************************************
#define IPC_O_ACK 0x0U // IPC incoming flag clear
// (acknowledge) register
#define IPC_O_STS 0x2U // IPC incoming flag status
// register
#define IPC_O_SET 0x4U // IPC remote flag set register
#define IPC_O_CLR 0x6U // IPC remote flag clear
// register
#define IPC_O_FLG 0x8U // IPC remote flag status
// register
#define IPC_O_COUNTERL 0xCU // IPC Counter Low Register
#define IPC_O_COUNTERH 0xEU // IPC Counter High Register
#ifndef CPU2
#define IPC_O_SENDCOM 0x10U // Local to Remote IPC Command
// Register
#define IPC_O_SENDADDR 0x12U // Local to Remote IPC Address
// Register
#define IPC_O_SENDDATA 0x14U // Local to Remote IPC Data
// Register
#define IPC_O_REMOTEREPLY 0x16U // Remote to Local IPC Reply
// Data Register
#define IPC_O_RECVCOM 0x18U // Remote to Local IPC Command
// Register
#define IPC_O_RECVADDR 0x1AU // Remote to Local IPC Address
// Register
#define IPC_O_RECVDATA 0x1CU // Remote to Local IPC Data
// Register
#define IPC_O_LOCALREPLY 0x1EU // Local to Remote IPC Reply
// Data Register
#else
#define IPC_O_RECVCOM 0x10U // Remote to Local IPC Command
// Register
#define IPC_O_RECVADDR 0x12U // Remote to Local IPC Address
// Register
#define IPC_O_RECVDATA 0x14U // Remote to Local IPC Data
// Register
#define IPC_O_LOCALREPLY 0x16U // Local to Remote IPC Reply
// Data Register
#define IPC_O_SENDCOM 0x18U // Local to Remote IPC Command
// Register
#define IPC_O_SENDADDR 0x1AU // Local to Remote IPC Address
// Register
#define IPC_O_SENDDATA 0x1CU // Local to Remote IPC Data
// Register
#define IPC_O_REMOTEREPLY 0x1EU // Remote to Local IPC Reply
// Data Register
#endif
#define IPC_O_BOOTSTS 0x20U // CPU2 to CPU1 IPC Boot Status
// Register
#define IPC_O_BOOTMODE 0x22U // CPU1 to CPU2 IPC Boot Mode
// Register
//*****************************************************************************
//
// The following are defines for the bit fields in the IPCACK register
//
//*****************************************************************************
#define IPC_ACK_IPC0 0x1U // Local IPC Flag 0
// Acknowledgement
#define IPC_ACK_IPC1 0x2U // Local IPC Flag 1
// Acknowledgement
#define IPC_ACK_IPC2 0x4U // Local IPC Flag 2
// Acknowledgement
#define IPC_ACK_IPC3 0x8U // Local IPC Flag 3
// Acknowledgement
#define IPC_ACK_IPC4 0x10U // Local IPC Flag 4
// Acknowledgement
#define IPC_ACK_IPC5 0x20U // Local IPC Flag 5
// Acknowledgement
#define IPC_ACK_IPC6 0x40U // Local IPC Flag 6
// Acknowledgement
#define IPC_ACK_IPC7 0x80U // Local IPC Flag 7
// Acknowledgement
#define IPC_ACK_IPC8 0x100U // Local IPC Flag 8
// Acknowledgement
#define IPC_ACK_IPC9 0x200U // Local IPC Flag 9
// Acknowledgement
#define IPC_ACK_IPC10 0x400U // Local IPC Flag 10
// Acknowledgement
#define IPC_ACK_IPC11 0x800U // Local IPC Flag 11
// Acknowledgement
#define IPC_ACK_IPC12 0x1000U // Local IPC Flag 12
// Acknowledgement
#define IPC_ACK_IPC13 0x2000U // Local IPC Flag 13
// Acknowledgement
#define IPC_ACK_IPC14 0x4000U // Local IPC Flag 14
// Acknowledgement
#define IPC_ACK_IPC15 0x8000U // Local IPC Flag 15
// Acknowledgement
#define IPC_ACK_IPC16 0x10000U // Local IPC Flag 16
// Acknowledgement
#define IPC_ACK_IPC17 0x20000U // Local IPC Flag 17
// Acknowledgement
#define IPC_ACK_IPC18 0x40000U // Local IPC Flag 18
// Acknowledgement
#define IPC_ACK_IPC19 0x80000U // Local IPC Flag 19
// Acknowledgement
#define IPC_ACK_IPC20 0x100000U // Local IPC Flag 20
// Acknowledgement
#define IPC_ACK_IPC21 0x200000U // Local IPC Flag 21
// Acknowledgement
#define IPC_ACK_IPC22 0x400000U // Local IPC Flag 22
// Acknowledgement
#define IPC_ACK_IPC23 0x800000U // Local IPC Flag 23
// Acknowledgement
#define IPC_ACK_IPC24 0x1000000U // Local IPC Flag 24
// Acknowledgement
#define IPC_ACK_IPC25 0x2000000U // Local IPC Flag 25
// Acknowledgement
#define IPC_ACK_IPC26 0x4000000U // Local IPC Flag 26
// Acknowledgement
#define IPC_ACK_IPC27 0x8000000U // Local IPC Flag 27
// Acknowledgement
#define IPC_ACK_IPC28 0x10000000U // Local IPC Flag 28
// Acknowledgement
#define IPC_ACK_IPC29 0x20000000U // Local IPC Flag 29
// Acknowledgement
#define IPC_ACK_IPC30 0x40000000U // Local IPC Flag 30
// Acknowledgement
#define IPC_ACK_IPC31 0x80000000U // Local IPC Flag 31
// Acknowledgement
//*****************************************************************************
//
// The following are defines for the bit fields in the IPCSTS register
//
//*****************************************************************************
#define IPC_STS_IPC0 0x1U // Local IPC Flag 0 Status
#define IPC_STS_IPC1 0x2U // Local IPC Flag 1 Status
#define IPC_STS_IPC2 0x4U // Local IPC Flag 2 Status
#define IPC_STS_IPC3 0x8U // Local IPC Flag 3 Status
#define IPC_STS_IPC4 0x10U // Local IPC Flag 4 Status
#define IPC_STS_IPC5 0x20U // Local IPC Flag 5 Status
#define IPC_STS_IPC6 0x40U // Local IPC Flag 6 Status
#define IPC_STS_IPC7 0x80U // Local IPC Flag 7 Status
#define IPC_STS_IPC8 0x100U // Local IPC Flag 8 Status
#define IPC_STS_IPC9 0x200U // Local IPC Flag 9 Status
#define IPC_STS_IPC10 0x400U // Local IPC Flag 10 Status
#define IPC_STS_IPC11 0x800U // Local IPC Flag 11 Status
#define IPC_STS_IPC12 0x1000U // Local IPC Flag 12 Status
#define IPC_STS_IPC13 0x2000U // Local IPC Flag 13 Status
#define IPC_STS_IPC14 0x4000U // Local IPC Flag 14 Status
#define IPC_STS_IPC15 0x8000U // Local IPC Flag 15 Status
#define IPC_STS_IPC16 0x10000U // Local IPC Flag 16 Status
#define IPC_STS_IPC17 0x20000U // Local IPC Flag 17 Status
#define IPC_STS_IPC18 0x40000U // Local IPC Flag 18 Status
#define IPC_STS_IPC19 0x80000U // Local IPC Flag 19 Status
#define IPC_STS_IPC20 0x100000U // Local IPC Flag 20 Status
#define IPC_STS_IPC21 0x200000U // Local IPC Flag 21 Status
#define IPC_STS_IPC22 0x400000U // Local IPC Flag 22 Status
#define IPC_STS_IPC23 0x800000U // Local IPC Flag 23 Status
#define IPC_STS_IPC24 0x1000000U // Local IPC Flag 24 Status
#define IPC_STS_IPC25 0x2000000U // Local IPC Flag 25 Status
#define IPC_STS_IPC26 0x4000000U // Local IPC Flag 26 Status
#define IPC_STS_IPC27 0x8000000U // Local IPC Flag 27 Status
#define IPC_STS_IPC28 0x10000000U // Local IPC Flag 28 Status
#define IPC_STS_IPC29 0x20000000U // Local IPC Flag 29 Status
#define IPC_STS_IPC30 0x40000000U // Local IPC Flag 30 Status
#define IPC_STS_IPC31 0x80000000U // Local IPC Flag 31 Status
//*****************************************************************************
//
// The following are defines for the bit fields in the IPCSET register
//
//*****************************************************************************
#define IPC_SET_IPC0 0x1U // Set Remote IPC0 Flag
#define IPC_SET_IPC1 0x2U // Set Remote IPC1 Flag
#define IPC_SET_IPC2 0x4U // Set Remote IPC2 Flag
#define IPC_SET_IPC3 0x8U // Set Remote IPC3 Flag
#define IPC_SET_IPC4 0x10U // Set Remote IPC4 Flag
#define IPC_SET_IPC5 0x20U // Set Remote IPC5 Flag
#define IPC_SET_IPC6 0x40U // Set Remote IPC6 Flag
#define IPC_SET_IPC7 0x80U // Set Remote IPC7 Flag
#define IPC_SET_IPC8 0x100U // Set Remote IPC8 Flag
#define IPC_SET_IPC9 0x200U // Set Remote IPC9 Flag
#define IPC_SET_IPC10 0x400U // Set Remote IPC10 Flag
#define IPC_SET_IPC11 0x800U // Set Remote IPC11 Flag
#define IPC_SET_IPC12 0x1000U // Set Remote IPC12 Flag
#define IPC_SET_IPC13 0x2000U // Set Remote IPC13 Flag
#define IPC_SET_IPC14 0x4000U // Set Remote IPC14 Flag
#define IPC_SET_IPC15 0x8000U // Set Remote IPC15 Flag
#define IPC_SET_IPC16 0x10000U // Set Remote IPC16 Flag
#define IPC_SET_IPC17 0x20000U // Set Remote IPC17 Flag
#define IPC_SET_IPC18 0x40000U // Set Remote IPC18 Flag
#define IPC_SET_IPC19 0x80000U // Set Remote IPC19 Flag
#define IPC_SET_IPC20 0x100000U // Set Remote IPC20 Flag
#define IPC_SET_IPC21 0x200000U // Set Remote IPC21 Flag
#define IPC_SET_IPC22 0x400000U // Set Remote IPC22 Flag
#define IPC_SET_IPC23 0x800000U // Set Remote IPC23 Flag
#define IPC_SET_IPC24 0x1000000U // Set Remote IPC24 Flag
#define IPC_SET_IPC25 0x2000000U // Set Remote IPC25 Flag
#define IPC_SET_IPC26 0x4000000U // Set Remote IPC26 Flag
#define IPC_SET_IPC27 0x8000000U // Set Remote IPC27 Flag
#define IPC_SET_IPC28 0x10000000U // Set Remote IPC28 Flag
#define IPC_SET_IPC29 0x20000000U // Set Remote IPC29 Flag
#define IPC_SET_IPC30 0x40000000U // Set Remote IPC30 Flag
#define IPC_SET_IPC31 0x80000000U // Set Remote IPC31 Flag
//*****************************************************************************
//
// The following are defines for the bit fields in the IPCCLR register
//
//*****************************************************************************
#define IPC_CLR_IPC0 0x1U // Clear Remote IPC0 Flag
#define IPC_CLR_IPC1 0x2U // Clear Remote IPC1 Flag
#define IPC_CLR_IPC2 0x4U // Clear Remote IPC2 Flag
#define IPC_CLR_IPC3 0x8U // Clear Remote IPC3 Flag
#define IPC_CLR_IPC4 0x10U // Clear Remote IPC4 Flag
#define IPC_CLR_IPC5 0x20U // Clear Remote IPC5 Flag
#define IPC_CLR_IPC6 0x40U // Clear Remote IPC6 Flag
#define IPC_CLR_IPC7 0x80U // Clear Remote IPC7 Flag
#define IPC_CLR_IPC8 0x100U // Clear Remote IPC8 Flag
#define IPC_CLR_IPC9 0x200U // Clear Remote IPC9 Flag
#define IPC_CLR_IPC10 0x400U // Clear Remote IPC10 Flag
#define IPC_CLR_IPC11 0x800U // Clear Remote IPC11 Flag
#define IPC_CLR_IPC12 0x1000U // Clear Remote IPC12 Flag
#define IPC_CLR_IPC13 0x2000U // Clear Remote IPC13 Flag
#define IPC_CLR_IPC14 0x4000U // Clear Remote IPC14 Flag
#define IPC_CLR_IPC15 0x8000U // Clear Remote IPC15 Flag
#define IPC_CLR_IPC16 0x10000U // Clear Remote IPC16 Flag
#define IPC_CLR_IPC17 0x20000U // Clear Remote IPC17 Flag
#define IPC_CLR_IPC18 0x40000U // Clear Remote IPC18 Flag
#define IPC_CLR_IPC19 0x80000U // Clear Remote IPC19 Flag
#define IPC_CLR_IPC20 0x100000U // Clear Remote IPC20 Flag
#define IPC_CLR_IPC21 0x200000U // Clear Remote IPC21 Flag
#define IPC_CLR_IPC22 0x400000U // Clear Remote IPC22 Flag
#define IPC_CLR_IPC23 0x800000U // Clear Remote IPC23 Flag
#define IPC_CLR_IPC24 0x1000000U // Clear Remote IPC24 Flag
#define IPC_CLR_IPC25 0x2000000U // Clear Remote IPC25 Flag
#define IPC_CLR_IPC26 0x4000000U // Clear Remote IPC26 Flag
#define IPC_CLR_IPC27 0x8000000U // Clear Remote IPC27 Flag
#define IPC_CLR_IPC28 0x10000000U // Clear Remote IPC28 Flag
#define IPC_CLR_IPC29 0x20000000U // Clear Remote IPC29 Flag
#define IPC_CLR_IPC30 0x40000000U // Clear Remote IPC30 Flag
#define IPC_CLR_IPC31 0x80000000U // Clear Remote IPC31 Flag
//*****************************************************************************
//
// The following are defines for the bit fields in the IPCFLG register
//
//*****************************************************************************
#define IPC_FLG_IPC0 0x1U // Remote IPC0 Flag Status
#define IPC_FLG_IPC1 0x2U // Remote IPC1 Flag Status
#define IPC_FLG_IPC2 0x4U // Remote IPC2 Flag Status
#define IPC_FLG_IPC3 0x8U // Remote IPC3 Flag Status
#define IPC_FLG_IPC4 0x10U // Remote IPC4 Flag Status
#define IPC_FLG_IPC5 0x20U // Remote IPC5 Flag Status
#define IPC_FLG_IPC6 0x40U // Remote IPC6 Flag Status
#define IPC_FLG_IPC7 0x80U // Remote IPC7 Flag Status
#define IPC_FLG_IPC8 0x100U // Remote IPC8 Flag Status
#define IPC_FLG_IPC9 0x200U // Remote IPC9 Flag Status
#define IPC_FLG_IPC10 0x400U // Remote IPC10 Flag Status
#define IPC_FLG_IPC11 0x800U // Remote IPC11 Flag Status
#define IPC_FLG_IPC12 0x1000U // Remote IPC12 Flag Status
#define IPC_FLG_IPC13 0x2000U // Remote IPC13 Flag Status
#define IPC_FLG_IPC14 0x4000U // Remote IPC14 Flag Status
#define IPC_FLG_IPC15 0x8000U // Remote IPC15 Flag Status
#define IPC_FLG_IPC16 0x10000U // Remote IPC16 Flag Status
#define IPC_FLG_IPC17 0x20000U // Remote IPC17 Flag Status
#define IPC_FLG_IPC18 0x40000U // Remote IPC18 Flag Status
#define IPC_FLG_IPC19 0x80000U // Remote IPC19 Flag Status
#define IPC_FLG_IPC20 0x100000U // Remote IPC20 Flag Status
#define IPC_FLG_IPC21 0x200000U // Remote IPC21 Flag Status
#define IPC_FLG_IPC22 0x400000U // Remote IPC22 Flag Status
#define IPC_FLG_IPC23 0x800000U // Remote IPC23 Flag Status
#define IPC_FLG_IPC24 0x1000000U // Remote IPC24 Flag Status
#define IPC_FLG_IPC25 0x2000000U // Remote IPC25 Flag Status
#define IPC_FLG_IPC26 0x4000000U // Remote IPC26 Flag Status
#define IPC_FLG_IPC27 0x8000000U // Remote IPC27 Flag Status
#define IPC_FLG_IPC28 0x10000000U // Remote IPC28 Flag Status
#define IPC_FLG_IPC29 0x20000000U // Remote IPC29 Flag Status
#define IPC_FLG_IPC30 0x40000000U // Remote IPC30 Flag Status
#define IPC_FLG_IPC31 0x80000000U // Remote IPC31 Flag Status
#endif
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//###########################################################################
//
// FILE: hw_mcbsp.h
//
// TITLE: Definitions for the MCBSP registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_MCBSP_H
#define HW_MCBSP_H
//*************************************************************************************************
//
// The following are defines for the MCBSP register offsets
//
//*************************************************************************************************
#define MCBSP_O_DRR2 0x0U // Data receive register bits 31-16
#define MCBSP_O_DRR1 0x1U // Data receive register bits 15-0
#define MCBSP_O_DXR2 0x2U // Data transmit register bits 31-16
#define MCBSP_O_DXR1 0x3U // Data transmit register bits 15-0
#define MCBSP_O_SPCR2 0x4U // Serial port control register 2
#define MCBSP_O_SPCR1 0x5U // Serial port control register 1
#define MCBSP_O_RCR2 0x6U // Receive Control register 2
#define MCBSP_O_RCR1 0x7U // Receive Control register 1
#define MCBSP_O_XCR2 0x8U // Transmit Control register 2
#define MCBSP_O_XCR1 0x9U // Transmit Control register 1
#define MCBSP_O_SRGR2 0xAU // Sample rate generator register 2
#define MCBSP_O_SRGR1 0xBU // Sample rate generator register 1
#define MCBSP_O_MCR2 0xCU // Multi-channel control register 2
#define MCBSP_O_MCR1 0xDU // Multi-channel control register 1
#define MCBSP_O_RCERA 0xEU // Receive channel enable partition A
#define MCBSP_O_RCERB 0xFU // Receive channel enable partition B
#define MCBSP_O_XCERA 0x10U // Transmit channel enable partition A
#define MCBSP_O_XCERB 0x11U // Transmit channel enable partition B
#define MCBSP_O_PCR 0x12U // Pin Control register
#define MCBSP_O_RCERC 0x13U // Receive channel enable partition C
#define MCBSP_O_RCERD 0x14U // Receive channel enable partition D
#define MCBSP_O_XCERC 0x15U // Transmit channel enable partition C
#define MCBSP_O_XCERD 0x16U // Transmit channel enable partition D
#define MCBSP_O_RCERE 0x17U // Receive channel enable partition E
#define MCBSP_O_RCERF 0x18U // Receive channel enable partition F
#define MCBSP_O_XCERE 0x19U // Transmit channel enable partition E
#define MCBSP_O_XCERF 0x1AU // Transmit channel enable partition F
#define MCBSP_O_RCERG 0x1BU // Receive channel enable partition G
#define MCBSP_O_RCERH 0x1CU // Receive channel enable partition H
#define MCBSP_O_XCERG 0x1DU // Transmit channel enable partition G
#define MCBSP_O_XCERH 0x1EU // Transmit channel enable partition H
#define MCBSP_O_MFFINT 0x23U // Interrupt enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the DRR2 register
//
//*************************************************************************************************
#define MCBSP_DRR2_HWLB_S 0U
#define MCBSP_DRR2_HWLB_M 0xFFU // High word low byte
#define MCBSP_DRR2_HWHB_S 8U
#define MCBSP_DRR2_HWHB_M 0xFF00U // High word high byte
//*************************************************************************************************
//
// The following are defines for the bit fields in the DRR1 register
//
//*************************************************************************************************
#define MCBSP_DRR1_LWLB_S 0U
#define MCBSP_DRR1_LWLB_M 0xFFU // Low word low byte
#define MCBSP_DRR1_LWHB_S 8U
#define MCBSP_DRR1_LWHB_M 0xFF00U // Low word high byte
//*************************************************************************************************
//
// The following are defines for the bit fields in the DXR2 register
//
//*************************************************************************************************
#define MCBSP_DXR2_HWLB_S 0U
#define MCBSP_DXR2_HWLB_M 0xFFU // High word low byte
#define MCBSP_DXR2_HWHB_S 8U
#define MCBSP_DXR2_HWHB_M 0xFF00U // High word high byte
//*************************************************************************************************
//
// The following are defines for the bit fields in the DXR1 register
//
//*************************************************************************************************
#define MCBSP_DXR1_LWLB_S 0U
#define MCBSP_DXR1_LWLB_M 0xFFU // Low word low byte
#define MCBSP_DXR1_LWHB_S 8U
#define MCBSP_DXR1_LWHB_M 0xFF00U // Low word high byte
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPCR2 register
//
//*************************************************************************************************
#define MCBSP_SPCR2_XRST 0x1U // Transmitter reset
#define MCBSP_SPCR2_XRDY 0x2U // Transmitter ready
#define MCBSP_SPCR2_XEMPTY 0x4U // Transmitter empty
#define MCBSP_SPCR2_XSYNCERR 0x8U // Transmit sync error INT flag
#define MCBSP_SPCR2_XINTM_S 4U
#define MCBSP_SPCR2_XINTM_M 0x30U // Transmit Interupt mode bits
#define MCBSP_SPCR2_GRST 0x40U // Sample rate generator reset
#define MCBSP_SPCR2_FRST 0x80U // Frame sync logic reset
#define MCBSP_SPCR2_SOFT 0x100U // SOFT bit
#define MCBSP_SPCR2_FREE 0x200U // FREE bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPCR1 register
//
//*************************************************************************************************
#define MCBSP_SPCR1_RRST 0x1U // Receiver reset
#define MCBSP_SPCR1_RRDY 0x2U // Receiver ready
#define MCBSP_SPCR1_RFULL 0x4U // Receiver full
#define MCBSP_SPCR1_RSYNCERR 0x8U // Receive sync error INT flag
#define MCBSP_SPCR1_RINTM_S 4U
#define MCBSP_SPCR1_RINTM_M 0x30U // Receive Interupt mode bits
#define MCBSP_SPCR1_DXENA 0x80U // DX delay enable
#define MCBSP_SPCR1_CLKSTP_S 11U
#define MCBSP_SPCR1_CLKSTP_M 0x1800U // Clock stop mode
#define MCBSP_SPCR1_RJUST_S 13U
#define MCBSP_SPCR1_RJUST_M 0x6000U // Rx sign extension and justification mode
#define MCBSP_SPCR1_DLB 0x8000U // Digital loopback
//*************************************************************************************************
//
// The following are defines for the bit fields in the RCR2 register
//
//*************************************************************************************************
#define MCBSP_RCR2_RDATDLY_S 0U
#define MCBSP_RCR2_RDATDLY_M 0x3U // Receive data delay
#define MCBSP_RCR2_RFIG 0x4U // Receive frame sync ignore
#define MCBSP_RCR2_RCOMPAND_S 3U
#define MCBSP_RCR2_RCOMPAND_M 0x18U // Receive Companding Mode selects
#define MCBSP_RCR2_RWDLEN2_S 5U
#define MCBSP_RCR2_RWDLEN2_M 0xE0U // Receive word length 2
#define MCBSP_RCR2_RFRLEN2_S 8U
#define MCBSP_RCR2_RFRLEN2_M 0x7F00U // Receive Frame length 2
#define MCBSP_RCR2_RPHASE 0x8000U // Receive Phase
//*************************************************************************************************
//
// The following are defines for the bit fields in the RCR1 register
//
//*************************************************************************************************
#define MCBSP_RCR1_RWDLEN1_S 5U
#define MCBSP_RCR1_RWDLEN1_M 0xE0U // Receive word length 1
#define MCBSP_RCR1_RFRLEN1_S 8U
#define MCBSP_RCR1_RFRLEN1_M 0x7F00U // Receive Frame length 1
//*************************************************************************************************
//
// The following are defines for the bit fields in the XCR2 register
//
//*************************************************************************************************
#define MCBSP_XCR2_XDATDLY_S 0U
#define MCBSP_XCR2_XDATDLY_M 0x3U // Transmit data delay
#define MCBSP_XCR2_XFIG 0x4U // Transmit frame sync ignore
#define MCBSP_XCR2_XCOMPAND_S 3U
#define MCBSP_XCR2_XCOMPAND_M 0x18U // Transmit Companding Mode selects
#define MCBSP_XCR2_XWDLEN2_S 5U
#define MCBSP_XCR2_XWDLEN2_M 0xE0U // Transmit word length 2
#define MCBSP_XCR2_XFRLEN2_S 8U
#define MCBSP_XCR2_XFRLEN2_M 0x7F00U // Transmit Frame length 2
#define MCBSP_XCR2_XPHASE 0x8000U // Transmit Phase
//*************************************************************************************************
//
// The following are defines for the bit fields in the XCR1 register
//
//*************************************************************************************************
#define MCBSP_XCR1_XWDLEN1_S 5U
#define MCBSP_XCR1_XWDLEN1_M 0xE0U // Transmit word length 1
#define MCBSP_XCR1_XFRLEN1_S 8U
#define MCBSP_XCR1_XFRLEN1_M 0x7F00U // Transmit Frame length 1
//*************************************************************************************************
//
// The following are defines for the bit fields in the SRGR2 register
//
//*************************************************************************************************
#define MCBSP_SRGR2_FPER_S 0U
#define MCBSP_SRGR2_FPER_M 0xFFFU // Frame-sync period
#define MCBSP_SRGR2_FSGM 0x1000U // Frame sync generator mode
#define MCBSP_SRGR2_CLKSM 0x2000U // Sample rate generator mode
#define MCBSP_SRGR2_GSYNC 0x8000U // CLKG sync
//*************************************************************************************************
//
// The following are defines for the bit fields in the SRGR1 register
//
//*************************************************************************************************
#define MCBSP_SRGR1_CLKGDV_S 0U
#define MCBSP_SRGR1_CLKGDV_M 0xFFU // CLKG divider
#define MCBSP_SRGR1_FWID_S 8U
#define MCBSP_SRGR1_FWID_M 0xFF00U // Frame width
//*************************************************************************************************
//
// The following are defines for the bit fields in the MCR2 register
//
//*************************************************************************************************
#define MCBSP_MCR2_XMCM_S 0U
#define MCBSP_MCR2_XMCM_M 0x3U // Transmit data delay
#define MCBSP_MCR2_XCBLK_S 2U
#define MCBSP_MCR2_XCBLK_M 0x1CU // Transmit frame sync ignore
#define MCBSP_MCR2_XPABLK_S 5U
#define MCBSP_MCR2_XPABLK_M 0x60U // Transmit Companding Mode selects
#define MCBSP_MCR2_XPBBLK_S 7U
#define MCBSP_MCR2_XPBBLK_M 0x180U // Transmit word length 2
#define MCBSP_MCR2_XMCME 0x200U // Transmit Frame length 2
//*************************************************************************************************
//
// The following are defines for the bit fields in the MCR1 register
//
//*************************************************************************************************
#define MCBSP_MCR1_RMCM 0x1U // Receive multichannel mode
#define MCBSP_MCR1_RCBLK_S 2U
#define MCBSP_MCR1_RCBLK_M 0x1CU // eceive current block
#define MCBSP_MCR1_RPABLK_S 5U
#define MCBSP_MCR1_RPABLK_M 0x60U // Receive partition A Block
#define MCBSP_MCR1_RPBBLK_S 7U
#define MCBSP_MCR1_RPBBLK_M 0x180U // Receive partition B Block
#define MCBSP_MCR1_RMCME 0x200U // Receive multi-channel enhance mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the PCR register
//
//*************************************************************************************************
#define MCBSP_PCR_CLKRP 0x1U // Receive Clock polarity
#define MCBSP_PCR_CLKXP 0x2U // Transmit clock polarity
#define MCBSP_PCR_FSRP 0x4U // Receive Frame synchronization polarity
#define MCBSP_PCR_FSXP 0x8U // Transmit Frame synchronization polarity
#define MCBSP_PCR_SCLKME 0x80U // Sample clock mode selection
#define MCBSP_PCR_CLKRM 0x100U // Receiver Clock Mode
#define MCBSP_PCR_CLKXM 0x200U // Transmit Clock Mode.
#define MCBSP_PCR_FSRM 0x400U // Receive Frame Synchronization Mode
#define MCBSP_PCR_FSXM 0x800U // Transmit Frame Synchronization Mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the MFFINT register
//
//*************************************************************************************************
#define MCBSP_MFFINT_XINT 0x1U // Enable for Receive Interrupt
#define MCBSP_MFFINT_RINT 0x4U // Enable for transmit Interrupt
#endif
28379d_P_SFRA/device/driverlib/inc/hw_memcfg.h
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//###########################################################################
//
// FILE: hw_memcfg.h
//
// TITLE: Definitions for the MEMCFG registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_MEMCFG_H
#define HW_MEMCFG_H
//*************************************************************************************************
//
// The following are defines for the MEMCFG register offsets
//
//*************************************************************************************************
#define MEMCFG_O_DXLOCK 0x0U // Dedicated RAM Config Lock Register
#define MEMCFG_O_DXCOMMIT 0x2U // Dedicated RAM Config Lock Commit Register
#define MEMCFG_O_DXACCPROT0 0x8U // Dedicated RAM Config Register
#define MEMCFG_O_DXTEST 0x10U // Dedicated RAM TEST Register
#define MEMCFG_O_DXINIT 0x12U // Dedicated RAM Init Register
#define MEMCFG_O_DXINITDONE 0x14U // Dedicated RAM InitDone Status Register
#define MEMCFG_O_LSXLOCK 0x20U // Local Shared RAM Config Lock Register
#define MEMCFG_O_LSXCOMMIT 0x22U // Local Shared RAM Config Lock Commit Register
#define MEMCFG_O_LSXMSEL 0x24U // Local Shared RAM Master Sel Register
#define MEMCFG_O_LSXCLAPGM 0x26U // Local Shared RAM Prog/Exe control Register
#define MEMCFG_O_LSXACCPROT0 0x28U // Local Shared RAM Config Register 0
#define MEMCFG_O_LSXACCPROT1 0x2AU // Local Shared RAM Config Register 1
#define MEMCFG_O_LSXTEST 0x30U // Local Shared RAM TEST Register
#define MEMCFG_O_LSXINIT 0x32U // Local Shared RAM Init Register
#define MEMCFG_O_LSXINITDONE 0x34U // Local Shared RAM InitDone Status Register
#define MEMCFG_O_GSXLOCK 0x40U // Global Shared RAM Config Lock Register
#define MEMCFG_O_GSXCOMMIT 0x42U // Global Shared RAM Config Lock Commit Register
#define MEMCFG_O_GSXMSEL 0x44U // Global Shared RAM Master Sel Register
#define MEMCFG_O_GSXACCPROT0 0x48U // Global Shared RAM Config Register 0
#define MEMCFG_O_GSXACCPROT1 0x4AU // Global Shared RAM Config Register 1
#define MEMCFG_O_GSXACCPROT2 0x4CU // Global Shared RAM Config Register 2
#define MEMCFG_O_GSXACCPROT3 0x4EU // Global Shared RAM Config Register 3
#define MEMCFG_O_GSXTEST 0x50U // Global Shared RAM TEST Register
#define MEMCFG_O_GSXINIT 0x52U // Global Shared RAM Init Register
#define MEMCFG_O_GSXINITDONE 0x54U // Global Shared RAM InitDone Status Register
#define MEMCFG_O_MSGXTEST 0x70U // Message RAM TEST Register
#define MEMCFG_O_MSGXINIT 0x72U // Message RAM Init Register
#define MEMCFG_O_MSGXINITDONE 0x74U // Message RAM InitDone Status Register
#define MEMCFG_O_EMIF1LOCK 0x0U // EMIF1 Config Lock Register
#define MEMCFG_O_EMIF1COMMIT 0x2U // EMIF1 Config Lock Commit Register
#define MEMCFG_O_EMIF1MSEL 0x4U // EMIF1 Master Sel Register
#define MEMCFG_O_EMIF1ACCPROT0 0x8U // EMIF1 Config Register 0
#define MEMCFG_O_EMIF2LOCK 0x0U // EMIF2 Config Lock Register
#define MEMCFG_O_EMIF2COMMIT 0x2U // EMIF2 Config Lock Commit Register
#define MEMCFG_O_EMIF2ACCPROT0 0x8U // EMIF2 Config Register 0
#define MEMCFG_O_NMAVFLG 0x0U // Non-Master Access Violation Flag Register
#define MEMCFG_O_NMAVSET 0x2U // Non-Master Access Violation Flag Set Register
#define MEMCFG_O_NMAVCLR 0x4U // Non-Master Access Violation Flag Clear Register
#define MEMCFG_O_NMAVINTEN 0x6U // Non-Master Access Violation Interrupt Enable Register
#define MEMCFG_O_NMCPURDAVADDR 0x8U // Non-Master CPU Read Access Violation Address
#define MEMCFG_O_NMCPUWRAVADDR 0xAU // Non-Master CPU Write Access Violation Address
#define MEMCFG_O_NMCPUFAVADDR 0xCU // Non-Master CPU Fetch Access Violation Address
#define MEMCFG_O_NMDMAWRAVADDR 0xEU // Non-Master DMA Write Access Violation Address
#define MEMCFG_O_NMCLA1RDAVADDR 0x10U // Non-Master CLA1 Read Access Violation Address
#define MEMCFG_O_NMCLA1WRAVADDR 0x12U // Non-Master CLA1 Write Access Violation Address
#define MEMCFG_O_NMCLA1FAVADDR 0x14U // Non-Master CLA1 Fetch Access Violation Address
#define MEMCFG_O_MAVFLG 0x20U // Master Access Violation Flag Register
#define MEMCFG_O_MAVSET 0x22U // Master Access Violation Flag Set Register
#define MEMCFG_O_MAVCLR 0x24U // Master Access Violation Flag Clear Register
#define MEMCFG_O_MAVINTEN 0x26U // Master Access Violation Interrupt Enable Register
#define MEMCFG_O_MCPUFAVADDR 0x28U // Master CPU Fetch Access Violation Address
#define MEMCFG_O_MCPUWRAVADDR 0x2AU // Master CPU Write Access Violation Address
#define MEMCFG_O_MDMAWRAVADDR 0x2CU // Master DMA Write Access Violation Address
#define MEMCFG_O_UCERRFLG 0x0U // Uncorrectable Error Flag Register
#define MEMCFG_O_UCERRSET 0x2U // Uncorrectable Error Flag Set Register
#define MEMCFG_O_UCERRCLR 0x4U // Uncorrectable Error Flag Clear Register
#define MEMCFG_O_UCCPUREADDR 0x6U // Uncorrectable CPU Read Error Address
#define MEMCFG_O_UCDMAREADDR 0x8U // Uncorrectable DMA Read Error Address
#define MEMCFG_O_UCCLA1READDR 0xAU // Uncorrectable CLA1 Read Error Address
#define MEMCFG_O_CERRFLG 0x20U // Correctable Error Flag Register
#define MEMCFG_O_CERRSET 0x22U // Correctable Error Flag Set Register
#define MEMCFG_O_CERRCLR 0x24U // Correctable Error Flag Clear Register
#define MEMCFG_O_CCPUREADDR 0x26U // Correctable CPU Read Error Address
#define MEMCFG_O_CERRCNT 0x2EU // Correctable Error Count Register
#define MEMCFG_O_CERRTHRES 0x30U // Correctable Error Threshold Value Register
#define MEMCFG_O_CEINTFLG 0x32U // Correctable Error Interrupt Flag Status Register
#define MEMCFG_O_CEINTCLR 0x34U // Correctable Error Interrupt Flag Clear Register
#define MEMCFG_O_CEINTSET 0x36U // Correctable Error Interrupt Flag Set Register
#define MEMCFG_O_CEINTEN 0x38U // Correctable Error Interrupt Enable Register
#define MEMCFG_O_ROMWAITSTATE 0x0U // ROM Wait State Configuration Register
#define MEMCFG_O_ROMPREFETCH 0x0U // ROM Prefetch Configuration Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the DxLOCK register
//
//*************************************************************************************************
#define MEMCFG_DXLOCK_LOCK_D0 0x4U // D0 RAM access protection and master select fields lock
// bit
#define MEMCFG_DXLOCK_LOCK_D1 0x8U // D1 RAM access protection and master select fields lock
// bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the DxCOMMIT register
//
//*************************************************************************************************
#define MEMCFG_DXCOMMIT_COMMIT_D0 0x4U // D0 RAM access protection and master select permanent
// lock
#define MEMCFG_DXCOMMIT_COMMIT_D1 0x8U // D1 RAM access protection and master select permanent
// lock
//*************************************************************************************************
//
// The following are defines for the bit fields in the DxACCPROT0 register
//
//*************************************************************************************************
#define MEMCFG_DXACCPROT0_FETCHPROT_D0 0x10000U // Fetch Protection For D0 RAM
#define MEMCFG_DXACCPROT0_CPUWRPROT_D0 0x20000U // CPU WR Protection For D0 RAM
#define MEMCFG_DXACCPROT0_FETCHPROT_D1 0x1000000U // Fetch Protection For D1 RAM
#define MEMCFG_DXACCPROT0_CPUWRPROT_D1 0x2000000U // CPU WR Protection For D1 RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the DxTEST register
//
//*************************************************************************************************
#define MEMCFG_DXTEST_TEST_M0_S 0U
#define MEMCFG_DXTEST_TEST_M0_M 0x3U // Selects the different modes for M0 RAM
#define MEMCFG_DXTEST_TEST_M1_S 2U
#define MEMCFG_DXTEST_TEST_M1_M 0xCU // Selects the different modes for M1 RAM
#define MEMCFG_DXTEST_TEST_D0_S 4U
#define MEMCFG_DXTEST_TEST_D0_M 0x30U // Selects the different modes for D0 RAM
#define MEMCFG_DXTEST_TEST_D1_S 6U
#define MEMCFG_DXTEST_TEST_D1_M 0xC0U // Selects the different modes for D1 RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the DxINIT register
//
//*************************************************************************************************
#define MEMCFG_DXINIT_INIT_M0 0x1U // RAM Initialization control for M0 RAM.
#define MEMCFG_DXINIT_INIT_M1 0x2U // RAM Initialization control for M1 RAM.
#define MEMCFG_DXINIT_INIT_D0 0x4U // RAM Initialization control for D0 RAM.
#define MEMCFG_DXINIT_INIT_D1 0x8U // RAM Initialization control for D1 RAM.
//*************************************************************************************************
//
// The following are defines for the bit fields in the DxINITDONE register
//
//*************************************************************************************************
#define MEMCFG_DXINITDONE_INITDONE_M0 0x1U // RAM Initialization status for M0 RAM.
#define MEMCFG_DXINITDONE_INITDONE_M1 0x2U // RAM Initialization status for M1 RAM.
#define MEMCFG_DXINITDONE_INITDONE_D0 0x4U // RAM Initialization status for D0 RAM.
#define MEMCFG_DXINITDONE_INITDONE_D1 0x8U // RAM Initialization status for D1 RAM.
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxLOCK register
//
//*************************************************************************************************
#define MEMCFG_LSXLOCK_LOCK_LS0 0x1U // LS0 RAM access protection and master select fields
// lock bit
#define MEMCFG_LSXLOCK_LOCK_LS1 0x2U // LS1 RAM access protection and master select fields
// lock bit
#define MEMCFG_LSXLOCK_LOCK_LS2 0x4U // LS2 RAM access protection and master select fields
// lock bit
#define MEMCFG_LSXLOCK_LOCK_LS3 0x8U // LS3 RAM access protection and master select fields
// lock bit
#define MEMCFG_LSXLOCK_LOCK_LS4 0x10U // LS4 RAM access protection and master select fields
// lock bit
#define MEMCFG_LSXLOCK_LOCK_LS5 0x20U // LS5 RAM access protection and master select fields
// lock bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxCOMMIT register
//
//*************************************************************************************************
#define MEMCFG_LSXCOMMIT_COMMIT_LS0 0x1U // LS0 RAM access protection and master select
// permanent lock
#define MEMCFG_LSXCOMMIT_COMMIT_LS1 0x2U // LS1 RAM access protection and master select
// permanent lock
#define MEMCFG_LSXCOMMIT_COMMIT_LS2 0x4U // LS2 RAM access protection and master select
// permanent lock
#define MEMCFG_LSXCOMMIT_COMMIT_LS3 0x8U // LS3 RAM access protection and master select
// permanent lock
#define MEMCFG_LSXCOMMIT_COMMIT_LS4 0x10U // LS4 RAM access protection and master select
// permanent lock
#define MEMCFG_LSXCOMMIT_COMMIT_LS5 0x20U // LS5 RAM access protection and master select
// permanent lock
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxMSEL register
//
//*************************************************************************************************
#define MEMCFG_LSXMSEL_MSEL_LS0_S 0U
#define MEMCFG_LSXMSEL_MSEL_LS0_M 0x3U // Master Select for LS0 RAM
#define MEMCFG_LSXMSEL_MSEL_LS1_S 2U
#define MEMCFG_LSXMSEL_MSEL_LS1_M 0xCU // Master Select for LS1 RAM
#define MEMCFG_LSXMSEL_MSEL_LS2_S 4U
#define MEMCFG_LSXMSEL_MSEL_LS2_M 0x30U // Master Select for LS2 RAM
#define MEMCFG_LSXMSEL_MSEL_LS3_S 6U
#define MEMCFG_LSXMSEL_MSEL_LS3_M 0xC0U // Master Select for LS3 RAM
#define MEMCFG_LSXMSEL_MSEL_LS4_S 8U
#define MEMCFG_LSXMSEL_MSEL_LS4_M 0x300U // Master Select for LS4 RAM
#define MEMCFG_LSXMSEL_MSEL_LS5_S 10U
#define MEMCFG_LSXMSEL_MSEL_LS5_M 0xC00U // Master Select for LS5 RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxCLAPGM register
//
//*************************************************************************************************
#define MEMCFG_LSXCLAPGM_CLAPGM_LS0 0x1U // Selects LS0 RAM as program vs data memory for CLA
#define MEMCFG_LSXCLAPGM_CLAPGM_LS1 0x2U // Selects LS1 RAM as program vs data memory for CLA
#define MEMCFG_LSXCLAPGM_CLAPGM_LS2 0x4U // Selects LS2 RAM as program vs data memory for CLA
#define MEMCFG_LSXCLAPGM_CLAPGM_LS3 0x8U // Selects LS3 RAM as program vs data memory for CLA
#define MEMCFG_LSXCLAPGM_CLAPGM_LS4 0x10U // Selects LS4 RAM as program vs data memory for CLA
#define MEMCFG_LSXCLAPGM_CLAPGM_LS5 0x20U // Selects LS5 RAM as program vs data memory for CLA
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxACCPROT0 register
//
//*************************************************************************************************
#define MEMCFG_LSXACCPROT0_FETCHPROT_LS0 0x1U // Fetch Protection For LS0 RAM
#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS0 0x2U // CPU WR Protection For LS0 RAM
#define MEMCFG_LSXACCPROT0_FETCHPROT_LS1 0x100U // Fetch Protection For LS1 RAM
#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS1 0x200U // CPU WR Protection For LS1 RAM
#define MEMCFG_LSXACCPROT0_FETCHPROT_LS2 0x10000U // Fetch Protection For LS2 RAM
#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS2 0x20000U // CPU WR Protection For LS2 RAM
#define MEMCFG_LSXACCPROT0_FETCHPROT_LS3 0x1000000U // Fetch Protection For LS3 RAM
#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS3 0x2000000U // CPU WR Protection For LS3 RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxACCPROT1 register
//
//*************************************************************************************************
#define MEMCFG_LSXACCPROT1_FETCHPROT_LS4 0x1U // Fetch Protection For LS4 RAM
#define MEMCFG_LSXACCPROT1_CPUWRPROT_LS4 0x2U // CPU WR Protection For LS4 RAM
#define MEMCFG_LSXACCPROT1_FETCHPROT_LS5 0x100U // Fetch Protection For LS5 RAM
#define MEMCFG_LSXACCPROT1_CPUWRPROT_LS5 0x200U // CPU WR Protection For LS5 RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxTEST register
//
//*************************************************************************************************
#define MEMCFG_LSXTEST_TEST_LS0_S 0U
#define MEMCFG_LSXTEST_TEST_LS0_M 0x3U // Selects the different modes for LS0 RAM
#define MEMCFG_LSXTEST_TEST_LS1_S 2U
#define MEMCFG_LSXTEST_TEST_LS1_M 0xCU // Selects the different modes for LS1 RAM
#define MEMCFG_LSXTEST_TEST_LS2_S 4U
#define MEMCFG_LSXTEST_TEST_LS2_M 0x30U // Selects the different modes for LS2 RAM
#define MEMCFG_LSXTEST_TEST_LS3_S 6U
#define MEMCFG_LSXTEST_TEST_LS3_M 0xC0U // Selects the different modes for LS3 RAM
#define MEMCFG_LSXTEST_TEST_LS4_S 8U
#define MEMCFG_LSXTEST_TEST_LS4_M 0x300U // Selects the different modes for LS4 RAM
#define MEMCFG_LSXTEST_TEST_LS5_S 10U
#define MEMCFG_LSXTEST_TEST_LS5_M 0xC00U // Selects the different modes for LS5 RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxINIT register
//
//*************************************************************************************************
#define MEMCFG_LSXINIT_INIT_LS0 0x1U // RAM Initialization control for LS0 RAM.
#define MEMCFG_LSXINIT_INIT_LS1 0x2U // RAM Initialization control for LS1 RAM.
#define MEMCFG_LSXINIT_INIT_LS2 0x4U // RAM Initialization control for LS2 RAM.
#define MEMCFG_LSXINIT_INIT_LS3 0x8U // RAM Initialization control for LS3 RAM.
#define MEMCFG_LSXINIT_INIT_LS4 0x10U // RAM Initialization control for LS4 RAM.
#define MEMCFG_LSXINIT_INIT_LS5 0x20U // RAM Initialization control for LS5 RAM.
//*************************************************************************************************
//
// The following are defines for the bit fields in the LSxINITDONE register
//
//*************************************************************************************************
#define MEMCFG_LSXINITDONE_INITDONE_LS0 0x1U // RAM Initialization status for LS0 RAM.
#define MEMCFG_LSXINITDONE_INITDONE_LS1 0x2U // RAM Initialization status for LS1 RAM.
#define MEMCFG_LSXINITDONE_INITDONE_LS2 0x4U // RAM Initialization status for LS2 RAM.
#define MEMCFG_LSXINITDONE_INITDONE_LS3 0x8U // RAM Initialization status for LS3 RAM.
#define MEMCFG_LSXINITDONE_INITDONE_LS4 0x10U // RAM Initialization status for LS4 RAM.
#define MEMCFG_LSXINITDONE_INITDONE_LS5 0x20U // RAM Initialization status for LS5 RAM.
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxLOCK register
//
//*************************************************************************************************
#define MEMCFG_GSXLOCK_LOCK_GS0 0x1U // GS0 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS1 0x2U // GS1 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS2 0x4U // GS2 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS3 0x8U // GS3 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS4 0x10U // GS4 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS5 0x20U // GS5 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS6 0x40U // GS6 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS7 0x80U // GS7 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS8 0x100U // GS8 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS9 0x200U // GS9 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS10 0x400U // GS10 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS11 0x800U // GS11 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS12 0x1000U // GS12 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS13 0x2000U // GS13 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS14 0x4000U // GS14 RAM access protection and master select fields
// lock bit
#define MEMCFG_GSXLOCK_LOCK_GS15 0x8000U // GS15 RAM access protection and master select fields
// lock bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxCOMMIT register
//
//*************************************************************************************************
#define MEMCFG_GSXCOMMIT_COMMIT_GS0 0x1U // GS0 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS1 0x2U // GS1 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS2 0x4U // GS2 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS3 0x8U // GS3 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS4 0x10U // GS4 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS5 0x20U // GS5 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS6 0x40U // GS6 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS7 0x80U // GS7 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS8 0x100U // GS8 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS9 0x200U // GS9 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS10 0x400U // GS10 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS11 0x800U // GS11 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS12 0x1000U // GS12 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS13 0x2000U // GS13 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS14 0x4000U // GS14 RAM access protection and master select
// permanent lock
#define MEMCFG_GSXCOMMIT_COMMIT_GS15 0x8000U // GS15 RAM access protection and master select
// permanent lock
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxMSEL register
//
//*************************************************************************************************
#define MEMCFG_GSXMSEL_MSEL_GS0 0x1U // Master Select for GS0 RAM
#define MEMCFG_GSXMSEL_MSEL_GS1 0x2U // Master Select for GS1 RAM
#define MEMCFG_GSXMSEL_MSEL_GS2 0x4U // Master Select for GS2 RAM
#define MEMCFG_GSXMSEL_MSEL_GS3 0x8U // Master Select for GS3 RAM
#define MEMCFG_GSXMSEL_MSEL_GS4 0x10U // Master Select for GS4 RAM
#define MEMCFG_GSXMSEL_MSEL_GS5 0x20U // Master Select for GS5 RAM
#define MEMCFG_GSXMSEL_MSEL_GS6 0x40U // Master Select for GS6 RAM
#define MEMCFG_GSXMSEL_MSEL_GS7 0x80U // Master Select for GS7 RAM
#define MEMCFG_GSXMSEL_MSEL_GS8 0x100U // Master Select for GS8 RAM
#define MEMCFG_GSXMSEL_MSEL_GS9 0x200U // Master Select for GS9 RAM
#define MEMCFG_GSXMSEL_MSEL_GS10 0x400U // Master Select for GS10 RAM
#define MEMCFG_GSXMSEL_MSEL_GS11 0x800U // Master Select for GS11 RAM
#define MEMCFG_GSXMSEL_MSEL_GS12 0x1000U // Master Select for GS12 RAM
#define MEMCFG_GSXMSEL_MSEL_GS13 0x2000U // Master Select for GS13 RAM
#define MEMCFG_GSXMSEL_MSEL_GS14 0x4000U // Master Select for GS14 RAM
#define MEMCFG_GSXMSEL_MSEL_GS15 0x8000U // Master Select for GS15 RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxACCPROT0 register
//
//*************************************************************************************************
#define MEMCFG_GSXACCPROT0_FETCHPROT_GS0 0x1U // Fetch Protection For GS0 RAM
#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS0 0x2U // CPU WR Protection For GS0 RAM
#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS0 0x4U // DMA WR Protection For GS0 RAM
#define MEMCFG_GSXACCPROT0_FETCHPROT_GS1 0x100U // Fetch Protection For GS1 RAM
#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS1 0x200U // CPU WR Protection For GS1 RAM
#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS1 0x400U // DMA WR Protection For GS1 RAM
#define MEMCFG_GSXACCPROT0_FETCHPROT_GS2 0x10000U // Fetch Protection For GS2 RAM
#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS2 0x20000U // CPU WR Protection For GS2 RAM
#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS2 0x40000U // DMA WR Protection For GS2 RAM
#define MEMCFG_GSXACCPROT0_FETCHPROT_GS3 0x1000000U // Fetch Protection For GS3 RAM
#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS3 0x2000000U // CPU WR Protection For GS3 RAM
#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS3 0x4000000U // DMA WR Protection For GS3 RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxACCPROT1 register
//
//*************************************************************************************************
#define MEMCFG_GSXACCPROT1_FETCHPROT_GS4 0x1U // Fetch Protection For GS4 RAM
#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS4 0x2U // CPU WR Protection For GS4 RAM
#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS4 0x4U // DMA WR Protection For GS4 RAM
#define MEMCFG_GSXACCPROT1_FETCHPROT_GS5 0x100U // Fetch Protection For GS5 RAM
#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS5 0x200U // CPU WR Protection For GS5 RAM
#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS5 0x400U // DMA WR Protection For GS5RAM
#define MEMCFG_GSXACCPROT1_FETCHPROT_GS6 0x10000U // Fetch Protection For GS6 RAM
#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS6 0x20000U // CPU WR Protection For GS6 RAM
#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS6 0x40000U // DMA WR Protection For GS6RAM
#define MEMCFG_GSXACCPROT1_FETCHPROT_GS7 0x1000000U // Fetch Protection For GS7 RAM
#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS7 0x2000000U // CPU WR Protection For GS7 RAM
#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS7 0x4000000U // DMA WR Protection For GS7RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxACCPROT2 register
//
//*************************************************************************************************
#define MEMCFG_GSXACCPROT2_FETCHPROT_GS8 0x1U // Fetch Protection For GS8 RAM
#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS8 0x2U // CPU WR Protection For GS8 RAM
#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS8 0x4U // DMA WR Protection For GS8 RAM
#define MEMCFG_GSXACCPROT2_FETCHPROT_GS9 0x100U // Fetch Protection For GS9 RAM
#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS9 0x200U // CPU WR Protection For GS9 RAM
#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS9 0x400U // DMA WR Protection For GS9RAM
#define MEMCFG_GSXACCPROT2_FETCHPROT_GS10 0x10000U // Fetch Protection For GS10 RAM
#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS10 0x20000U // CPU WR Protection For GS10 RAM
#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS10 0x40000U // DMA WR Protection For GS10RAM
#define MEMCFG_GSXACCPROT2_FETCHPROT_GS11 0x1000000U // Fetch Protection For GS11 RAM
#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS11 0x2000000U // CPU WR Protection For GS11 RAM
#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS11 0x4000000U // DMA WR Protection For GS11RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxACCPROT3 register
//
//*************************************************************************************************
#define MEMCFG_GSXACCPROT3_FETCHPROT_GS12 0x1U // Fetch Protection For GS12 RAM
#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS12 0x2U // CPU WR Protection For GS12 RAM
#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS12 0x4U // DMA WR Protection For GS12 RAM
#define MEMCFG_GSXACCPROT3_FETCHPROT_GS13 0x100U // Fetch Protection For GS13 RAM
#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS13 0x200U // CPU WR Protection For GS13 RAM
#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS13 0x400U // DMA WR Protection For GS13RAM
#define MEMCFG_GSXACCPROT3_FETCHPROT_GS14 0x10000U // Fetch Protection For GS14 RAM
#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS14 0x20000U // CPU WR Protection For GS14 RAM
#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS14 0x40000U // DMA WR Protection For GS14RAM
#define MEMCFG_GSXACCPROT3_FETCHPROT_GS15 0x1000000U // Fetch Protection For GS15 RAM
#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS15 0x2000000U // CPU WR Protection For GS15 RAM
#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS15 0x4000000U // DMA WR Protection For GS15RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxTEST register
//
//*************************************************************************************************
#define MEMCFG_GSXTEST_TEST_GS0_S 0U
#define MEMCFG_GSXTEST_TEST_GS0_M 0x3U // Selects the different modes for GS0 RAM
#define MEMCFG_GSXTEST_TEST_GS1_S 2U
#define MEMCFG_GSXTEST_TEST_GS1_M 0xCU // Selects the different modes for GS1 RAM
#define MEMCFG_GSXTEST_TEST_GS2_S 4U
#define MEMCFG_GSXTEST_TEST_GS2_M 0x30U // Selects the different modes for GS2 RAM
#define MEMCFG_GSXTEST_TEST_GS3_S 6U
#define MEMCFG_GSXTEST_TEST_GS3_M 0xC0U // Selects the different modes for GS3 RAM
#define MEMCFG_GSXTEST_TEST_GS4_S 8U
#define MEMCFG_GSXTEST_TEST_GS4_M 0x300U // Selects the different modes for GS4 RAM
#define MEMCFG_GSXTEST_TEST_GS5_S 10U
#define MEMCFG_GSXTEST_TEST_GS5_M 0xC00U // Selects the different modes for GS5 RAM
#define MEMCFG_GSXTEST_TEST_GS6_S 12U
#define MEMCFG_GSXTEST_TEST_GS6_M 0x3000U // Selects the different modes for GS6 RAM
#define MEMCFG_GSXTEST_TEST_GS7_S 14U
#define MEMCFG_GSXTEST_TEST_GS7_M 0xC000U // Selects the different modes for GS7 RAM
#define MEMCFG_GSXTEST_TEST_GS8_S 16U
#define MEMCFG_GSXTEST_TEST_GS8_M 0x30000U // Selects the different modes for GS8 RAM
#define MEMCFG_GSXTEST_TEST_GS9_S 18U
#define MEMCFG_GSXTEST_TEST_GS9_M 0xC0000U // Selects the different modes for GS9 RAM
#define MEMCFG_GSXTEST_TEST_GS10_S 20U
#define MEMCFG_GSXTEST_TEST_GS10_M 0x300000U // Selects the different modes for GS10 RAM
#define MEMCFG_GSXTEST_TEST_GS11_S 22U
#define MEMCFG_GSXTEST_TEST_GS11_M 0xC00000U // Selects the different modes for GS11 RAM
#define MEMCFG_GSXTEST_TEST_GS12_S 24U
#define MEMCFG_GSXTEST_TEST_GS12_M 0x3000000U // Selects the different modes for GS12 RAM
#define MEMCFG_GSXTEST_TEST_GS13_S 26U
#define MEMCFG_GSXTEST_TEST_GS13_M 0xC000000U // Selects the different modes for GS13 RAM
#define MEMCFG_GSXTEST_TEST_GS14_S 28U
#define MEMCFG_GSXTEST_TEST_GS14_M 0x30000000U // Selects the different modes for GS14 RAM
#define MEMCFG_GSXTEST_TEST_GS15_S 30U
#define MEMCFG_GSXTEST_TEST_GS15_M 0xC0000000U // Selects the different modes for GS15 RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxINIT register
//
//*************************************************************************************************
#define MEMCFG_GSXINIT_INIT_GS0 0x1U // RAM Initialization control for GS0 RAM.
#define MEMCFG_GSXINIT_INIT_GS1 0x2U // RAM Initialization control for GS1 RAM.
#define MEMCFG_GSXINIT_INIT_GS2 0x4U // RAM Initialization control for GS2 RAM.
#define MEMCFG_GSXINIT_INIT_GS3 0x8U // RAM Initialization control for GS3 RAM.
#define MEMCFG_GSXINIT_INIT_GS4 0x10U // RAM Initialization control for GS4 RAM.
#define MEMCFG_GSXINIT_INIT_GS5 0x20U // RAM Initialization control for GS5 RAM.
#define MEMCFG_GSXINIT_INIT_GS6 0x40U // RAM Initialization control for GS6 RAM.
#define MEMCFG_GSXINIT_INIT_GS7 0x80U // RAM Initialization control for GS7 RAM.
#define MEMCFG_GSXINIT_INIT_GS8 0x100U // RAM Initialization control for GS8 RAM.
#define MEMCFG_GSXINIT_INIT_GS9 0x200U // RAM Initialization control for GS9 RAM.
#define MEMCFG_GSXINIT_INIT_GS10 0x400U // RAM Initialization control for GS10 RAM.
#define MEMCFG_GSXINIT_INIT_GS11 0x800U // RAM Initialization control for GS11 RAM.
#define MEMCFG_GSXINIT_INIT_GS12 0x1000U // RAM Initialization control for GS12 RAM.
#define MEMCFG_GSXINIT_INIT_GS13 0x2000U // RAM Initialization control for GS13 RAM.
#define MEMCFG_GSXINIT_INIT_GS14 0x4000U // RAM Initialization control for GS14 RAM.
#define MEMCFG_GSXINIT_INIT_GS15 0x8000U // RAM Initialization control for GS15 RAM.
//*************************************************************************************************
//
// The following are defines for the bit fields in the GSxINITDONE register
//
//*************************************************************************************************
#define MEMCFG_GSXINITDONE_INITDONE_GS0 0x1U // RAM Initialization status for GS0 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS1 0x2U // RAM Initialization status for GS1 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS2 0x4U // RAM Initialization status for GS2 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS3 0x8U // RAM Initialization status for GS3 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS4 0x10U // RAM Initialization status for GS4 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS5 0x20U // RAM Initialization status for GS5 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS6 0x40U // RAM Initialization status for GS6 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS7 0x80U // RAM Initialization status for GS7 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS8 0x100U // RAM Initialization status for GS8 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS9 0x200U // RAM Initialization status for GS9 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS10 0x400U // RAM Initialization status for GS10 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS11 0x800U // RAM Initialization status for GS11 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS12 0x1000U // RAM Initialization status for GS12 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS13 0x2000U // RAM Initialization status for GS13 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS14 0x4000U // RAM Initialization status for GS14 RAM.
#define MEMCFG_GSXINITDONE_INITDONE_GS15 0x8000U // RAM Initialization status for GS15 RAM.
//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxTEST register
//
//*************************************************************************************************
#define MEMCFG_MSGXTEST_TEST_CPUTOCPU_S 0U
#define MEMCFG_MSGXTEST_TEST_CPUTOCPU_M 0x3U // CPU to CPU Mode Select
#define MEMCFG_MSGXTEST_TEST_CPUTOCLA1_S 2U
#define MEMCFG_MSGXTEST_TEST_CPUTOCLA1_M 0xCU // CPU to CLA1 MSG RAM Mode Select
#define MEMCFG_MSGXTEST_TEST_CLA1TOCPU_S 4U
#define MEMCFG_MSGXTEST_TEST_CLA1TOCPU_M 0x30U // CLA1 to CPU MSG RAM Mode Select
//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxINIT register
//
//*************************************************************************************************
#define MEMCFG_MSGXINIT_INIT_CPUTOCPU 0x1U // Initialization control for CPU to CPU MSG RAM
#define MEMCFG_MSGXINIT_INIT_CPUTOCLA1 0x2U // Initialization control for CPUTOCLA1 MSG RAM
#define MEMCFG_MSGXINIT_INIT_CLA1TOCPU 0x4U // Initialization control for CLA1TOCPU MSG RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the MSGxINITDONE register
//
//*************************************************************************************************
#define MEMCFG_MSGXINITDONE_INITDONE_CPUTOCPU 0x1U // Initialization status for CPU to CPU MSG
// RAM
#define MEMCFG_MSGXINITDONE_INITDONE_CPUTOCLA1 0x2U // Initialization status for CPU to CLA1
// MSG RAM
#define MEMCFG_MSGXINITDONE_INITDONE_CLA1TOCPU 0x4U // Initialization status for CLA1 to CPU
// MSG RAM
//*************************************************************************************************
//
// The following are defines for the bit fields in the EMIF1LOCK register
//
//*************************************************************************************************
#define MEMCFG_EMIF1LOCK_LOCK_EMIF1 0x1U // EMIF1 access protection and master select fields
// lock bit
//*************************************************************************************************
//
// The following are defines for the bit fields in the EMIF1COMMIT register
//
//*************************************************************************************************
#define MEMCFG_EMIF1COMMIT_COMMIT_EMIF1 0x1U // EMIF1 access protection and master select
// permanent lock
//*************************************************************************************************
//
// The following are defines for the bit fields in the EMIF1MSEL register
//
//*************************************************************************************************
#define MEMCFG_EMIF1MSEL_MSEL_EMIF1_S 0U
#define MEMCFG_EMIF1MSEL_MSEL_EMIF1_M 0x3U // Master Select for EMIF1.
#define MEMCFG_EMIF1MSEL_KEY_S 4U
#define MEMCFG_EMIF1MSEL_KEY_M 0xFFFFFFF0U // KEY to enable the write into MSEL_EMIF1
// bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the EMIF1ACCPROT0 register
//
//*************************************************************************************************
#define MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 0x1U // Fetch Protection For EMIF1
#define MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 0x2U // CPU WR Protection For EMIF1
#define MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1 0x4U // DMA WR Protection For EMIF1
//*************************************************************************************************
//
// The following are defines for the bit fields in the EMIF2LOCK register
//
//*************************************************************************************************
#define MEMCFG_EMIF2LOCK_LOCK_EMIF2 0x1U // EMIF2 access protection and master select permanent
// lock
//*************************************************************************************************
//
// The following are defines for the bit fields in the EMIF2COMMIT register
//
//*************************************************************************************************
#define MEMCFG_EMIF2COMMIT_COMMIT_EMIF2 0x1U // EMIF2 access protection and master select
// permanent lock
//*************************************************************************************************
//
// The following are defines for the bit fields in the EMIF2ACCPROT0 register
//
//*************************************************************************************************
#define MEMCFG_EMIF2ACCPROT0_FETCHPROT_EMIF2 0x1U // Fetch Protection For EMIF2
#define MEMCFG_EMIF2ACCPROT0_CPUWRPROT_EMIF2 0x2U // CPU WR Protection For EMIF2
//*************************************************************************************************
//
// The following are defines for the bit fields in the NMAVFLG register
//
//*************************************************************************************************
#define MEMCFG_NMAVFLG_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag
#define MEMCFG_NMAVFLG_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag
#define MEMCFG_NMAVFLG_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag
#define MEMCFG_NMAVFLG_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag
#define MEMCFG_NMAVFLG_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag
#define MEMCFG_NMAVFLG_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag
#define MEMCFG_NMAVFLG_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the NMAVSET register
//
//*************************************************************************************************
#define MEMCFG_NMAVSET_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag Set
#define MEMCFG_NMAVSET_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag Set
#define MEMCFG_NMAVSET_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag Set
#define MEMCFG_NMAVSET_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag Set
#define MEMCFG_NMAVSET_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag Set
#define MEMCFG_NMAVSET_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag Set
#define MEMCFG_NMAVSET_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag Set
//*************************************************************************************************
//
// The following are defines for the bit fields in the NMAVCLR register
//
//*************************************************************************************************
#define MEMCFG_NMAVCLR_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag Clear
#define MEMCFG_NMAVCLR_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag Clear
#define MEMCFG_NMAVCLR_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag Clear
#define MEMCFG_NMAVCLR_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag Clear
#define MEMCFG_NMAVCLR_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag Clear
#define MEMCFG_NMAVCLR_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag Clear
#define MEMCFG_NMAVCLR_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the NMAVINTEN register
//
//*************************************************************************************************
#define MEMCFG_NMAVINTEN_CPUREAD 0x1U // Non Master CPU Read Access Violation Interrupt
// Enable
#define MEMCFG_NMAVINTEN_CPUWRITE 0x2U // Non Master CPU Write Access Violation Interrupt
// Enable
#define MEMCFG_NMAVINTEN_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Interrupt
// Enable
#define MEMCFG_NMAVINTEN_DMAWRITE 0x8U // Non Master DMA Write Access Violation Interrupt
// Enable
#define MEMCFG_NMAVINTEN_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Interrupt
// Enable
#define MEMCFG_NMAVINTEN_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Interrupt
// Enable
#define MEMCFG_NMAVINTEN_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Interrupt
// Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the MAVFLG register
//
//*************************************************************************************************
#define MEMCFG_MAVFLG_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag
#define MEMCFG_MAVFLG_CPUWRITE 0x2U // Master CPU Write Access Violation Flag
#define MEMCFG_MAVFLG_DMAWRITE 0x4U // Master DMA Write Access Violation Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the MAVSET register
//
//*************************************************************************************************
#define MEMCFG_MAVSET_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag Set
#define MEMCFG_MAVSET_CPUWRITE 0x2U // Master CPU Write Access Violation Flag Set
#define MEMCFG_MAVSET_DMAWRITE 0x4U // Master DMA Write Access Violation Flag Set
//*************************************************************************************************
//
// The following are defines for the bit fields in the MAVCLR register
//
//*************************************************************************************************
#define MEMCFG_MAVCLR_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag Clear
#define MEMCFG_MAVCLR_CPUWRITE 0x2U // Master CPU Write Access Violation Flag Clear
#define MEMCFG_MAVCLR_DMAWRITE 0x4U // Master DMA Write Access Violation Flag Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the MAVINTEN register
//
//*************************************************************************************************
#define MEMCFG_MAVINTEN_CPUFETCH 0x1U // Master CPU Fetch Access Violation Interrupt Enable
#define MEMCFG_MAVINTEN_CPUWRITE 0x2U // Master CPU Write Access Violation Interrupt Enable
#define MEMCFG_MAVINTEN_DMAWRITE 0x4U // Master DMA Write Access Violation Interrupt Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the UCERRFLG register
//
//*************************************************************************************************
#define MEMCFG_UCERRFLG_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag
#define MEMCFG_UCERRFLG_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag
#define MEMCFG_UCERRFLG_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the UCERRSET register
//
//*************************************************************************************************
#define MEMCFG_UCERRSET_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag Set
#define MEMCFG_UCERRSET_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag Set
#define MEMCFG_UCERRSET_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag Set
//*************************************************************************************************
//
// The following are defines for the bit fields in the UCERRCLR register
//
//*************************************************************************************************
#define MEMCFG_UCERRCLR_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag Clear
#define MEMCFG_UCERRCLR_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag Clear
#define MEMCFG_UCERRCLR_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the CERRFLG register
//
//*************************************************************************************************
#define MEMCFG_CERRFLG_CPURDERR 0x1U // CPU Correctable Read Error Flag
#define MEMCFG_CERRFLG_DMARDERR 0x2U // DMA Correctable Read Error Flag
#define MEMCFG_CERRFLG_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the CERRSET register
//
//*************************************************************************************************
#define MEMCFG_CERRSET_CPURDERR 0x1U // CPU Correctable Read Error Flag Set
#define MEMCFG_CERRSET_DMARDERR 0x2U // DMA Correctable Read Error Flag Set
#define MEMCFG_CERRSET_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag Set
//*************************************************************************************************
//
// The following are defines for the bit fields in the CERRCLR register
//
//*************************************************************************************************
#define MEMCFG_CERRCLR_CPURDERR 0x1U // CPU Correctable Read Error Flag Clear
#define MEMCFG_CERRCLR_DMARDERR 0x2U // DMA Correctable Read Error Flag Clear
#define MEMCFG_CERRCLR_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the CEINTFLG register
//
//*************************************************************************************************
#define MEMCFG_CEINTFLG_CEINTFLAG 0x1U // Total corrected error count exceeded threshold flag.
//*************************************************************************************************
//
// The following are defines for the bit fields in the CEINTCLR register
//
//*************************************************************************************************
#define MEMCFG_CEINTCLR_CEINTCLR 0x1U // CPU Corrected Error Threshold Exceeded Error Clear.
//*************************************************************************************************
//
// The following are defines for the bit fields in the CEINTSET register
//
//*************************************************************************************************
#define MEMCFG_CEINTSET_CEINTSET 0x1U // Total corrected error count exceeded flag set.
//*************************************************************************************************
//
// The following are defines for the bit fields in the CEINTEN register
//
//*************************************************************************************************
#define MEMCFG_CEINTEN_CEINTEN 0x1U // CPU/DMA Correctable Error Interrupt Enable.
//*************************************************************************************************
//
// The following are defines for the bit fields in the ROMWAITSTATE register
//
//*************************************************************************************************
#define MEMCFG_ROMWAITSTATE_WSDISABLE 0x1U // C28x ROM Wait State Enable/Disable Control
//*************************************************************************************************
//
// The following are defines for the bit fields in the ROMPREFETCH register
//
//*************************************************************************************************
#define MEMCFG_ROMPREFETCH_PFENABLE 0x1U // ROM Prefetch Enable/Disable Control
#endif
28379d_P_SFRA/device/driverlib/inc/hw_memmap.h
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//###########################################################################
//
// FILE: hw_memmap.h
//
// TITLE: Macros defining the memory map of the C28x.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_MEMMAP_H
#define HW_MEMMAP_H
//*****************************************************************************
//
// The following are defines for the base address of the memories and
// peripherals.
//
//*****************************************************************************
#define M0_RAM_BASE 0x00000000U
#define M1_RAM_BASE 0x00000400U
#define ADCARESULT_BASE 0x00000B00U
#define ADCBRESULT_BASE 0x00000B20U
#define ADCCRESULT_BASE 0x00000B40U
#define ADCDRESULT_BASE 0x00000B60U
#define CPUTIMER0_BASE 0x00000C00U
#define CPUTIMER1_BASE 0x00000C08U
#define CPUTIMER2_BASE 0x00000C10U
#define CLA1_SOFTINT_BASE 0x00000CE0U
#define PIECTRL_BASE 0x00000CE0U
#define PIEVECTTABLE_BASE 0x00000D00U
#define DMA_BASE 0x00001000U
#define DMA_CH1_BASE 0x00001020U
#define DMA_CH2_BASE 0x00001040U
#define DMA_CH3_BASE 0x00001060U
#define DMA_CH4_BASE 0x00001080U
#define DMA_CH5_BASE 0x000010A0U
#define DMA_CH6_BASE 0x000010C0U
#define CLA1_BASE 0x00001400U
#define CLATOCPU_RAM_BASE 0x00001480U
#define CPUTOCLA_RAM_BASE 0x00001500U
#define CLB1_BASE 0x00003000U
#define CLB1_LOGICCFG_BASE 0x00003000U
#define CLB1_LOGICCTL_BASE 0x00003100U
#define CLB1_DATAEXCH_BASE 0x00003200U
#define CLB2_BASE 0x00003400U
#define CLB2_LOGICCFG_BASE 0x00003400U
#define CLB2_LOGICCTL_BASE 0x00003500U
#define CLB2_DATAEXCH_BASE 0x00003600U
#define CLB3_BASE 0x00003800U
#define CLB3_LOGICCFG_BASE 0x00003800U
#define CLB3_LOGICCTL_BASE 0x00003900U
#define CLB3_DATAEXCH_BASE 0x00003A00U
#define CLB4_BASE 0x00003C00U
#define CLB4_LOGICCFG_BASE 0x00003C00U
#define CLB4_LOGICCTL_BASE 0x00003D00U
#define CLB4_DATAEXCH_BASE 0x00003E00U
#define EPWM1_BASE 0x00004000U
#define EPWM2_BASE 0x00004100U
#define EPWM3_BASE 0x00004200U
#define EPWM4_BASE 0x00004300U
#define EPWM5_BASE 0x00004400U
#define EPWM6_BASE 0x00004500U
#define EPWM7_BASE 0x00004600U
#define EPWM8_BASE 0x00004700U
#define EPWM9_BASE 0x00004800U
#define EPWM10_BASE 0x00004900U
#define EPWM11_BASE 0x00004A00U
#define EPWM12_BASE 0x00004B00U
#define ECAP1_BASE 0x00005000U
#define ECAP2_BASE 0x00005020U
#define ECAP3_BASE 0x00005040U
#define ECAP4_BASE 0x00005060U
#define ECAP5_BASE 0x00005080U
#define ECAP6_BASE 0x000050A0U
#define EQEP1_BASE 0x00005100U
#define EQEP2_BASE 0x00005140U
#define EQEP3_BASE 0x00005180U
#define DACA_BASE 0x00005C00U
#define DACB_BASE 0x00005C10U
#define DACC_BASE 0x00005C20U
#define CMPSS1_BASE 0x00005C80U
#define CMPSS2_BASE 0x00005CA0U
#define CMPSS3_BASE 0x00005CC0U
#define CMPSS4_BASE 0x00005CE0U
#define CMPSS5_BASE 0x00005D00U
#define CMPSS6_BASE 0x00005D20U
#define CMPSS7_BASE 0x00005D40U
#define CMPSS8_BASE 0x00005D60U
#define SDFM1_BASE 0x00005E00U
#define SDFM2_BASE 0x00005E80U
#define MCBSPA_BASE 0x00006000U
#define MCBSPB_BASE 0x00006040U
#define SPIA_BASE 0x00006100U
#define SPIB_BASE 0x00006110U
#define SPIC_BASE 0x00006120U
#define UPP_BASE 0x00006200U
#define UPP_TX_MSG_RAM_BASE 0x00006C00U
#define UPP_RX_MSG_RAM_BASE 0x00006E00U
#define WD_BASE 0x00007000U
#define NMI_BASE 0x00007060U
#define XINT_BASE 0x00007070U
#define SCIA_BASE 0x00007200U
#define SCIB_BASE 0x00007210U
#define SCIC_BASE 0x00007220U
#define SCID_BASE 0x00007230U
#define I2CA_BASE 0x00007300U
#define I2CB_BASE 0x00007340U
#define ADCA_BASE 0x00007400U
#define ADCB_BASE 0x00007480U
#define ADCC_BASE 0x00007500U
#define ADCD_BASE 0x00007580U
#define INPUTXBAR_BASE 0x00007900U
#define XBAR_BASE 0x00007920U
#define SYNCSOC_BASE 0x00007940U
#define DMACLASRCSEL_BASE 0x00007980U
#define EPWMXBAR_BASE 0x00007A00U
#define CLBXBAR_BASE 0x00007A40U
#define OUTPUTXBAR_BASE 0x00007A80U
#define GPIOCTRL_BASE 0x00007C00U
#define GPIODATA_BASE 0x00007F00U
#define LS0_RAM_BASE 0x00008000U
#define LS1_RAM_BASE 0x00008800U
#define LS2_RAM_BASE 0x00009000U
#define LS3_RAM_BASE 0x00009800U
#define LS4_RAM_BASE 0x0000A000U
#define LS5_RAM_BASE 0x0000A800U
#define D0_RAM_BASE 0x0000B000U
#define D1_RAM_BASE 0x0000B800U
#define GS0_RAM_BASE 0x0000C000U
#define GS1_RAM_BASE 0x0000D000U
#define GS2_RAM_BASE 0x0000E000U
#define GS3_RAM_BASE 0x0000F000U
#define GS4_RAM_BASE 0x00010000U
#define GS5_RAM_BASE 0x00011000U
#define GS6_RAM_BASE 0x00012000U
#define GS7_RAM_BASE 0x00013000U
#define GS8_RAM_BASE 0x00014000U
#define GS9_RAM_BASE 0x00015000U
#define GS10_RAM_BASE 0x00016000U
#define GS11_RAM_BASE 0x00017000U
#define GS12_RAM_BASE 0x00018000U
#define GS13_RAM_BASE 0x00019000U
#define GS14_RAM_BASE 0x0001A000U
#define GS15_RAM_BASE 0x0001B000U
#define CPU2_TO_CPU1_MSG_RAM_BASE 0x0003F800U
#define CPU1_TO_CPU2_MSG_RAM_BASE 0x0003FC00U
#define USBA_BASE 0x00040000U
#define EMIF1_BASE 0x00047000U
#define EMIF2_BASE 0x00047800U
#define CANA_BASE 0x00048000U
#define CANA_MSG_RAM_BASE 0x00049000U
#define CANB_BASE 0x0004A000U
#define CANB_MSG_RAM_BASE 0x0004B000U
#define IPC_BASE 0x00050000U
#define FLASHPUMPSEMAPHORE_BASE 0x00050024U
#define DEVCFG_BASE 0x0005D000U
#define ANALOGSUBSYS_BASE 0x0005D180U
#define CLKCFG_BASE 0x0005D200U
#define CPUSYS_BASE 0x0005D300U
#define ROMPREFETCH_BASE 0x0005E608U
#define DCSM_Z1_BASE 0x0005F000U
#define DCSM_Z2_BASE 0x0005F040U
#define DCSMCOMMON_BASE 0x0005F070U
#define MEMCFG_BASE 0x0005F400U
#define EMIF1CONFIG_BASE 0x0005F480U
#define EMIF2CONFIG_BASE 0x0005F4A0U
#define ACCESSPROTECTION_BASE 0x0005F4C0U
#define MEMORYERROR_BASE 0x0005F500U
#define ROMWAITSTATE_BASE 0x0005F540U
#define FLASH0CTRL_BASE 0x0005F800U
#define FLASH0ECC_BASE 0x0005FB00U
#define DCSM_Z1OTP_BASE 0x00078000U
#define DCSM_Z2OTP_BASE 0x00078200U
#define UID_BASE 0x000703C0U
#endif
28379d_P_SFRA/device/driverlib/inc/hw_nmi.h
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//###########################################################################
//
// FILE: hw_nmi.h
//
// TITLE: Definitions for the NMI registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_NMI_H
#define HW_NMI_H
//*************************************************************************************************
//
// The following are defines for the NMI register offsets
//
//*************************************************************************************************
#define NMI_O_CFG 0x0U // NMI Configuration Register
#define NMI_O_FLG 0x1U // NMI Flag Register (XRSn Clear)
#define NMI_O_FLGCLR 0x2U // NMI Flag Clear Register
#define NMI_O_FLGFRC 0x3U // NMI Flag Force Register
#define NMI_O_WDCNT 0x4U // NMI Watchdog Counter Register
#define NMI_O_WDPRD 0x5U // NMI Watchdog Period Register
#define NMI_O_SHDFLG 0x6U // NMI Shadow Flag Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the NMICFG register
//
//*************************************************************************************************
#define NMI_CFG_NMIE 0x1U // Global NMI Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the NMIFLG register
//
//*************************************************************************************************
#define NMI_FLG_NMIINT 0x1U // NMI Interrupt Flag
#define NMI_FLG_CLOCKFAIL 0x2U // Clock Fail Interrupt Flag
#define NMI_FLG_RAMUNCERR 0x4U // RAM Uncorrectable Error NMI Flag
#define NMI_FLG_FLUNCERR 0x8U // Flash Uncorrectable Error NMI Flag
#define NMI_FLG_CPU1HWBISTERR 0x10U // HW BIST Error NMI Flag
#define NMI_FLG_CPU2HWBISTERR 0x20U // HW BIST Error NMI Flag
#define NMI_FLG_PIEVECTERR 0x40U // PIE Vector Fetch Error Flag
#define NMI_FLG_CLBNMI 0x100U // Configurable Logic Block NMI Flag
#define NMI_FLG_CPU2WDRSN 0x200U // CPU2 WDRSn Reset Indication Flag
#define NMI_FLG_CPU2NMIWDRSN 0x400U // CPU2 NMIWDRSn Reset Indication Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the NMIFLGCLR register
//
//*************************************************************************************************
#define NMI_FLGCLR_NMIINT 0x1U // NMIINT Flag Clear
#define NMI_FLGCLR_CLOCKFAIL 0x2U // CLOCKFAIL Flag Clear
#define NMI_FLGCLR_RAMUNCERR 0x4U // RAMUNCERR Flag Clear
#define NMI_FLGCLR_FLUNCERR 0x8U // FLUNCERR Flag Clear
#define NMI_FLGCLR_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Clear
#define NMI_FLGCLR_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Clear
#define NMI_FLGCLR_PIEVECTERR 0x40U // PIEVECTERR Flag Clear
#define NMI_FLGCLR_CLBNMI 0x100U // CLBNMI Flag Clear
#define NMI_FLGCLR_CPU2WDRSN 0x200U // CPU2WDRSn Flag Clear
#define NMI_FLGCLR_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Clear
#define NMI_FLGCLR_OVF 0x800U // OVF Flag Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the NMIFLGFRC register
//
//*************************************************************************************************
#define NMI_FLGFRC_CLOCKFAIL 0x2U // CLOCKFAIL Flag Force
#define NMI_FLGFRC_RAMUNCERR 0x4U // RAMUNCERR Flag Force
#define NMI_FLGFRC_FLUNCERR 0x8U // FLUNCERR Flag Force
#define NMI_FLGFRC_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Force
#define NMI_FLGFRC_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Force
#define NMI_FLGFRC_PIEVECTERR 0x40U // PIEVECTERR Flag Force
#define NMI_FLGFRC_CLBNMI 0x100U // CLBNMI Flag Force
#define NMI_FLGFRC_CPU2WDRSN 0x200U // CPU2WDRSn Flag Force
#define NMI_FLGFRC_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Force
#define NMI_FLGFRC_OVF 0x800U // OVF Flag Force
//*************************************************************************************************
//
// The following are defines for the bit fields in the NMISHDFLG register
//
//*************************************************************************************************
#define NMI_SHDFLG_CLOCKFAIL 0x2U // Shadow CLOCKFAIL Flag
#define NMI_SHDFLG_RAMUNCERR 0x4U // Shadow RAMUNCERR Flag
#define NMI_SHDFLG_FLUNCERR 0x8U // Shadow FLUNCERR Flag
#define NMI_SHDFLG_CPU1HWBISTERR 0x10U // Shadow CPU1HWBISTERR Flag
#define NMI_SHDFLG_CPU2HWBISTERR 0x20U // Shadow CPU2HWBISTERR Flag
#define NMI_SHDFLG_PIEVECTERR 0x40U // Shadow PIEVECTERR Flag
#define NMI_SHDFLG_CLBNMI 0x100U // Shadow CLBNMI Flag
#define NMI_SHDFLG_CPU2WDRSN 0x200U // Shadow CPU2WDRSn Flag
#define NMI_SHDFLG_CPU2NMIWDRSN 0x400U // Shadow CPU2NMIWDRSn Flag
#define NMI_SHDFLG_OVF 0x800U // Shadow OVF Flag
#endif
28379d_P_SFRA/device/driverlib/inc/hw_otp.h
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//###########################################################################
//
// FILE: hw_otp.h
//
// TITLE: Definitions for the OTP registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_OTP_H
#define HW_OTP_H
//*************************************************************************************************
//
// The following are defines for the OTP register offsets
//
//*************************************************************************************************
#define OTP_O_UID_PSRAND0 0x0U // UID Psuedo-random 160 bit number
#define OTP_O_UID_PSRAND1 0x2U // UID Psuedo-random 160 bit number
#define OTP_O_UID_PSRAND2 0x4U // UID Psuedo-random 160 bit number
#define OTP_O_UID_PSRAND3 0x6U // UID Psuedo-random 160 bit number
#define OTP_O_UID_PSRAND4 0x8U // UID Psuedo-random 160 bit number
#define OTP_O_UID_PSRAND5 0xAU // UID Psuedo-random 160 bit number
#define OTP_O_UID_UNIQUE 0xCU // UID UID Unique 32 bit number
#define OTP_O_UID_CHECKSUM 0xEU // UID Checksum
#endif
28379d_P_SFRA/device/driverlib/inc/hw_outputxbar.h
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28379d_P_SFRA/device/driverlib/inc/hw_pie.h
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//###########################################################################
//
// FILE: hw_pie.h
//
// TITLE: Definitions for the PIE registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_PIE_H
#define HW_PIE_H
//*************************************************************************************************
//
// The following are defines for the PIE register offsets
//
//*************************************************************************************************
#define PIE_O_CTRL 0x0U // ePIE Control Register
#define PIE_O_ACK 0x1U // Interrupt Acknowledge Register
#define PIE_O_IER1 0x2U // Interrupt Group 1 Enable Register
#define PIE_O_IFR1 0x3U // Interrupt Group 1 Flag Register
#define PIE_O_IER2 0x4U // Interrupt Group 2 Enable Register
#define PIE_O_IFR2 0x5U // Interrupt Group 2 Flag Register
#define PIE_O_IER3 0x6U // Interrupt Group 3 Enable Register
#define PIE_O_IFR3 0x7U // Interrupt Group 3 Flag Register
#define PIE_O_IER4 0x8U // Interrupt Group 4 Enable Register
#define PIE_O_IFR4 0x9U // Interrupt Group 4 Flag Register
#define PIE_O_IER5 0xAU // Interrupt Group 5 Enable Register
#define PIE_O_IFR5 0xBU // Interrupt Group 5 Flag Register
#define PIE_O_IER6 0xCU // Interrupt Group 6 Enable Register
#define PIE_O_IFR6 0xDU // Interrupt Group 6 Flag Register
#define PIE_O_IER7 0xEU // Interrupt Group 7 Enable Register
#define PIE_O_IFR7 0xFU // Interrupt Group 7 Flag Register
#define PIE_O_IER8 0x10U // Interrupt Group 8 Enable Register
#define PIE_O_IFR8 0x11U // Interrupt Group 8 Flag Register
#define PIE_O_IER9 0x12U // Interrupt Group 9 Enable Register
#define PIE_O_IFR9 0x13U // Interrupt Group 9 Flag Register
#define PIE_O_IER10 0x14U // Interrupt Group 10 Enable Register
#define PIE_O_IFR10 0x15U // Interrupt Group 10 Flag Register
#define PIE_O_IER11 0x16U // Interrupt Group 11 Enable Register
#define PIE_O_IFR11 0x17U // Interrupt Group 11 Flag Register
#define PIE_O_IER12 0x18U // Interrupt Group 12 Enable Register
#define PIE_O_IFR12 0x19U // Interrupt Group 12 Flag Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIECTRL register
//
//*************************************************************************************************
#define PIE_CTRL_ENPIE 0x1U // PIE Enable
#define PIE_CTRL_PIEVECT_S 1U
#define PIE_CTRL_PIEVECT_M 0xFFFEU // PIE Vector Address
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEACK register
//
//*************************************************************************************************
#define PIE_ACK_ACK1 0x1U // Acknowledge PIE Interrupt Group 1
#define PIE_ACK_ACK2 0x2U // Acknowledge PIE Interrupt Group 2
#define PIE_ACK_ACK3 0x4U // Acknowledge PIE Interrupt Group 3
#define PIE_ACK_ACK4 0x8U // Acknowledge PIE Interrupt Group 4
#define PIE_ACK_ACK5 0x10U // Acknowledge PIE Interrupt Group 5
#define PIE_ACK_ACK6 0x20U // Acknowledge PIE Interrupt Group 6
#define PIE_ACK_ACK7 0x40U // Acknowledge PIE Interrupt Group 7
#define PIE_ACK_ACK8 0x80U // Acknowledge PIE Interrupt Group 8
#define PIE_ACK_ACK9 0x100U // Acknowledge PIE Interrupt Group 9
#define PIE_ACK_ACK10 0x200U // Acknowledge PIE Interrupt Group 10
#define PIE_ACK_ACK11 0x400U // Acknowledge PIE Interrupt Group 11
#define PIE_ACK_ACK12 0x800U // Acknowledge PIE Interrupt Group 12
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER1 register
//
//*************************************************************************************************
#define PIE_IER1_INTX1 0x1U // Enable for Interrupt 1.1
#define PIE_IER1_INTX2 0x2U // Enable for Interrupt 1.2
#define PIE_IER1_INTX3 0x4U // Enable for Interrupt 1.3
#define PIE_IER1_INTX4 0x8U // Enable for Interrupt 1.4
#define PIE_IER1_INTX5 0x10U // Enable for Interrupt 1.5
#define PIE_IER1_INTX6 0x20U // Enable for Interrupt 1.6
#define PIE_IER1_INTX7 0x40U // Enable for Interrupt 1.7
#define PIE_IER1_INTX8 0x80U // Enable for Interrupt 1.8
#define PIE_IER1_INTX9 0x100U // Enable for Interrupt 1.9
#define PIE_IER1_INTX10 0x200U // Enable for Interrupt 1.10
#define PIE_IER1_INTX11 0x400U // Enable for Interrupt 1.11
#define PIE_IER1_INTX12 0x800U // Enable for Interrupt 1.12
#define PIE_IER1_INTX13 0x1000U // Enable for Interrupt 1.13
#define PIE_IER1_INTX14 0x2000U // Enable for Interrupt 1.14
#define PIE_IER1_INTX15 0x4000U // Enable for Interrupt 1.15
#define PIE_IER1_INTX16 0x8000U // Enable for Interrupt 1.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR1 register
//
//*************************************************************************************************
#define PIE_IFR1_INTX1 0x1U // Flag for Interrupt 1.1
#define PIE_IFR1_INTX2 0x2U // Flag for Interrupt 1.2
#define PIE_IFR1_INTX3 0x4U // Flag for Interrupt 1.3
#define PIE_IFR1_INTX4 0x8U // Flag for Interrupt 1.4
#define PIE_IFR1_INTX5 0x10U // Flag for Interrupt 1.5
#define PIE_IFR1_INTX6 0x20U // Flag for Interrupt 1.6
#define PIE_IFR1_INTX7 0x40U // Flag for Interrupt 1.7
#define PIE_IFR1_INTX8 0x80U // Flag for Interrupt 1.8
#define PIE_IFR1_INTX9 0x100U // Flag for Interrupt 1.9
#define PIE_IFR1_INTX10 0x200U // Flag for Interrupt 1.10
#define PIE_IFR1_INTX11 0x400U // Flag for Interrupt 1.11
#define PIE_IFR1_INTX12 0x800U // Flag for Interrupt 1.12
#define PIE_IFR1_INTX13 0x1000U // Flag for Interrupt 1.13
#define PIE_IFR1_INTX14 0x2000U // Flag for Interrupt 1.14
#define PIE_IFR1_INTX15 0x4000U // Flag for Interrupt 1.15
#define PIE_IFR1_INTX16 0x8000U // Flag for Interrupt 1.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER2 register
//
//*************************************************************************************************
#define PIE_IER2_INTX1 0x1U // Enable for Interrupt 2.1
#define PIE_IER2_INTX2 0x2U // Enable for Interrupt 2.2
#define PIE_IER2_INTX3 0x4U // Enable for Interrupt 2.3
#define PIE_IER2_INTX4 0x8U // Enable for Interrupt 2.4
#define PIE_IER2_INTX5 0x10U // Enable for Interrupt 2.5
#define PIE_IER2_INTX6 0x20U // Enable for Interrupt 2.6
#define PIE_IER2_INTX7 0x40U // Enable for Interrupt 2.7
#define PIE_IER2_INTX8 0x80U // Enable for Interrupt 2.8
#define PIE_IER2_INTX9 0x100U // Enable for Interrupt 2.9
#define PIE_IER2_INTX10 0x200U // Enable for Interrupt 2.10
#define PIE_IER2_INTX11 0x400U // Enable for Interrupt 2.11
#define PIE_IER2_INTX12 0x800U // Enable for Interrupt 2.12
#define PIE_IER2_INTX13 0x1000U // Enable for Interrupt 2.13
#define PIE_IER2_INTX14 0x2000U // Enable for Interrupt 2.14
#define PIE_IER2_INTX15 0x4000U // Enable for Interrupt 2.15
#define PIE_IER2_INTX16 0x8000U // Enable for Interrupt 2.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR2 register
//
//*************************************************************************************************
#define PIE_IFR2_INTX1 0x1U // Flag for Interrupt 2.1
#define PIE_IFR2_INTX2 0x2U // Flag for Interrupt 2.2
#define PIE_IFR2_INTX3 0x4U // Flag for Interrupt 2.3
#define PIE_IFR2_INTX4 0x8U // Flag for Interrupt 2.4
#define PIE_IFR2_INTX5 0x10U // Flag for Interrupt 2.5
#define PIE_IFR2_INTX6 0x20U // Flag for Interrupt 2.6
#define PIE_IFR2_INTX7 0x40U // Flag for Interrupt 2.7
#define PIE_IFR2_INTX8 0x80U // Flag for Interrupt 2.8
#define PIE_IFR2_INTX9 0x100U // Flag for Interrupt 2.9
#define PIE_IFR2_INTX10 0x200U // Flag for Interrupt 2.10
#define PIE_IFR2_INTX11 0x400U // Flag for Interrupt 2.11
#define PIE_IFR2_INTX12 0x800U // Flag for Interrupt 2.12
#define PIE_IFR2_INTX13 0x1000U // Flag for Interrupt 2.13
#define PIE_IFR2_INTX14 0x2000U // Flag for Interrupt 2.14
#define PIE_IFR2_INTX15 0x4000U // Flag for Interrupt 2.15
#define PIE_IFR2_INTX16 0x8000U // Flag for Interrupt 2.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER3 register
//
//*************************************************************************************************
#define PIE_IER3_INTX1 0x1U // Enable for Interrupt 3.1
#define PIE_IER3_INTX2 0x2U // Enable for Interrupt 3.2
#define PIE_IER3_INTX3 0x4U // Enable for Interrupt 3.3
#define PIE_IER3_INTX4 0x8U // Enable for Interrupt 3.4
#define PIE_IER3_INTX5 0x10U // Enable for Interrupt 3.5
#define PIE_IER3_INTX6 0x20U // Enable for Interrupt 3.6
#define PIE_IER3_INTX7 0x40U // Enable for Interrupt 3.7
#define PIE_IER3_INTX8 0x80U // Enable for Interrupt 3.8
#define PIE_IER3_INTX9 0x100U // Enable for Interrupt 3.9
#define PIE_IER3_INTX10 0x200U // Enable for Interrupt 3.10
#define PIE_IER3_INTX11 0x400U // Enable for Interrupt 3.11
#define PIE_IER3_INTX12 0x800U // Enable for Interrupt 3.12
#define PIE_IER3_INTX13 0x1000U // Enable for Interrupt 3.13
#define PIE_IER3_INTX14 0x2000U // Enable for Interrupt 3.14
#define PIE_IER3_INTX15 0x4000U // Enable for Interrupt 3.15
#define PIE_IER3_INTX16 0x8000U // Enable for Interrupt 3.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR3 register
//
//*************************************************************************************************
#define PIE_IFR3_INTX1 0x1U // Flag for Interrupt 3.1
#define PIE_IFR3_INTX2 0x2U // Flag for Interrupt 3.2
#define PIE_IFR3_INTX3 0x4U // Flag for Interrupt 3.3
#define PIE_IFR3_INTX4 0x8U // Flag for Interrupt 3.4
#define PIE_IFR3_INTX5 0x10U // Flag for Interrupt 3.5
#define PIE_IFR3_INTX6 0x20U // Flag for Interrupt 3.6
#define PIE_IFR3_INTX7 0x40U // Flag for Interrupt 3.7
#define PIE_IFR3_INTX8 0x80U // Flag for Interrupt 3.8
#define PIE_IFR3_INTX9 0x100U // Flag for Interrupt 3.9
#define PIE_IFR3_INTX10 0x200U // Flag for Interrupt 3.10
#define PIE_IFR3_INTX11 0x400U // Flag for Interrupt 3.11
#define PIE_IFR3_INTX12 0x800U // Flag for Interrupt 3.12
#define PIE_IFR3_INTX13 0x1000U // Flag for Interrupt 3.13
#define PIE_IFR3_INTX14 0x2000U // Flag for Interrupt 3.14
#define PIE_IFR3_INTX15 0x4000U // Flag for Interrupt 3.15
#define PIE_IFR3_INTX16 0x8000U // Flag for Interrupt 3.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER4 register
//
//*************************************************************************************************
#define PIE_IER4_INTX1 0x1U // Enable for Interrupt 4.1
#define PIE_IER4_INTX2 0x2U // Enable for Interrupt 4.2
#define PIE_IER4_INTX3 0x4U // Enable for Interrupt 4.3
#define PIE_IER4_INTX4 0x8U // Enable for Interrupt 4.4
#define PIE_IER4_INTX5 0x10U // Enable for Interrupt 4.5
#define PIE_IER4_INTX6 0x20U // Enable for Interrupt 4.6
#define PIE_IER4_INTX7 0x40U // Enable for Interrupt 4.7
#define PIE_IER4_INTX8 0x80U // Enable for Interrupt 4.8
#define PIE_IER4_INTX9 0x100U // Enable for Interrupt 4.9
#define PIE_IER4_INTX10 0x200U // Enable for Interrupt 4.10
#define PIE_IER4_INTX11 0x400U // Enable for Interrupt 4.11
#define PIE_IER4_INTX12 0x800U // Enable for Interrupt 4.12
#define PIE_IER4_INTX13 0x1000U // Enable for Interrupt 4.13
#define PIE_IER4_INTX14 0x2000U // Enable for Interrupt 4.14
#define PIE_IER4_INTX15 0x4000U // Enable for Interrupt 4.15
#define PIE_IER4_INTX16 0x8000U // Enable for Interrupt 4.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR4 register
//
//*************************************************************************************************
#define PIE_IFR4_INTX1 0x1U // Flag for Interrupt 4.1
#define PIE_IFR4_INTX2 0x2U // Flag for Interrupt 4.2
#define PIE_IFR4_INTX3 0x4U // Flag for Interrupt 4.3
#define PIE_IFR4_INTX4 0x8U // Flag for Interrupt 4.4
#define PIE_IFR4_INTX5 0x10U // Flag for Interrupt 4.5
#define PIE_IFR4_INTX6 0x20U // Flag for Interrupt 4.6
#define PIE_IFR4_INTX7 0x40U // Flag for Interrupt 4.7
#define PIE_IFR4_INTX8 0x80U // Flag for Interrupt 4.8
#define PIE_IFR4_INTX9 0x100U // Flag for Interrupt 4.9
#define PIE_IFR4_INTX10 0x200U // Flag for Interrupt 4.10
#define PIE_IFR4_INTX11 0x400U // Flag for Interrupt 4.11
#define PIE_IFR4_INTX12 0x800U // Flag for Interrupt 4.12
#define PIE_IFR4_INTX13 0x1000U // Flag for Interrupt 4.13
#define PIE_IFR4_INTX14 0x2000U // Flag for Interrupt 4.14
#define PIE_IFR4_INTX15 0x4000U // Flag for Interrupt 4.15
#define PIE_IFR4_INTX16 0x8000U // Flag for Interrupt 4.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER5 register
//
//*************************************************************************************************
#define PIE_IER5_INTX1 0x1U // Enable for Interrupt 5.1
#define PIE_IER5_INTX2 0x2U // Enable for Interrupt 5.2
#define PIE_IER5_INTX3 0x4U // Enable for Interrupt 5.3
#define PIE_IER5_INTX4 0x8U // Enable for Interrupt 5.4
#define PIE_IER5_INTX5 0x10U // Enable for Interrupt 5.5
#define PIE_IER5_INTX6 0x20U // Enable for Interrupt 5.6
#define PIE_IER5_INTX7 0x40U // Enable for Interrupt 5.7
#define PIE_IER5_INTX8 0x80U // Enable for Interrupt 5.8
#define PIE_IER5_INTX9 0x100U // Enable for Interrupt 5.9
#define PIE_IER5_INTX10 0x200U // Enable for Interrupt 5.10
#define PIE_IER5_INTX11 0x400U // Enable for Interrupt 5.11
#define PIE_IER5_INTX12 0x800U // Enable for Interrupt 5.12
#define PIE_IER5_INTX13 0x1000U // Enable for Interrupt 5.13
#define PIE_IER5_INTX14 0x2000U // Enable for Interrupt 5.14
#define PIE_IER5_INTX15 0x4000U // Enable for Interrupt 5.15
#define PIE_IER5_INTX16 0x8000U // Enable for Interrupt 5.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR5 register
//
//*************************************************************************************************
#define PIE_IFR5_INTX1 0x1U // Flag for Interrupt 5.1
#define PIE_IFR5_INTX2 0x2U // Flag for Interrupt 5.2
#define PIE_IFR5_INTX3 0x4U // Flag for Interrupt 5.3
#define PIE_IFR5_INTX4 0x8U // Flag for Interrupt 5.4
#define PIE_IFR5_INTX5 0x10U // Flag for Interrupt 5.5
#define PIE_IFR5_INTX6 0x20U // Flag for Interrupt 5.6
#define PIE_IFR5_INTX7 0x40U // Flag for Interrupt 5.7
#define PIE_IFR5_INTX8 0x80U // Flag for Interrupt 5.8
#define PIE_IFR5_INTX9 0x100U // Flag for Interrupt 5.9
#define PIE_IFR5_INTX10 0x200U // Flag for Interrupt 5.10
#define PIE_IFR5_INTX11 0x400U // Flag for Interrupt 5.11
#define PIE_IFR5_INTX12 0x800U // Flag for Interrupt 5.12
#define PIE_IFR5_INTX13 0x1000U // Flag for Interrupt 5.13
#define PIE_IFR5_INTX14 0x2000U // Flag for Interrupt 5.14
#define PIE_IFR5_INTX15 0x4000U // Flag for Interrupt 5.15
#define PIE_IFR5_INTX16 0x8000U // Flag for Interrupt 5.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER6 register
//
//*************************************************************************************************
#define PIE_IER6_INTX1 0x1U // Enable for Interrupt 6.1
#define PIE_IER6_INTX2 0x2U // Enable for Interrupt 6.2
#define PIE_IER6_INTX3 0x4U // Enable for Interrupt 6.3
#define PIE_IER6_INTX4 0x8U // Enable for Interrupt 6.4
#define PIE_IER6_INTX5 0x10U // Enable for Interrupt 6.5
#define PIE_IER6_INTX6 0x20U // Enable for Interrupt 6.6
#define PIE_IER6_INTX7 0x40U // Enable for Interrupt 6.7
#define PIE_IER6_INTX8 0x80U // Enable for Interrupt 6.8
#define PIE_IER6_INTX9 0x100U // Enable for Interrupt 6.9
#define PIE_IER6_INTX10 0x200U // Enable for Interrupt 6.10
#define PIE_IER6_INTX11 0x400U // Enable for Interrupt 6.11
#define PIE_IER6_INTX12 0x800U // Enable for Interrupt 6.12
#define PIE_IER6_INTX13 0x1000U // Enable for Interrupt 6.13
#define PIE_IER6_INTX14 0x2000U // Enable for Interrupt 6.14
#define PIE_IER6_INTX15 0x4000U // Enable for Interrupt 6.15
#define PIE_IER6_INTX16 0x8000U // Enable for Interrupt 6.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR6 register
//
//*************************************************************************************************
#define PIE_IFR6_INTX1 0x1U // Flag for Interrupt 6.1
#define PIE_IFR6_INTX2 0x2U // Flag for Interrupt 6.2
#define PIE_IFR6_INTX3 0x4U // Flag for Interrupt 6.3
#define PIE_IFR6_INTX4 0x8U // Flag for Interrupt 6.4
#define PIE_IFR6_INTX5 0x10U // Flag for Interrupt 6.5
#define PIE_IFR6_INTX6 0x20U // Flag for Interrupt 6.6
#define PIE_IFR6_INTX7 0x40U // Flag for Interrupt 6.7
#define PIE_IFR6_INTX8 0x80U // Flag for Interrupt 6.8
#define PIE_IFR6_INTX9 0x100U // Flag for Interrupt 6.9
#define PIE_IFR6_INTX10 0x200U // Flag for Interrupt 6.10
#define PIE_IFR6_INTX11 0x400U // Flag for Interrupt 6.11
#define PIE_IFR6_INTX12 0x800U // Flag for Interrupt 6.12
#define PIE_IFR6_INTX13 0x1000U // Flag for Interrupt 6.13
#define PIE_IFR6_INTX14 0x2000U // Flag for Interrupt 6.14
#define PIE_IFR6_INTX15 0x4000U // Flag for Interrupt 6.15
#define PIE_IFR6_INTX16 0x8000U // Flag for Interrupt 6.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER7 register
//
//*************************************************************************************************
#define PIE_IER7_INTX1 0x1U // Enable for Interrupt 7.1
#define PIE_IER7_INTX2 0x2U // Enable for Interrupt 7.2
#define PIE_IER7_INTX3 0x4U // Enable for Interrupt 7.3
#define PIE_IER7_INTX4 0x8U // Enable for Interrupt 7.4
#define PIE_IER7_INTX5 0x10U // Enable for Interrupt 7.5
#define PIE_IER7_INTX6 0x20U // Enable for Interrupt 7.6
#define PIE_IER7_INTX7 0x40U // Enable for Interrupt 7.7
#define PIE_IER7_INTX8 0x80U // Enable for Interrupt 7.8
#define PIE_IER7_INTX9 0x100U // Enable for Interrupt 7.9
#define PIE_IER7_INTX10 0x200U // Enable for Interrupt 7.10
#define PIE_IER7_INTX11 0x400U // Enable for Interrupt 7.11
#define PIE_IER7_INTX12 0x800U // Enable for Interrupt 7.12
#define PIE_IER7_INTX13 0x1000U // Enable for Interrupt 7.13
#define PIE_IER7_INTX14 0x2000U // Enable for Interrupt 7.14
#define PIE_IER7_INTX15 0x4000U // Enable for Interrupt 7.15
#define PIE_IER7_INTX16 0x8000U // Enable for Interrupt 7.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR7 register
//
//*************************************************************************************************
#define PIE_IFR7_INTX1 0x1U // Flag for Interrupt 7.1
#define PIE_IFR7_INTX2 0x2U // Flag for Interrupt 7.2
#define PIE_IFR7_INTX3 0x4U // Flag for Interrupt 7.3
#define PIE_IFR7_INTX4 0x8U // Flag for Interrupt 7.4
#define PIE_IFR7_INTX5 0x10U // Flag for Interrupt 7.5
#define PIE_IFR7_INTX6 0x20U // Flag for Interrupt 7.6
#define PIE_IFR7_INTX7 0x40U // Flag for Interrupt 7.7
#define PIE_IFR7_INTX8 0x80U // Flag for Interrupt 7.8
#define PIE_IFR7_INTX9 0x100U // Flag for Interrupt 7.9
#define PIE_IFR7_INTX10 0x200U // Flag for Interrupt 7.10
#define PIE_IFR7_INTX11 0x400U // Flag for Interrupt 7.11
#define PIE_IFR7_INTX12 0x800U // Flag for Interrupt 7.12
#define PIE_IFR7_INTX13 0x1000U // Flag for Interrupt 7.13
#define PIE_IFR7_INTX14 0x2000U // Flag for Interrupt 7.14
#define PIE_IFR7_INTX15 0x4000U // Flag for Interrupt 7.15
#define PIE_IFR7_INTX16 0x8000U // Flag for Interrupt 7.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER8 register
//
//*************************************************************************************************
#define PIE_IER8_INTX1 0x1U // Enable for Interrupt 8.1
#define PIE_IER8_INTX2 0x2U // Enable for Interrupt 8.2
#define PIE_IER8_INTX3 0x4U // Enable for Interrupt 8.3
#define PIE_IER8_INTX4 0x8U // Enable for Interrupt 8.4
#define PIE_IER8_INTX5 0x10U // Enable for Interrupt 8.5
#define PIE_IER8_INTX6 0x20U // Enable for Interrupt 8.6
#define PIE_IER8_INTX7 0x40U // Enable for Interrupt 8.7
#define PIE_IER8_INTX8 0x80U // Enable for Interrupt 8.8
#define PIE_IER8_INTX9 0x100U // Enable for Interrupt 8.9
#define PIE_IER8_INTX10 0x200U // Enable for Interrupt 8.10
#define PIE_IER8_INTX11 0x400U // Enable for Interrupt 8.11
#define PIE_IER8_INTX12 0x800U // Enable for Interrupt 8.12
#define PIE_IER8_INTX13 0x1000U // Enable for Interrupt 8.13
#define PIE_IER8_INTX14 0x2000U // Enable for Interrupt 8.14
#define PIE_IER8_INTX15 0x4000U // Enable for Interrupt 8.15
#define PIE_IER8_INTX16 0x8000U // Enable for Interrupt 8.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR8 register
//
//*************************************************************************************************
#define PIE_IFR8_INTX1 0x1U // Flag for Interrupt 8.1
#define PIE_IFR8_INTX2 0x2U // Flag for Interrupt 8.2
#define PIE_IFR8_INTX3 0x4U // Flag for Interrupt 8.3
#define PIE_IFR8_INTX4 0x8U // Flag for Interrupt 8.4
#define PIE_IFR8_INTX5 0x10U // Flag for Interrupt 8.5
#define PIE_IFR8_INTX6 0x20U // Flag for Interrupt 8.6
#define PIE_IFR8_INTX7 0x40U // Flag for Interrupt 8.7
#define PIE_IFR8_INTX8 0x80U // Flag for Interrupt 8.8
#define PIE_IFR8_INTX9 0x100U // Flag for Interrupt 8.9
#define PIE_IFR8_INTX10 0x200U // Flag for Interrupt 8.10
#define PIE_IFR8_INTX11 0x400U // Flag for Interrupt 8.11
#define PIE_IFR8_INTX12 0x800U // Flag for Interrupt 8.12
#define PIE_IFR8_INTX13 0x1000U // Flag for Interrupt 8.13
#define PIE_IFR8_INTX14 0x2000U // Flag for Interrupt 8.14
#define PIE_IFR8_INTX15 0x4000U // Flag for Interrupt 8.15
#define PIE_IFR8_INTX16 0x8000U // Flag for Interrupt 8.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER9 register
//
//*************************************************************************************************
#define PIE_IER9_INTX1 0x1U // Enable for Interrupt 9.1
#define PIE_IER9_INTX2 0x2U // Enable for Interrupt 9.2
#define PIE_IER9_INTX3 0x4U // Enable for Interrupt 9.3
#define PIE_IER9_INTX4 0x8U // Enable for Interrupt 9.4
#define PIE_IER9_INTX5 0x10U // Enable for Interrupt 9.5
#define PIE_IER9_INTX6 0x20U // Enable for Interrupt 9.6
#define PIE_IER9_INTX7 0x40U // Enable for Interrupt 9.7
#define PIE_IER9_INTX8 0x80U // Enable for Interrupt 9.8
#define PIE_IER9_INTX9 0x100U // Enable for Interrupt 9.9
#define PIE_IER9_INTX10 0x200U // Enable for Interrupt 9.10
#define PIE_IER9_INTX11 0x400U // Enable for Interrupt 9.11
#define PIE_IER9_INTX12 0x800U // Enable for Interrupt 9.12
#define PIE_IER9_INTX13 0x1000U // Enable for Interrupt 9.13
#define PIE_IER9_INTX14 0x2000U // Enable for Interrupt 9.14
#define PIE_IER9_INTX15 0x4000U // Enable for Interrupt 9.15
#define PIE_IER9_INTX16 0x8000U // Enable for Interrupt 9.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR9 register
//
//*************************************************************************************************
#define PIE_IFR9_INTX1 0x1U // Flag for Interrupt 9.1
#define PIE_IFR9_INTX2 0x2U // Flag for Interrupt 9.2
#define PIE_IFR9_INTX3 0x4U // Flag for Interrupt 9.3
#define PIE_IFR9_INTX4 0x8U // Flag for Interrupt 9.4
#define PIE_IFR9_INTX5 0x10U // Flag for Interrupt 9.5
#define PIE_IFR9_INTX6 0x20U // Flag for Interrupt 9.6
#define PIE_IFR9_INTX7 0x40U // Flag for Interrupt 9.7
#define PIE_IFR9_INTX8 0x80U // Flag for Interrupt 9.8
#define PIE_IFR9_INTX9 0x100U // Flag for Interrupt 9.9
#define PIE_IFR9_INTX10 0x200U // Flag for Interrupt 9.10
#define PIE_IFR9_INTX11 0x400U // Flag for Interrupt 9.11
#define PIE_IFR9_INTX12 0x800U // Flag for Interrupt 9.12
#define PIE_IFR9_INTX13 0x1000U // Flag for Interrupt 9.13
#define PIE_IFR9_INTX14 0x2000U // Flag for Interrupt 9.14
#define PIE_IFR9_INTX15 0x4000U // Flag for Interrupt 9.15
#define PIE_IFR9_INTX16 0x8000U // Flag for Interrupt 9.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER10 register
//
//*************************************************************************************************
#define PIE_IER10_INTX1 0x1U // Enable for Interrupt 10.1
#define PIE_IER10_INTX2 0x2U // Enable for Interrupt 10.2
#define PIE_IER10_INTX3 0x4U // Enable for Interrupt 10.3
#define PIE_IER10_INTX4 0x8U // Enable for Interrupt 10.4
#define PIE_IER10_INTX5 0x10U // Enable for Interrupt 10.5
#define PIE_IER10_INTX6 0x20U // Enable for Interrupt 10.6
#define PIE_IER10_INTX7 0x40U // Enable for Interrupt 10.7
#define PIE_IER10_INTX8 0x80U // Enable for Interrupt 10.8
#define PIE_IER10_INTX9 0x100U // Enable for Interrupt 10.9
#define PIE_IER10_INTX10 0x200U // Enable for Interrupt 10.10
#define PIE_IER10_INTX11 0x400U // Enable for Interrupt 10.11
#define PIE_IER10_INTX12 0x800U // Enable for Interrupt 10.12
#define PIE_IER10_INTX13 0x1000U // Enable for Interrupt 10.13
#define PIE_IER10_INTX14 0x2000U // Enable for Interrupt 10.14
#define PIE_IER10_INTX15 0x4000U // Enable for Interrupt 10.15
#define PIE_IER10_INTX16 0x8000U // Enable for Interrupt 10.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR10 register
//
//*************************************************************************************************
#define PIE_IFR10_INTX1 0x1U // Flag for Interrupt 10.1
#define PIE_IFR10_INTX2 0x2U // Flag for Interrupt 10.2
#define PIE_IFR10_INTX3 0x4U // Flag for Interrupt 10.3
#define PIE_IFR10_INTX4 0x8U // Flag for Interrupt 10.4
#define PIE_IFR10_INTX5 0x10U // Flag for Interrupt 10.5
#define PIE_IFR10_INTX6 0x20U // Flag for Interrupt 10.6
#define PIE_IFR10_INTX7 0x40U // Flag for Interrupt 10.7
#define PIE_IFR10_INTX8 0x80U // Flag for Interrupt 10.8
#define PIE_IFR10_INTX9 0x100U // Flag for Interrupt 10.9
#define PIE_IFR10_INTX10 0x200U // Flag for Interrupt 10.10
#define PIE_IFR10_INTX11 0x400U // Flag for Interrupt 10.11
#define PIE_IFR10_INTX12 0x800U // Flag for Interrupt 10.12
#define PIE_IFR10_INTX13 0x1000U // Flag for Interrupt 10.13
#define PIE_IFR10_INTX14 0x2000U // Flag for Interrupt 10.14
#define PIE_IFR10_INTX15 0x4000U // Flag for Interrupt 10.15
#define PIE_IFR10_INTX16 0x8000U // Flag for Interrupt 10.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER11 register
//
//*************************************************************************************************
#define PIE_IER11_INTX1 0x1U // Enable for Interrupt 11.1
#define PIE_IER11_INTX2 0x2U // Enable for Interrupt 11.2
#define PIE_IER11_INTX3 0x4U // Enable for Interrupt 11.3
#define PIE_IER11_INTX4 0x8U // Enable for Interrupt 11.4
#define PIE_IER11_INTX5 0x10U // Enable for Interrupt 11.5
#define PIE_IER11_INTX6 0x20U // Enable for Interrupt 11.6
#define PIE_IER11_INTX7 0x40U // Enable for Interrupt 11.7
#define PIE_IER11_INTX8 0x80U // Enable for Interrupt 11.8
#define PIE_IER11_INTX9 0x100U // Enable for Interrupt 11.9
#define PIE_IER11_INTX10 0x200U // Enable for Interrupt 11.10
#define PIE_IER11_INTX11 0x400U // Enable for Interrupt 11.11
#define PIE_IER11_INTX12 0x800U // Enable for Interrupt 11.12
#define PIE_IER11_INTX13 0x1000U // Enable for Interrupt 11.13
#define PIE_IER11_INTX14 0x2000U // Enable for Interrupt 11.14
#define PIE_IER11_INTX15 0x4000U // Enable for Interrupt 11.15
#define PIE_IER11_INTX16 0x8000U // Enable for Interrupt 11.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR11 register
//
//*************************************************************************************************
#define PIE_IFR11_INTX1 0x1U // Flag for Interrupt 11.1
#define PIE_IFR11_INTX2 0x2U // Flag for Interrupt 11.2
#define PIE_IFR11_INTX3 0x4U // Flag for Interrupt 11.3
#define PIE_IFR11_INTX4 0x8U // Flag for Interrupt 11.4
#define PIE_IFR11_INTX5 0x10U // Flag for Interrupt 11.5
#define PIE_IFR11_INTX6 0x20U // Flag for Interrupt 11.6
#define PIE_IFR11_INTX7 0x40U // Flag for Interrupt 11.7
#define PIE_IFR11_INTX8 0x80U // Flag for Interrupt 11.8
#define PIE_IFR11_INTX9 0x100U // Flag for Interrupt 11.9
#define PIE_IFR11_INTX10 0x200U // Flag for Interrupt 11.10
#define PIE_IFR11_INTX11 0x400U // Flag for Interrupt 11.11
#define PIE_IFR11_INTX12 0x800U // Flag for Interrupt 11.12
#define PIE_IFR11_INTX13 0x1000U // Flag for Interrupt 11.13
#define PIE_IFR11_INTX14 0x2000U // Flag for Interrupt 11.14
#define PIE_IFR11_INTX15 0x4000U // Flag for Interrupt 11.15
#define PIE_IFR11_INTX16 0x8000U // Flag for Interrupt 11.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIER12 register
//
//*************************************************************************************************
#define PIE_IER12_INTX1 0x1U // Enable for Interrupt 12.1
#define PIE_IER12_INTX2 0x2U // Enable for Interrupt 12.2
#define PIE_IER12_INTX3 0x4U // Enable for Interrupt 12.3
#define PIE_IER12_INTX4 0x8U // Enable for Interrupt 12.4
#define PIE_IER12_INTX5 0x10U // Enable for Interrupt 12.5
#define PIE_IER12_INTX6 0x20U // Enable for Interrupt 12.6
#define PIE_IER12_INTX7 0x40U // Enable for Interrupt 12.7
#define PIE_IER12_INTX8 0x80U // Enable for Interrupt 12.8
#define PIE_IER12_INTX9 0x100U // Enable for Interrupt 12.9
#define PIE_IER12_INTX10 0x200U // Enable for Interrupt 12.10
#define PIE_IER12_INTX11 0x400U // Enable for Interrupt 12.11
#define PIE_IER12_INTX12 0x800U // Enable for Interrupt 12.12
#define PIE_IER12_INTX13 0x1000U // Enable for Interrupt 12.13
#define PIE_IER12_INTX14 0x2000U // Enable for Interrupt 12.14
#define PIE_IER12_INTX15 0x4000U // Enable for Interrupt 12.15
#define PIE_IER12_INTX16 0x8000U // Enable for Interrupt 12.16
//*************************************************************************************************
//
// The following are defines for the bit fields in the PIEIFR12 register
//
//*************************************************************************************************
#define PIE_IFR12_INTX1 0x1U // Flag for Interrupt 12.1
#define PIE_IFR12_INTX2 0x2U // Flag for Interrupt 12.2
#define PIE_IFR12_INTX3 0x4U // Flag for Interrupt 12.3
#define PIE_IFR12_INTX4 0x8U // Flag for Interrupt 12.4
#define PIE_IFR12_INTX5 0x10U // Flag for Interrupt 12.5
#define PIE_IFR12_INTX6 0x20U // Flag for Interrupt 12.6
#define PIE_IFR12_INTX7 0x40U // Flag for Interrupt 12.7
#define PIE_IFR12_INTX8 0x80U // Flag for Interrupt 12.8
#define PIE_IFR12_INTX9 0x100U // Flag for Interrupt 12.9
#define PIE_IFR12_INTX10 0x200U // Flag for Interrupt 12.10
#define PIE_IFR12_INTX11 0x400U // Flag for Interrupt 12.11
#define PIE_IFR12_INTX12 0x800U // Flag for Interrupt 12.12
#define PIE_IFR12_INTX13 0x1000U // Flag for Interrupt 12.13
#define PIE_IFR12_INTX14 0x2000U // Flag for Interrupt 12.14
#define PIE_IFR12_INTX15 0x4000U // Flag for Interrupt 12.15
#define PIE_IFR12_INTX16 0x8000U // Flag for Interrupt 12.16
#endif
28379d_P_SFRA/device/driverlib/inc/hw_sci.h
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//###########################################################################
//
// FILE: hw_sci.h
//
// TITLE: Definitions for the SCI registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_SCI_H
#define HW_SCI_H
//*************************************************************************************************
//
// The following are defines for the SCI register offsets
//
//*************************************************************************************************
#define SCI_O_CCR 0x0U // Communications control register
#define SCI_O_CTL1 0x1U // Control register 1
#define SCI_O_HBAUD 0x2U // Baud rate (high) register
#define SCI_O_LBAUD 0x3U // Baud rate (low) register
#define SCI_O_CTL2 0x4U // Control register 2
#define SCI_O_RXST 0x5U // Receive status register
#define SCI_O_RXEMU 0x6U // Receive emulation buffer register
#define SCI_O_RXBUF 0x7U // Receive data buffer
#define SCI_O_TXBUF 0x9U // Transmit data buffer
#define SCI_O_FFTX 0xAU // FIFO transmit register
#define SCI_O_FFRX 0xBU // FIFO receive register
#define SCI_O_FFCT 0xCU // FIFO control register
#define SCI_O_PRI 0xFU // SCI priority control
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCICCR register
//
//*************************************************************************************************
#define SCI_CCR_SCICHAR_S 0U
#define SCI_CCR_SCICHAR_M 0x7U // Character length control
#define SCI_CCR_ADDRIDLE_MODE 0x8U // ADDR/IDLE Mode control
#define SCI_CCR_LOOPBKENA 0x10U // Loop Back enable
#define SCI_CCR_PARITYENA 0x20U // Parity enable
#define SCI_CCR_PARITY 0x40U // Even or Odd Parity
#define SCI_CCR_STOPBITS 0x80U // Number of Stop Bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCICTL1 register
//
//*************************************************************************************************
#define SCI_CTL1_RXENA 0x1U // SCI receiver enable
#define SCI_CTL1_TXENA 0x2U // SCI transmitter enable
#define SCI_CTL1_SLEEP 0x4U // SCI sleep
#define SCI_CTL1_TXWAKE 0x8U // Transmitter wakeup method
#define SCI_CTL1_SWRESET 0x20U // Software reset
#define SCI_CTL1_RXERRINTENA 0x40U // Receive error interrupt enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIHBAUD register
//
//*************************************************************************************************
#define SCI_HBAUD_BAUD_S 0U
#define SCI_HBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCIHBAUD
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCILBAUD register
//
//*************************************************************************************************
#define SCI_LBAUD_BAUD_S 0U
#define SCI_LBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCILBAUD
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCICTL2 register
//
//*************************************************************************************************
#define SCI_CTL2_TXINTENA 0x1U // Transmit __interrupt enable
#define SCI_CTL2_RXBKINTENA 0x2U // Receiver-buffer break enable
#define SCI_CTL2_TXEMPTY 0x40U // Transmitter empty flag
#define SCI_CTL2_TXRDY 0x80U // Transmitter ready flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIRXST register
//
//*************************************************************************************************
#define SCI_RXST_RXWAKE 0x2U // Receiver wakeup detect flag
#define SCI_RXST_PE 0x4U // Parity error flag
#define SCI_RXST_OE 0x8U // Overrun error flag
#define SCI_RXST_FE 0x10U // Framing error flag
#define SCI_RXST_BRKDT 0x20U // Break-detect flag
#define SCI_RXST_RXRDY 0x40U // Receiver ready flag
#define SCI_RXST_RXERROR 0x80U // Receiver error flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIRXEMU register
//
//*************************************************************************************************
#define SCI_RXEMU_ERXDT_S 0U
#define SCI_RXEMU_ERXDT_M 0xFFU // Receive emulation buffer data
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIRXBUF register
//
//*************************************************************************************************
#define SCI_RXBUF_SAR_S 0U
#define SCI_RXBUF_SAR_M 0xFFU // Receive Character bits
#define SCI_RXBUF_SCIFFPE 0x4000U // Receiver error flag
#define SCI_RXBUF_SCIFFFE 0x8000U // Receiver error flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCITXBUF register
//
//*************************************************************************************************
#define SCI_TXBUF_TXDT_S 0U
#define SCI_TXBUF_TXDT_M 0xFFU // Transmit data buffer
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFFTX register
//
//*************************************************************************************************
#define SCI_FFTX_TXFFIL_S 0U
#define SCI_FFTX_TXFFIL_M 0x1FU // Interrupt level
#define SCI_FFTX_TXFFIENA 0x20U // Interrupt enable
#define SCI_FFTX_TXFFINTCLR 0x40U // Clear INT flag
#define SCI_FFTX_TXFFINT 0x80U // INT flag
#define SCI_FFTX_TXFFST_S 8U
#define SCI_FFTX_TXFFST_M 0x1F00U // FIFO status
#define SCI_FFTX_TXFIFORESET 0x2000U // FIFO reset
#define SCI_FFTX_SCIFFENA 0x4000U // Enhancement enable
#define SCI_FFTX_SCIRST 0x8000U // SCI reset rx/tx channels
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFFRX register
//
//*************************************************************************************************
#define SCI_FFRX_RXFFIL_S 0U
#define SCI_FFRX_RXFFIL_M 0x1FU // Interrupt level
#define SCI_FFRX_RXFFIENA 0x20U // Interrupt enable
#define SCI_FFRX_RXFFINTCLR 0x40U // Clear INT flag
#define SCI_FFRX_RXFFINT 0x80U // INT flag
#define SCI_FFRX_RXFFST_S 8U
#define SCI_FFRX_RXFFST_M 0x1F00U // FIFO status
#define SCI_FFRX_RXFIFORESET 0x2000U // FIFO reset
#define SCI_FFRX_RXFFOVRCLR 0x4000U // Clear overflow
#define SCI_FFRX_RXFFOVF 0x8000U // FIFO overflow
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIFFCT register
//
//*************************************************************************************************
#define SCI_FFCT_FFTXDLY_S 0U
#define SCI_FFCT_FFTXDLY_M 0xFFU // FIFO transmit delay
#define SCI_FFCT_CDC 0x2000U // Auto baud mode enable
#define SCI_FFCT_ABDCLR 0x4000U // Auto baud clear
#define SCI_FFCT_ABD 0x8000U // Auto baud detect
//*************************************************************************************************
//
// The following are defines for the bit fields in the SCIPRI register
//
//*************************************************************************************************
#define SCI_PRI_FREESOFT_S 3U
#define SCI_PRI_FREESOFT_M 0x18U // Emulation modes
#endif
28379d_P_SFRA/device/driverlib/inc/hw_sdfm.h
+431
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//###########################################################################
//
// FILE: hw_sdfm.h
//
// TITLE: Definitions for the SDFM registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_SDFM_H
#define HW_SDFM_H
//*************************************************************************************************
//
// The following are defines for the SDFM register offsets
//
//*************************************************************************************************
#define SDFM_O_SDIFLG 0x0U // Interrupt Flag Register
#define SDFM_O_SDIFLGCLR 0x2U // Interrupt Flag Clear Register
#define SDFM_O_SDCTL 0x4U // SD Control Register
#define SDFM_O_SDMFILEN 0x6U // SD Master Filter Enable
#define SDFM_O_SDCTLPARM1 0x10U // Control Parameter Register for Ch1
#define SDFM_O_SDDFPARM1 0x11U // Data Filter Parameter Register for Ch1
#define SDFM_O_SDDPARM1 0x12U // Integer Parameter Register for Ch1
#define SDFM_O_SDCMPH1 0x13U // High-level Threshold Register for Ch1
#define SDFM_O_SDCMPL1 0x14U // Low-level Threshold Register for Ch1
#define SDFM_O_SDCPARM1 0x15U // Comparator Parameter Register for Ch1
#define SDFM_O_SDDATA1 0x16U // Filter Data Register (16 or 32bit) for Ch1
#define SDFM_O_SDCTLPARM2 0x20U // Control Parameter Register for Ch2
#define SDFM_O_SDDFPARM2 0x21U // Data Filter Parameter Register for Ch2
#define SDFM_O_SDDPARM2 0x22U // Integer Parameter Register for Ch2
#define SDFM_O_SDCMPH2 0x23U // High-level Threshold Register for Ch2
#define SDFM_O_SDCMPL2 0x24U // Low-level Threshold Register for Ch2
#define SDFM_O_SDCPARM2 0x25U // Comparator Parameter Register for Ch2
#define SDFM_O_SDDATA2 0x26U // Filter Data Register (16 or 32bit) for Ch2
#define SDFM_O_SDCTLPARM3 0x30U // Control Parameter Register for Ch3
#define SDFM_O_SDDFPARM3 0x31U // Data Filter Parameter Register for Ch3
#define SDFM_O_SDDPARM3 0x32U // Integer Parameter Register for Ch3
#define SDFM_O_SDCMPH3 0x33U // High-level Threshold Register for Ch3
#define SDFM_O_SDCMPL3 0x34U // Low-level Threshold Register for Ch3
#define SDFM_O_SDCPARM3 0x35U // Comparator Parameter Register for Ch3
#define SDFM_O_SDDATA3 0x36U // Filter Data Register (16 or 32bit) for Ch3
#define SDFM_O_SDCTLPARM4 0x40U // Control Parameter Register for Ch4
#define SDFM_O_SDDFPARM4 0x41U // Data Filter Parameter Register for Ch4
#define SDFM_O_SDDPARM4 0x42U // Integer Parameter Register for Ch4
#define SDFM_O_SDCMPH4 0x43U // High-level Threshold Register for Ch4
#define SDFM_O_SDCMPL4 0x44U // Low-level Threshold Register for Ch4
#define SDFM_O_SDCPARM4 0x45U // Comparator Parameter Register for Ch4
#define SDFM_O_SDDATA4 0x46U // Filter Data Register (16 or 32bit) for Ch4
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDIFLG register
//
//*************************************************************************************************
#define SDFM_SDIFLG_IFH1 0x1U // High-level Interrupt flag Filter 1
#define SDFM_SDIFLG_IFL1 0x2U // Low-Level Interrupt flag Filter 1
#define SDFM_SDIFLG_IFH2 0x4U // High-level Interrupt flag Filter 2
#define SDFM_SDIFLG_IFL2 0x8U // Low-Level Interrupt flag Filter 2
#define SDFM_SDIFLG_IFH3 0x10U // High-level Interrupt flag Filter 3
#define SDFM_SDIFLG_IFL3 0x20U // Low-Level Interrupt flag Filter 3
#define SDFM_SDIFLG_IFH4 0x40U // High-level Interrupt flag Filter 4
#define SDFM_SDIFLG_IFL4 0x80U // Low-Level Interrupt flag Filter 4
#define SDFM_SDIFLG_MF1 0x100U // Modulator Failure for Filter 1
#define SDFM_SDIFLG_MF2 0x200U // Modulator Failure for Filter 2
#define SDFM_SDIFLG_MF3 0x400U // Modulator Failure for Filter 3
#define SDFM_SDIFLG_MF4 0x800U // Modulator Failure for Filter 4
#define SDFM_SDIFLG_AF1 0x1000U // Acknowledge flag for Filter 1
#define SDFM_SDIFLG_AF2 0x2000U // Acknowledge flag for Filter 2
#define SDFM_SDIFLG_AF3 0x4000U // Acknowledge flag for Filter 3
#define SDFM_SDIFLG_AF4 0x8000U // Acknowledge flag for Filter 4
#define SDFM_SDIFLG_MIF 0x80000000U // Master Interrupt Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDIFLGCLR register
//
//*************************************************************************************************
#define SDFM_SDIFLGCLR_IFH1 0x1U // High-level Interrupt flag Filter 1
#define SDFM_SDIFLGCLR_IFL1 0x2U // Low-Level Interrupt flag Filter 1
#define SDFM_SDIFLGCLR_IFH2 0x4U // High-level Interrupt flag Filter 2
#define SDFM_SDIFLGCLR_IFL2 0x8U // Low-Level Interrupt flag Filter 2
#define SDFM_SDIFLGCLR_IFH3 0x10U // High-level Interrupt flag Filter 3
#define SDFM_SDIFLGCLR_IFL3 0x20U // Low-Level Interrupt flag Filter 3
#define SDFM_SDIFLGCLR_IFH4 0x40U // High-level Interrupt flag Filter 4
#define SDFM_SDIFLGCLR_IFL4 0x80U // Low-Level Interrupt flag Filter 4
#define SDFM_SDIFLGCLR_MF1 0x100U // Modulator Failure for Filter 1
#define SDFM_SDIFLGCLR_MF2 0x200U // Modulator Failure for Filter 2
#define SDFM_SDIFLGCLR_MF3 0x400U // Modulator Failure for Filter 3
#define SDFM_SDIFLGCLR_MF4 0x800U // Modulator Failure for Filter 4
#define SDFM_SDIFLGCLR_AF1 0x1000U // Acknowledge flag for Filter 1
#define SDFM_SDIFLGCLR_AF2 0x2000U // Acknowledge flag for Filter 2
#define SDFM_SDIFLGCLR_AF3 0x4000U // Acknowledge flag for Filter 3
#define SDFM_SDIFLGCLR_AF4 0x8000U // Acknowledge flag for Filter 4
#define SDFM_SDIFLGCLR_MIF 0x80000000U // Master Interrupt Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTL register
//
//*************************************************************************************************
#define SDFM_SDCTL_MIE 0x2000U // Master Interrupt enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDMFILEN register
//
//*************************************************************************************************
#define SDFM_SDMFILEN_MFE 0x800U // Master Filter Enable.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTLPARM1 register
//
//*************************************************************************************************
#define SDFM_SDCTLPARM1_MOD_S 0U
#define SDFM_SDCTLPARM1_MOD_M 0x3U // Delta-Sigma Modulator mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDFPARM1 register
//
//*************************************************************************************************
#define SDFM_SDDFPARM1_DOSR_S 0U
#define SDFM_SDDFPARM1_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1
#define SDFM_SDDFPARM1_FEN 0x100U // Filter Enable
#define SDFM_SDDFPARM1_AE 0x200U // Ack Enable
#define SDFM_SDDFPARM1_SST_S 10U
#define SDFM_SDDFPARM1_SST_M 0xC00U // Data Filter Structure (DataFast/1/2/3)
#define SDFM_SDDFPARM1_SDSYNCEN 0x1000U // Data FILTER Reset Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDPARM1 register
//
//*************************************************************************************************
#define SDFM_SDDPARM1_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement)
#define SDFM_SDDPARM1_SH_S 11U
#define SDFM_SDDPARM1_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode)
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCMPH1 register
//
//*************************************************************************************************
#define SDFM_SDCMPH1_HLT_S 0U
#define SDFM_SDCMPH1_HLT_M 0x7FFFU // High-level threshold for the comparator filter output.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCMPL1 register
//
//*************************************************************************************************
#define SDFM_SDCMPL1_LLT_S 0U
#define SDFM_SDCMPL1_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCPARM1 register
//
//*************************************************************************************************
#define SDFM_SDCPARM1_COSR_S 0U
#define SDFM_SDCPARM1_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1
#define SDFM_SDCPARM1_IEH 0x20U // High-level interrupt enable
#define SDFM_SDCPARM1_IEL 0x40U // Low-level interrupt enable
#define SDFM_SDCPARM1_CS1_CS0_S 7U
#define SDFM_SDCPARM1_CS1_CS0_M 0x180U // Comparator filter structure
// (Sincfast/Sinc1/Sinc2/Sinc3
#define SDFM_SDCPARM1_MFIE 0x200U // Modulator Failure Interrupt enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATA1 register
//
//*************************************************************************************************
#define SDFM_SDDATA1_DATA16_S 0U
#define SDFM_SDDATA1_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b
// mode
#define SDFM_SDDATA1_DATA32HI_S 16U
#define SDFM_SDDATA1_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTLPARM2 register
//
//*************************************************************************************************
#define SDFM_SDCTLPARM2_MOD_S 0U
#define SDFM_SDCTLPARM2_MOD_M 0x3U // Delta-Sigma Modulator mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDFPARM2 register
//
//*************************************************************************************************
#define SDFM_SDDFPARM2_DOSR_S 0U
#define SDFM_SDDFPARM2_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1
#define SDFM_SDDFPARM2_FEN 0x100U // Filter Enable
#define SDFM_SDDFPARM2_AE 0x200U // Ack Enable
#define SDFM_SDDFPARM2_SST_S 10U
#define SDFM_SDDFPARM2_SST_M 0xC00U // Data Filter Structure (SincFast/1/2/3)
#define SDFM_SDDFPARM2_SDSYNCEN 0x1000U // Data FILTER Reset Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDPARM2 register
//
//*************************************************************************************************
#define SDFM_SDDPARM2_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement)
#define SDFM_SDDPARM2_SH_S 11U
#define SDFM_SDDPARM2_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode)
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCMPH2 register
//
//*************************************************************************************************
#define SDFM_SDCMPH2_HLT_S 0U
#define SDFM_SDCMPH2_HLT_M 0x7FFFU // High-level threshold for the comparator filter output.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCMPL2 register
//
//*************************************************************************************************
#define SDFM_SDCMPL2_LLT_S 0U
#define SDFM_SDCMPL2_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCPARM2 register
//
//*************************************************************************************************
#define SDFM_SDCPARM2_COSR_S 0U
#define SDFM_SDCPARM2_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1
#define SDFM_SDCPARM2_IEH 0x20U // High-level interrupt enable
#define SDFM_SDCPARM2_IEL 0x40U // Low-level interrupt enable
#define SDFM_SDCPARM2_CS1_CS0_S 7U
#define SDFM_SDCPARM2_CS1_CS0_M 0x180U // Comparator filter structure
// (Sincfast/Sinc1/Sinc2/Sinc3
#define SDFM_SDCPARM2_MFIE 0x200U // Modulator Failure Interrupt enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATA2 register
//
//*************************************************************************************************
#define SDFM_SDDATA2_DATA16_S 0U
#define SDFM_SDDATA2_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b
// mode
#define SDFM_SDDATA2_DATA32HI_S 16U
#define SDFM_SDDATA2_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTLPARM3 register
//
//*************************************************************************************************
#define SDFM_SDCTLPARM3_MOD_S 0U
#define SDFM_SDCTLPARM3_MOD_M 0x3U // Delta-Sigma Modulator mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDFPARM3 register
//
//*************************************************************************************************
#define SDFM_SDDFPARM3_DOSR_S 0U
#define SDFM_SDDFPARM3_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1
#define SDFM_SDDFPARM3_FEN 0x100U // Filter Enable
#define SDFM_SDDFPARM3_AE 0x200U // Ack Enable
#define SDFM_SDDFPARM3_SST_S 10U
#define SDFM_SDDFPARM3_SST_M 0xC00U // Data filter structure (SincFast/1/2/3)
#define SDFM_SDDFPARM3_SDSYNCEN 0x1000U // Data FILTER Reset Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDPARM3 register
//
//*************************************************************************************************
#define SDFM_SDDPARM3_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement)
#define SDFM_SDDPARM3_SH_S 11U
#define SDFM_SDDPARM3_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode)
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCMPH3 register
//
//*************************************************************************************************
#define SDFM_SDCMPH3_HLT_S 0U
#define SDFM_SDCMPH3_HLT_M 0x7FFFU // High-level threshold for the comparator filter output.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCMPL3 register
//
//*************************************************************************************************
#define SDFM_SDCMPL3_LLT_S 0U
#define SDFM_SDCMPL3_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCPARM3 register
//
//*************************************************************************************************
#define SDFM_SDCPARM3_COSR_S 0U
#define SDFM_SDCPARM3_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1
#define SDFM_SDCPARM3_IEH 0x20U // High-level interrupt enable
#define SDFM_SDCPARM3_IEL 0x40U // Low-level interrupt enable
#define SDFM_SDCPARM3_CS1_CS0_S 7U
#define SDFM_SDCPARM3_CS1_CS0_M 0x180U // Comparator filter structure
// (Sincfast/Sinc1/Sinc2/Sinc3
#define SDFM_SDCPARM3_MFIE 0x200U // Modulator Failure Interrupt enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATA3 register
//
//*************************************************************************************************
#define SDFM_SDDATA3_DATA16_S 0U
#define SDFM_SDDATA3_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b
// mode
#define SDFM_SDDATA3_DATA32HI_S 16U
#define SDFM_SDDATA3_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCTLPARM4 register
//
//*************************************************************************************************
#define SDFM_SDCTLPARM4_MOD_S 0U
#define SDFM_SDCTLPARM4_MOD_M 0x3U // Delta-Sigma Modulator mode
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDFPARM4 register
//
//*************************************************************************************************
#define SDFM_SDDFPARM4_DOSR_S 0U
#define SDFM_SDDFPARM4_DOSR_M 0xFFU // SINC Filter Oversample Ratio= DOSR+1
#define SDFM_SDDFPARM4_FEN 0x100U // Filter Enable
#define SDFM_SDDFPARM4_AE 0x200U // Ack Enable
#define SDFM_SDDFPARM4_SST_S 10U
#define SDFM_SDDFPARM4_SST_M 0xC00U // Data filter structure (SincFast/1/2/3)
#define SDFM_SDDFPARM4_SDSYNCEN 0x1000U // SINC FILTER Reset Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDPARM4 register
//
//*************************************************************************************************
#define SDFM_SDDPARM4_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement)
#define SDFM_SDDPARM4_SH_S 11U
#define SDFM_SDDPARM4_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode)
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCMPH4 register
//
//*************************************************************************************************
#define SDFM_SDCMPH4_HLT_S 0U
#define SDFM_SDCMPH4_HLT_M 0x7FFFU // High-level threshold for the comparator filter output.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCMPL4 register
//
//*************************************************************************************************
#define SDFM_SDCMPL4_LLT_S 0U
#define SDFM_SDCMPL4_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output.
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDCPARM4 register
//
//*************************************************************************************************
#define SDFM_SDCPARM4_COSR_S 0U
#define SDFM_SDCPARM4_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1
#define SDFM_SDCPARM4_IEH 0x20U // High-level interrupt enable
#define SDFM_SDCPARM4_IEL 0x40U // Low-level interrupt enable
#define SDFM_SDCPARM4_CS1_CS0_S 7U
#define SDFM_SDCPARM4_CS1_CS0_M 0x180U // Comparator filter structure
// (Sincfast/Sinc1/Sinc2/Sinc3
#define SDFM_SDCPARM4_MFIE 0x200U // Modulator Failure Interrupt enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the SDDATA4 register
//
//*************************************************************************************************
#define SDFM_SDDATA4_DATA16_S 0U
#define SDFM_SDDATA4_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b
// mode
#define SDFM_SDDATA4_DATA32HI_S 16U
#define SDFM_SDDATA4_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode
#endif
28379d_P_SFRA/device/driverlib/inc/hw_spi.h
+157
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//###########################################################################
//
// FILE: hw_spi.h
//
// TITLE: Definitions for the SPI registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_SPI_H
#define HW_SPI_H
//*************************************************************************************************
//
// The following are defines for the SPI register offsets
//
//*************************************************************************************************
#define SPI_O_CCR 0x0U // SPI Configuration Control Register
#define SPI_O_CTL 0x1U // SPI Operation Control Register
#define SPI_O_STS 0x2U // SPI Status Register
#define SPI_O_BRR 0x4U // SPI Baud Rate Register
#define SPI_O_RXEMU 0x6U // SPI Emulation Buffer Register
#define SPI_O_RXBUF 0x7U // SPI Serial Input Buffer Register
#define SPI_O_TXBUF 0x8U // SPI Serial Output Buffer Register
#define SPI_O_DAT 0x9U // SPI Serial Data Register
#define SPI_O_FFTX 0xAU // SPI FIFO Transmit Register
#define SPI_O_FFRX 0xBU // SPI FIFO Receive Register
#define SPI_O_FFCT 0xCU // SPI FIFO Control Register
#define SPI_O_PRI 0xFU // SPI Priority Control Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPICCR register
//
//*************************************************************************************************
#define SPI_CCR_SPICHAR_S 0U
#define SPI_CCR_SPICHAR_M 0xFU // Character Length Control
#define SPI_CCR_SPILBK 0x10U // SPI Loopback
#define SPI_CCR_HS_MODE 0x20U // High Speed mode control
#define SPI_CCR_CLKPOLARITY 0x40U // Shift Clock Polarity
#define SPI_CCR_SPISWRESET 0x80U // SPI Software Reset
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPICTL register
//
//*************************************************************************************************
#define SPI_CTL_SPIINTENA 0x1U // SPI Interupt Enable
#define SPI_CTL_TALK 0x2U // Master/Slave Transmit Enable
#define SPI_CTL_MASTER_SLAVE 0x4U // SPI Network Mode Control
#define SPI_CTL_CLK_PHASE 0x8U // SPI Clock Phase
#define SPI_CTL_OVERRUNINTENA 0x10U // Overrun Interrupt Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPISTS register
//
//*************************************************************************************************
#define SPI_STS_BUFFULL_FLAG 0x20U // SPI Transmit Buffer Full Flag
#define SPI_STS_INT_FLAG 0x40U // SPI Interrupt Flag
#define SPI_STS_OVERRUN_FLAG 0x80U // SPI Receiver Overrun Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIBRR register
//
//*************************************************************************************************
#define SPI_BRR_SPI_BIT_RATE_S 0U
#define SPI_BRR_SPI_BIT_RATE_M 0x7FU // SPI Bit Rate Control
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIFFTX register
//
//*************************************************************************************************
#define SPI_FFTX_TXFFIL_S 0U
#define SPI_FFTX_TXFFIL_M 0x1FU // TXFIFO Interrupt Level
#define SPI_FFTX_TXFFIENA 0x20U // TXFIFO Interrupt Enable
#define SPI_FFTX_TXFFINTCLR 0x40U // TXFIFO Interrupt Clear
#define SPI_FFTX_TXFFINT 0x80U // TXFIFO Interrupt Flag
#define SPI_FFTX_TXFFST_S 8U
#define SPI_FFTX_TXFFST_M 0x1F00U // Transmit FIFO Status
#define SPI_FFTX_TXFIFO 0x2000U // TXFIFO Reset
#define SPI_FFTX_SPIFFENA 0x4000U // FIFO Enhancements Enable
#define SPI_FFTX_SPIRST 0x8000U // SPI Reset
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIFFRX register
//
//*************************************************************************************************
#define SPI_FFRX_RXFFIL_S 0U
#define SPI_FFRX_RXFFIL_M 0x1FU // RXFIFO Interrupt Level
#define SPI_FFRX_RXFFIENA 0x20U // RXFIFO Interrupt Enable
#define SPI_FFRX_RXFFINTCLR 0x40U // RXFIFO Interupt Clear
#define SPI_FFRX_RXFFINT 0x80U // RXFIFO Interrupt Flag
#define SPI_FFRX_RXFFST_S 8U
#define SPI_FFRX_RXFFST_M 0x1F00U // Receive FIFO Status
#define SPI_FFRX_RXFIFORESET 0x2000U // RXFIFO Reset
#define SPI_FFRX_RXFFOVFCLR 0x4000U // Receive FIFO Overflow Clear
#define SPI_FFRX_RXFFOVF 0x8000U // Receive FIFO Overflow Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIFFCT register
//
//*************************************************************************************************
#define SPI_FFCT_TXDLY_S 0U
#define SPI_FFCT_TXDLY_M 0xFFU // FIFO Transmit Delay Bits
//*************************************************************************************************
//
// The following are defines for the bit fields in the SPIPRI register
//
//*************************************************************************************************
#define SPI_PRI_TRIWIRE 0x1U // 3-wire mode select bit
#define SPI_PRI_STEINV 0x2U // SPISTE inversion bit
#define SPI_PRI_FREE 0x10U // Free emulation mode
#define SPI_PRI_SOFT 0x20U // Soft emulation mode
#endif
28379d_P_SFRA/device/driverlib/inc/hw_sysctl.h
+1428
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28379d_P_SFRA/device/driverlib/inc/hw_types.h
+166
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//###########################################################################
//
// FILE: hw_types.h
//
// TITLE: Type definitions used in driverlib functions.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_TYPES_H
#define HW_TYPES_H
//*****************************************************************************
//
// Macros for hardware access
//
//*****************************************************************************
#if defined(__TMS320C28XX_CLA__)
#define HWREG(x) \
(*((volatile uint32_t *)((uintptr_t)(x))))
#define HWREGH(x) \
(*((volatile uint16_t *)((uintptr_t)(x))))
#else
#define HWREG(x) \
(*((volatile uint32_t *)(x)))
#define HWREGH(x) \
(*((volatile uint16_t *)(x)))
#endif
#define HWREG_BP(x) \
__byte_peripheral_32((uint32_t *)(x))
#define HWREGB(x) \
__byte((int16_t *)(x),0)
//*****************************************************************************
//
// SUCCESS and FAILURE for API return value
//
//*****************************************************************************
#define STATUS_S_SUCCESS (0)
#define STATUS_E_FAILURE (-1)
//*****************************************************************************
//
// Definition of 8 bit types for USB Driver code to maintain portability
// between byte and word addressable cores of C2000 Devices.
//
//*****************************************************************************
typedef uint16_t uint8_t;
typedef int16_t int8_t;
//****************************************************************************
//
// For checking NULL pointers
//
//****************************************************************************
#ifndef NULL
#define NULL ((void *)0x0)
#endif
//*****************************************************************************
//
// 32-bit & 64-bit float type
//
//*****************************************************************************
#ifndef C2000_IEEE754_TYPES
#define C2000_IEEE754_TYPES
#ifdef __TI_EABI__
typedef float float32_t;
typedef double float64_t;
#else // TI COFF
typedef float float32_t;
typedef long double float64_t;
#endif // __TI_EABI__
#endif // C2000_IEEE754_TYPES
//*****************************************************************************
//
// Emulated Bitbanded write
//
//*****************************************************************************
#define HWREGBITW(address, mask, value) \
(*(volatile uint32_t *)(address)) = \
((*(volatile uint32_t *)(address)) & ~((uint32_t)1 << mask)) \
| ((uint32_t)value << mask)
#define HWREGBITHW(address, mask, value) \
(*(volatile uint16_t *)(address)) = \
((*(volatile uint16_t *)(address)) & ~((uint16_t)1 << mask)) \
| ((uint16_t)value << mask)
//*****************************************************************************
//
// Emulated Bitbanded read
//
//*****************************************************************************
#define HWREGBITR(address, mask) \
(((*(volatile uint32_t *)(address)) & ((uint32_t)1 << mask)) >> mask)
#define HWREGBITHR(address, mask) \
(((*(volatile uint16_t *)(address)) & ((uint16_t)1 << mask)) >> mask)
//*****************************************************************************
//
// Extern compiler intrinsic prototypes. See compiler User's Guide for details.
// These are provided to satisfy static analysis tools. The #ifndef is required
// because the '&' is for a C++-style reference, and although it is the correct
// prototype, it will not build in C code.
//
//*****************************************************************************
#if(defined(__TMS320C28XX__) || defined(__TMS320C28XX_CLA__))
#else
extern int16_t &__byte(int16_t *array, uint16_t byte_index);
extern uint32_t &__byte_peripheral_32(uint32_t *x);
#endif
//
// C++ Bool Compatibility
//
#if defined(__cplusplus)
typedef bool _Bool;
#endif
/* To fix Misra-C errors */
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
#endif // HW_TYPES_H
28379d_P_SFRA/device/driverlib/inc/hw_upp.h
+306
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@@ -0,0 +1,306 @@
//###########################################################################
//
// FILE: hw_upp.h
//
// TITLE: Definitions for the UPP registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_UPP_H
#define HW_UPP_H
//*************************************************************************************************
//
// The following are defines for the UPP register offsets
//
//*************************************************************************************************
#define UPP_O_PID 0x0U // Peripheral ID Register
#define UPP_O_PERCTL 0x2U // Peripheral Control Register
#define UPP_O_CHCTL 0x8U // General Control Register
#define UPP_O_IFCFG 0xAU // Interface Configuration Register
#define UPP_O_IFIVAL 0xCU // Interface Idle Value Register
#define UPP_O_THCFG 0xEU // Threshold Configuration Register
#define UPP_O_RAWINTST 0x10U // Raw Interrupt Status Register
#define UPP_O_ENINTST 0x12U // Enable Interrupt Status Register
#define UPP_O_INTENSET 0x14U // Interrupt Enable Set Register
#define UPP_O_INTENCLR 0x16U // Interrupt Enable Clear Register
#define UPP_O_CHIDESC0 0x20U // DMA Channel I Descriptor 0 Register
#define UPP_O_CHIDESC1 0x22U // DMA Channel I Descriptor 1 Register
#define UPP_O_CHIDESC2 0x24U // DMA Channel I Descriptor 2 Register
#define UPP_O_CHIST0 0x28U // DMA Channel I Status 0 Register
#define UPP_O_CHIST1 0x2AU // DMA Channel I Status 1 Register
#define UPP_O_CHIST2 0x2CU // DMA Channel I Status 2 Register
#define UPP_O_CHQDESC0 0x30U // DMA Channel Q Descriptor 0 Register
#define UPP_O_CHQDESC1 0x32U // DMA Channel Q Descriptor 1 Register
#define UPP_O_CHQDESC2 0x34U // DMA Channel Q Descriptor 2 Register
#define UPP_O_CHQST0 0x38U // DMA Channel Q Status 0 Register
#define UPP_O_CHQST1 0x3AU // DMA Channel Q Status 1 Register
#define UPP_O_CHQST2 0x3CU // DMA Channel Q Status 2 Register
#define UPP_O_GINTEN 0x40U // Global Peripheral Interrupt Enable Register
#define UPP_O_GINTFLG 0x42U // Global Peripheral Interrupt Flag Register
#define UPP_O_GINTCLR 0x44U // Global Peripheral Interrupt Clear Register
#define UPP_O_DLYCTL 0x46U // IO clock data skew control Register
//*************************************************************************************************
//
// The following are defines for the bit fields in the PERCTL register
//
//*************************************************************************************************
#define UPP_PERCTL_FREE 0x1U // Emulation control.
#define UPP_PERCTL_SOFT 0x2U // Emulation control.
#define UPP_PERCTL_RTEMU 0x4U // Realtime emulation control.
#define UPP_PERCTL_PEREN 0x8U // Peripheral Enable
#define UPP_PERCTL_SOFTRST 0x10U // Software Reset
#define UPP_PERCTL_DMAST 0x80U // DMA Burst transaction status
//*************************************************************************************************
//
// The following are defines for the bit fields in the CHCTL register
//
//*************************************************************************************************
#define UPP_CHCTL_MODE_S 0U
#define UPP_CHCTL_MODE_M 0x3U // Operating mode
#define UPP_CHCTL_SDRTXILA 0x8U // SDR TX Interleve mode
#define UPP_CHCTL_DEMUXA 0x10U // DDR de-multiplexing mode
#define UPP_CHCTL_DRA 0x10000U // Data rate
//*************************************************************************************************
//
// The following are defines for the bit fields in the IFCFG register
//
//*************************************************************************************************
#define UPP_IFCFG_STARTPOLA 0x1U // Polarity of START(SELECT) signal
#define UPP_IFCFG_ENAPOLA 0x2U // Polarity of ENABLE(WRITE) signal
#define UPP_IFCFG_WAITPOLA 0x4U // Polarity of WAIT signal.
#define UPP_IFCFG_STARTA 0x8U // Enable Usage of START (SELECT) signal
#define UPP_IFCFG_ENAA 0x10U // Enable Usage of ENABLE (WRITE) signal
#define UPP_IFCFG_WAITA 0x20U // Enable Usage of WAIT signal
#define UPP_IFCFG_CLKDIVA_S 8U
#define UPP_IFCFG_CLKDIVA_M 0xF00U // Clock divider for tx mode
#define UPP_IFCFG_CLKINVA 0x1000U // Clock inversion
#define UPP_IFCFG_TRISENA 0x2000U // Pin Tri-state Control
//*************************************************************************************************
//
// The following are defines for the bit fields in the IFIVAL register
//
//*************************************************************************************************
#define UPP_IFIVAL_VALA_S 0U
#define UPP_IFIVAL_VALA_M 0x1FFU // Idle Value
//*************************************************************************************************
//
// The following are defines for the bit fields in the THCFG register
//
//*************************************************************************************************
#define UPP_THCFG_RDSIZEI_S 0U
#define UPP_THCFG_RDSIZEI_M 0x3U // DMA Read Threshold for DMA Channel I
#define UPP_THCFG_RDSIZEQ_S 8U
#define UPP_THCFG_RDSIZEQ_M 0x300U // DMA Read Threshold for DMA Channel Q
#define UPP_THCFG_TXSIZEA_S 16U
#define UPP_THCFG_TXSIZEA_M 0x30000U // I/O Transmit Threshold Value
//*************************************************************************************************
//
// The following are defines for the bit fields in the RAWINTST register
//
//*************************************************************************************************
#define UPP_RAWINTST_DPEI 0x1U // Interrupt raw status for DMA programming error
#define UPP_RAWINTST_UOEI 0x2U // Interrupt raw status for DMA under-run or over-run
#define UPP_RAWINTST_EOWI 0x8U // Interrupt raw status for end-of window condition
#define UPP_RAWINTST_EOLI 0x10U // Interrupt raw status for end-of-line condition
#define UPP_RAWINTST_DPEQ 0x100U // Interrupt raw status for DMA programming error
#define UPP_RAWINTST_UOEQ 0x200U // Interrupt raw status for DMA under-run or over-run
#define UPP_RAWINTST_EOWQ 0x800U // Interrupt raw status for end-of window condition
#define UPP_RAWINTST_EOLQ 0x1000U // Interrupt raw status for end-of-line condition
//*************************************************************************************************
//
// The following are defines for the bit fields in the ENINTST register
//
//*************************************************************************************************
#define UPP_ENINTST_DPEI 0x1U // Interrupt enable status for DMA programming error
#define UPP_ENINTST_UOEI 0x2U // Interrupt enable status for DMA under-run or over-run
#define UPP_ENINTST_EOWI 0x8U // Interrupt enable status for end-of window condition
#define UPP_ENINTST_EOLI 0x10U // Interrupt enable status for end-of-line condition
#define UPP_ENINTST_DPEQ 0x100U // Interrupt enable status for DMA programming error
#define UPP_ENINTST_UOEQ 0x200U // Interrupt enable status for DMA under-run or over-run
#define UPP_ENINTST_EOWQ 0x800U // Interrupt enable status for end-of window condition
#define UPP_ENINTST_EOLQ 0x1000U // Interrupt enable status for end-of-line condition
//*************************************************************************************************
//
// The following are defines for the bit fields in the INTENSET register
//
//*************************************************************************************************
#define UPP_INTENSET_DPEI 0x1U // Interrupt enable for DMA programming error
#define UPP_INTENSET_UOEI 0x2U // Interrupt enable for DMA under-run or over-run
#define UPP_INTENSET_EOWI 0x8U // Interrupt enable for end-of window condition
#define UPP_INTENSET_EOLI 0x10U // Interrupt enable for end-of-line condition
#define UPP_INTENSET_DPEQ 0x100U // Interrupt enable for DMA programming error
#define UPP_INTENSET_UOEQ 0x200U // Interrupt enable for DMA under-run or over-run
#define UPP_INTENSET_EOWQ 0x800U // Interrupt enable for end-of window condition
#define UPP_INTENSET_EOLQ 0x1000U // Interrupt enable for end-of-line condition
//*************************************************************************************************
//
// The following are defines for the bit fields in the INTENCLR register
//
//*************************************************************************************************
#define UPP_INTENCLR_DPEI 0x1U // Interrupt clear for DMA programming error
#define UPP_INTENCLR_UOEI 0x2U // Interrupt clear for DMA under-run or over-run
#define UPP_INTENCLR_EOWI 0x8U // Interrupt clear for end-of window condition
#define UPP_INTENCLR_EOLI 0x10U // Interrupt clear for end-of-line condition
#define UPP_INTENCLR_DPEQ 0x100U // Interrupt clear for DMA programming error
#define UPP_INTENCLR_UOEQ 0x200U // Interrupt clear for DMA under-run or over-run
#define UPP_INTENCLR_EOWQ 0x800U // Interrupt clear for end-of window condition
#define UPP_INTENCLR_EOLQ 0x1000U // Interrupt clear for end-of-line condition
//*************************************************************************************************
//
// The following are defines for the bit fields in the CHIDESC1 register
//
//*************************************************************************************************
#define UPP_CHIDESC1_BCNT_S 0U
#define UPP_CHIDESC1_BCNT_M 0xFFFFU // Number of bytes in a line for DMA Channel I
// transfer.
#define UPP_CHIDESC1_LCNT_S 16U
#define UPP_CHIDESC1_LCNT_M 0xFFFF0000U // Number of lines in a window for DMA Channel I
// transfer.
//*************************************************************************************************
//
// The following are defines for the bit fields in the CHIDESC2 register
//
//*************************************************************************************************
#define UPP_CHIDESC2_LOFFSET_S 0U
#define UPP_CHIDESC2_LOFFSET_M 0xFFFFU // Current start address to next start address offset.
//*************************************************************************************************
//
// The following are defines for the bit fields in the CHIST1 register
//
//*************************************************************************************************
#define UPP_CHIST1_BCNT_S 0U
#define UPP_CHIST1_BCNT_M 0xFFFFU // Current byte number.
#define UPP_CHIST1_LCNT_S 16U
#define UPP_CHIST1_LCNT_M 0xFFFF0000U // Current line number.
//*************************************************************************************************
//
// The following are defines for the bit fields in the CHIST2 register
//
//*************************************************************************************************
#define UPP_CHIST2_ACT 0x1U // Status of DMA descriptor.
#define UPP_CHIST2_PEND 0x2U // Status of DMA.
#define UPP_CHIST2_WM_S 4U
#define UPP_CHIST2_WM_M 0xF0U // Watermark for FIFO block count for DMA Channel I tranfer.
//*************************************************************************************************
//
// The following are defines for the bit fields in the CHQDESC1 register
//
//*************************************************************************************************
#define UPP_CHQDESC1_BCNT_S 0U
#define UPP_CHQDESC1_BCNT_M 0xFFFFU // Number of bytes in a line for DMA Channel Q
// transfer.
#define UPP_CHQDESC1_LCNT_S 16U
#define UPP_CHQDESC1_LCNT_M 0xFFFF0000U // Number of lines in a window for DMA Channel Q
// transfer.
//*************************************************************************************************
//
// The following are defines for the bit fields in the CHQDESC2 register
//
//*************************************************************************************************
#define UPP_CHQDESC2_LOFFSET_S 0U
#define UPP_CHQDESC2_LOFFSET_M 0xFFFFU // Current start address to next start address offset.
//*************************************************************************************************
//
// The following are defines for the bit fields in the CHQST1 register
//
//*************************************************************************************************
#define UPP_CHQST1_BCNT_S 0U
#define UPP_CHQST1_BCNT_M 0xFFFFU // Current byte number.
#define UPP_CHQST1_LCNT_S 16U
#define UPP_CHQST1_LCNT_M 0xFFFF0000U // Current line number.
//*************************************************************************************************
//
// The following are defines for the bit fields in the CHQST2 register
//
//*************************************************************************************************
#define UPP_CHQST2_ACT 0x1U // Status of DMA descriptor.
#define UPP_CHQST2_PEND 0x2U // Status of DMA.
#define UPP_CHQST2_WM_S 4U
#define UPP_CHQST2_WM_M 0xF0U // Watermark for FIFO block count for DMA Channel Q tranfer.
//*************************************************************************************************
//
// The following are defines for the bit fields in the GINTEN register
//
//*************************************************************************************************
#define UPP_GINTEN_GINTEN 0x1U // Global Interrupt Enable
//*************************************************************************************************
//
// The following are defines for the bit fields in the GINTFLG register
//
//*************************************************************************************************
#define UPP_GINTFLG_GINTFLG 0x1U // Global Interrupt Flag
//*************************************************************************************************
//
// The following are defines for the bit fields in the GINTCLR register
//
//*************************************************************************************************
#define UPP_GINTCLR_GINTCLR 0x1U // Global Interrupt Clear
//*************************************************************************************************
//
// The following are defines for the bit fields in the DLYCTL register
//
//*************************************************************************************************
#define UPP_DLYCTL_DLYDIS 0x1U // IO dealy control disable.
#define UPP_DLYCTL_DLYCTL_S 1U
#define UPP_DLYCTL_DLYCTL_M 0x6U // IO delay control.
#endif
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//###########################################################################
//
// FILE: hw_xbar.h
//
// TITLE: Definitions for the XBAR registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_XBAR_H
#define HW_XBAR_H
//*************************************************************************************************
//
// The following are defines for the XBAR register offsets
//
//*************************************************************************************************
#define XBAR_O_FLG1 0x0U // X-Bar Input Flag Register 1
#define XBAR_O_FLG2 0x2U // X-Bar Input Flag Register 2
#define XBAR_O_FLG3 0x4U // X-Bar Input Flag Register 3
#define XBAR_O_CLR1 0x8U // X-Bar Input Flag Clear Register 1
#define XBAR_O_CLR2 0xAU // X-Bar Input Flag Clear Register 2
#define XBAR_O_CLR3 0xCU // X-Bar Input Flag Clear Register 3
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARFLG1 register
//
//*************************************************************************************************
#define XBAR_FLG1_CMPSS1_CTRIPL 0x1U // Input Flag for CMPSS1.CTRIPL Signal
#define XBAR_FLG1_CMPSS1_CTRIPH 0x2U // Input Flag for CMPSS1.CTRIPH Signal
#define XBAR_FLG1_CMPSS2_CTRIPL 0x4U // Input Flag for CMPSS2.CTRIPL Signal
#define XBAR_FLG1_CMPSS2_CTRIPH 0x8U // Input Flag for CMPSS2.CTRIPH Signal
#define XBAR_FLG1_CMPSS3_CTRIPL 0x10U // Input Flag for CMPSS3.CTRIPL Signal
#define XBAR_FLG1_CMPSS3_CTRIPH 0x20U // Input Flag for CMPSS3.CTRIPH Signal
#define XBAR_FLG1_CMPSS4_CTRIPL 0x40U // Input Flag for CMPSS4.CTRIPL Signal
#define XBAR_FLG1_CMPSS4_CTRIPH 0x80U // Input Flag for CMPSS4.CTRIPH Signal
#define XBAR_FLG1_CMPSS5_CTRIPL 0x100U // Input Flag for CMPSS5.CTRIPL Signal
#define XBAR_FLG1_CMPSS5_CTRIPH 0x200U // Input Flag for CMPSS5.CTRIPH Signal
#define XBAR_FLG1_CMPSS6_CTRIPL 0x400U // Input Flag for CMPSS6.CTRIPL Signal
#define XBAR_FLG1_CMPSS6_CTRIPH 0x800U // Input Flag for CMPSS6.CTRIPH Signal
#define XBAR_FLG1_CMPSS7_CTRIPL 0x1000U // Input Flag for CMPSS7.CTRIPL Signal
#define XBAR_FLG1_CMPSS7_CTRIPH 0x2000U // Input Flag for CMPSS7.CTRIPH Signal
#define XBAR_FLG1_CMPSS8_CTRIPL 0x4000U // Input Flag for CMPSS8.CTRIPL Signal
#define XBAR_FLG1_CMPSS8_CTRIPH 0x8000U // Input Flag for CMPSS8.CTRIPH Signal
#define XBAR_FLG1_CMPSS1_CTRIPOUTL 0x10000U // Input Flag for CMPSS1.CTRIPOUTL Signal
#define XBAR_FLG1_CMPSS1_CTRIPOUTH 0x20000U // Input Flag for CMPSS1.CTRIPOUTH Signal
#define XBAR_FLG1_CMPSS2_CTRIPOUTL 0x40000U // Input Flag for CMPSS2.CTRIPOUTL Signal
#define XBAR_FLG1_CMPSS2_CTRIPOUTH 0x80000U // Input Flag for CMPSS2.CTRIPOUTH Signal
#define XBAR_FLG1_CMPSS3_CTRIPOUTL 0x100000U // Input Flag for CMPSS3.CTRIPOUTL Signal
#define XBAR_FLG1_CMPSS3_CTRIPOUTH 0x200000U // Input Flag for CMPSS3.CTRIPOUTH Signal
#define XBAR_FLG1_CMPSS4_CTRIPOUTL 0x400000U // Input Flag for CMPSS4.CTRIPOUTL Signal
#define XBAR_FLG1_CMPSS4_CTRIPOUTH 0x800000U // Input Flag for CMPSS4.CTRIPOUTH Signal
#define XBAR_FLG1_CMPSS5_CTRIPOUTL 0x1000000U // Input Flag for CMPSS5.CTRIPOUTL Signal
#define XBAR_FLG1_CMPSS5_CTRIPOUTH 0x2000000U // Input Flag for CMPSS5.CTRIPOUTH Signal
#define XBAR_FLG1_CMPSS6_CTRIPOUTL 0x4000000U // Input Flag for CMPSS6.CTRIPOUTL Signal
#define XBAR_FLG1_CMPSS6_CTRIPOUTH 0x8000000U // Input Flag for CMPSS6.CTRIPOUTH Signal
#define XBAR_FLG1_CMPSS7_CTRIPOUTL 0x10000000U // Input Flag for CMPSS7.CTRIPOUTL Signal
#define XBAR_FLG1_CMPSS7_CTRIPOUTH 0x20000000U // Input Flag for CMPSS7.CTRIPOUTH Signal
#define XBAR_FLG1_CMPSS8_CTRIPOUTL 0x40000000U // Input Flag for CMPSS8.CTRIPOUTL Signal
#define XBAR_FLG1_CMPSS8_CTRIPOUTH 0x80000000U // Input Flag for CMPSS8.CTRIPOUTH Signal
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARFLG2 register
//
//*************************************************************************************************
#define XBAR_FLG2_INPUT1 0x1U // Input Flag for INPUT1 Signal
#define XBAR_FLG2_INPUT2 0x2U // Input Flag for INPUT2 Signal
#define XBAR_FLG2_INPUT3 0x4U // Input Flag for INPUT3 Signal
#define XBAR_FLG2_INPUT4 0x8U // Input Flag for INPUT4 Signal
#define XBAR_FLG2_INPUT5 0x10U // Input Flag for INPUT5 Signal
#define XBAR_FLG2_INPUT6 0x20U // Input Flag for INPUT6 Signal
#define XBAR_FLG2_ADCSOCAO 0x40U // Input Flag for ADCSOCAO Signal
#define XBAR_FLG2_ADCSOCBO 0x80U // Input Flag for ADCSOCBO Signal
#define XBAR_FLG2_CLB1_OUT4 0x100U // Input Flag for CLB1_OUT4 Signal
#define XBAR_FLG2_CLB1_OUT5 0x200U // Input Flag for CLB1_OUT5 Signal
#define XBAR_FLG2_CLB2_OUT4 0x400U // Input Flag for CLB2_OUT4 Signal
#define XBAR_FLG2_CLB2_OUT5 0x800U // Input Flag for CLB2_OUT5 Signal
#define XBAR_FLG2_CLB3_OUT4 0x1000U // Input Flag for CLB3_OUT4 Signal
#define XBAR_FLG2_CLB3_OUT5 0x2000U // Input Flag for CLB3_OUT5 Signal
#define XBAR_FLG2_CLB4_OUT4 0x4000U // Input Flag for CLB4_OUT4 Signal
#define XBAR_FLG2_CLB4_OUT5 0x8000U // Input Flag for CLB4_OUT5 Signal
#define XBAR_FLG2_ECAP1_OUT 0x10000U // Input Flag for ECAP1.OUT Signal
#define XBAR_FLG2_ECAP2_OUT 0x20000U // Input Flag for ECAP2.OUT Signal
#define XBAR_FLG2_ECAP3_OUT 0x40000U // Input Flag for ECAP3.OUT Signal
#define XBAR_FLG2_ECAP4_OUT 0x80000U // Input Flag for ECAP4.OUT Signal
#define XBAR_FLG2_ECAP5_OUT 0x100000U // Input Flag for ECAP5.OUT Signal
#define XBAR_FLG2_ECAP6_OUT 0x200000U // Input Flag for ECAP6.OUT Signal
#define XBAR_FLG2_EXTSYNCOUT 0x400000U // Input Flag for EXTSYNCOUT Signal
#define XBAR_FLG2_ADCAEVT1 0x800000U // Input Flag for ADCAEVT1 Signal
#define XBAR_FLG2_ADCAEVT2 0x1000000U // Input Flag for ADCAEVT2 Signal
#define XBAR_FLG2_ADCAEVT3 0x2000000U // Input Flag for ADCAEVT3 Signal
#define XBAR_FLG2_ADCAEVT4 0x4000000U // Input Flag for ADCAEVT4 Signal
#define XBAR_FLG2_ADCBEVT1 0x8000000U // Input Flag for ADCBEVT1 Signal
#define XBAR_FLG2_ADCBEVT2 0x10000000U // Input Flag for ADCBEVT2 Signal
#define XBAR_FLG2_ADCBEVT3 0x20000000U // Input Flag for ADCBEVT3 Signal
#define XBAR_FLG2_ADCBEVT4 0x40000000U // Input Flag for ADCBEVT4 Signal
#define XBAR_FLG2_ADCCEVT1 0x80000000U // Input Flag for ADCCEVT1 Signal
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARFLG3 register
//
//*************************************************************************************************
#define XBAR_FLG3_ADCCEVT2 0x1U // Input Flag for ADCCEVT2 Signal
#define XBAR_FLG3_ADCCEVT3 0x2U // Input Flag for ADCCEVT3 Signal
#define XBAR_FLG3_ADCCEVT4 0x4U // Input Flag for ADCCEVT4 Signal
#define XBAR_FLG3_ADCDEVT1 0x8U // Input Flag for ADCDEVT1 Signal
#define XBAR_FLG3_ADCDEVT2 0x10U // Input Flag for ADCDEVT2 Signal
#define XBAR_FLG3_ADCDEVT3 0x20U // Input Flag for ADCDEVT3 Signal
#define XBAR_FLG3_ADCDEVT4 0x40U // Input Flag for ADCDEVT4 Signal
#define XBAR_FLG3_SD1FLT1_COMPL 0x80U // Input Flag for SD1FLT1.COMPL Signal
#define XBAR_FLG3_SD1FLT1_COMPH 0x100U // Input Flag for SD1FLT1.COMPH Signal
#define XBAR_FLG3_SD1FLT2_COMPL 0x200U // Input Flag for SD1FLT2.COMPL Signal
#define XBAR_FLG3_SD1FLT2_COMPH 0x400U // Input Flag for SD1FLT2.COMPH Signal
#define XBAR_FLG3_SD1FLT3_COMPL 0x800U // Input Flag for SD1FLT3.COMPL Signal
#define XBAR_FLG3_SD1FLT3_COMPH 0x1000U // Input Flag for SD1FLT3.COMPH Signal
#define XBAR_FLG3_SD1FLT4_COMPL 0x2000U // Input Flag for SD1FLT4.COMPL Signal
#define XBAR_FLG3_SD1FLT4_COMPH 0x4000U // Input Flag for SD1FLT4.COMPH Signal
#define XBAR_FLG3_SD2FLT1_COMPL 0x8000U // Input Flag for SD2FLT1.COMPL Signal
#define XBAR_FLG3_SD2FLT1_COMPH 0x10000U // Input Flag for SD2FLT1.COMPH Signal
#define XBAR_FLG3_SD2FLT2_COMPL 0x20000U // Input Flag for SD2FLT2.COMPL Signal
#define XBAR_FLG3_SD2FLT2_COMPH 0x40000U // Input Flag for SD2FLT2.COMPH Signal
#define XBAR_FLG3_SD2FLT3_COMPL 0x80000U // Input Flag for SD2FLT3.COMPL Signal
#define XBAR_FLG3_SD2FLT3_COMPH 0x100000U // Input Flag for SD2FLT3.COMPH Signal
#define XBAR_FLG3_SD2FLT4_COMPL 0x200000U // Input Flag for SD2FLT4.COMPL Signal
#define XBAR_FLG3_SD2FLT4_COMPH 0x400000U // Input Flag for SD2FLT4.COMPH Signal
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARCLR1 register
//
//*************************************************************************************************
#define XBAR_CLR1_CMPSS1_CTRIPL 0x1U // Input Flag Clear for CMPSS1.CTRIPL Signal
#define XBAR_CLR1_CMPSS1_CTRIPH 0x2U // Input Flag Clear for CMPSS1.CTRIPH Signal
#define XBAR_CLR1_CMPSS2_CTRIPL 0x4U // Input Flag Clear for CMPSS2.CTRIPL Signal
#define XBAR_CLR1_CMPSS2_CTRIPH 0x8U // Input Flag Clear for CMPSS2.CTRIPH Signal
#define XBAR_CLR1_CMPSS3_CTRIPL 0x10U // Input Flag Clear for CMPSS3.CTRIPL Signal
#define XBAR_CLR1_CMPSS3_CTRIPH 0x20U // Input Flag Clear for CMPSS3.CTRIPH Signal
#define XBAR_CLR1_CMPSS4_CTRIPL 0x40U // Input Flag Clear for CMPSS4.CTRIPL Signal
#define XBAR_CLR1_CMPSS4_CTRIPH 0x80U // Input Flag Clear for CMPSS4.CTRIPH Signal
#define XBAR_CLR1_CMPSS5_CTRIPL 0x100U // Input Flag Clear for CMPSS5.CTRIPL Signal
#define XBAR_CLR1_CMPSS5_CTRIPH 0x200U // Input Flag Clear for CMPSS5.CTRIPH Signal
#define XBAR_CLR1_CMPSS6_CTRIPL 0x400U // Input Flag Clear for CMPSS6.CTRIPL Signal
#define XBAR_CLR1_CMPSS6_CTRIPH 0x800U // Input Flag Clear for CMPSS6.CTRIPH Signal
#define XBAR_CLR1_CMPSS7_CTRIPL 0x1000U // Input Flag Clear for CMPSS7.CTRIPL Signal
#define XBAR_CLR1_CMPSS7_CTRIPH 0x2000U // Input Flag Clear for CMPSS7.CTRIPH Signal
#define XBAR_CLR1_CMPSS8_CTRIPL 0x4000U // Input Flag Clear for CMPSS8.CTRIPL Signal
#define XBAR_CLR1_CMPSS8_CTRIPH 0x8000U // Input Flag Clear for CMPSS8.CTRIPH Signal
#define XBAR_CLR1_CMPSS1_CTRIPOUTL 0x10000U // Input Flag Clear for CMPSS1.CTRIPOUTL Signal
#define XBAR_CLR1_CMPSS1_CTRIPOUTH 0x20000U // Input Flag Clear for CMPSS1.CTRIPOUTH Signal
#define XBAR_CLR1_CMPSS2_CTRIPOUTL 0x40000U // Input Flag Clear for CMPSS2.CTRIPOUTL Signal
#define XBAR_CLR1_CMPSS2_CTRIPOUTH 0x80000U // Input Flag Clear for CMPSS2.CTRIPOUTH Signal
#define XBAR_CLR1_CMPSS3_CTRIPOUTL 0x100000U // Input Flag Clear for CMPSS3.CTRIPOUTL Signal
#define XBAR_CLR1_CMPSS3_CTRIPOUTH 0x200000U // Input Flag Clear for CMPSS3.CTRIPOUTH Signal
#define XBAR_CLR1_CMPSS4_CTRIPOUTL 0x400000U // Input Flag Clear for CMPSS4.CTRIPOUTL Signal
#define XBAR_CLR1_CMPSS4_CTRIPOUTH 0x800000U // Input Flag Clear for CMPSS4.CTRIPOUTH Signal
#define XBAR_CLR1_CMPSS5_CTRIPOUTL 0x1000000U // Input Flag Clear for CMPSS5.CTRIPOUTL Signal
#define XBAR_CLR1_CMPSS5_CTRIPOUTH 0x2000000U // Input Flag Clear for CMPSS5.CTRIPOUTH Signal
#define XBAR_CLR1_CMPSS6_CTRIPOUTL 0x4000000U // Input Flag Clear for CMPSS6.CTRIPOUTL Signal
#define XBAR_CLR1_CMPSS6_CTRIPOUTH 0x8000000U // Input Flag Clear for CMPSS6.CTRIPOUTH Signal
#define XBAR_CLR1_CMPSS7_CTRIPOUTL 0x10000000U // Input Flag Clear for CMPSS7.CTRIPOUTL Signal
#define XBAR_CLR1_CMPSS7_CTRIPOUTH 0x20000000U // Input Flag Clear for CMPSS7.CTRIPOUTH Signal
#define XBAR_CLR1_CMPSS8_CTRIPOUTL 0x40000000U // Input Flag Clear for CMPSS8.CTRIPOUTL Signal
#define XBAR_CLR1_CMPSS8_CTRIPOUTH 0x80000000U // Input Flag Clear for CMPSS8.CTRIPOUTH Signal
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARCLR2 register
//
//*************************************************************************************************
#define XBAR_CLR2_INPUT1 0x1U // Input Flag Clear for INPUT1 Signal
#define XBAR_CLR2_INPUT2 0x2U // Input Flag Clear for INPUT2 Signal
#define XBAR_CLR2_INPUT3 0x4U // Input Flag Clear for INPUT3 Signal
#define XBAR_CLR2_INPUT4 0x8U // Input Flag Clear for INPUT4 Signal
#define XBAR_CLR2_INPUT5 0x10U // Input Flag Clear for INPUT5 Signal
#define XBAR_CLR2_INPUT7 0x20U // Input Flag Clear for INPUT7 Signal
#define XBAR_CLR2_ADCSOCAO 0x40U // Input Flag Clear for ADCSOCAO Signal
#define XBAR_CLR2_ADCSOCBO 0x80U // Input Flag Clear for ADCSOCBO Signal
#define XBAR_CLR2_CLB1_OUT4 0x100U // Input Flag Clear for CLB1_OUT4 Signal
#define XBAR_CLR2_CLB1_OUT5 0x200U // Input Flag Clear for CLB1_OUT5 Signal
#define XBAR_CLR2_CLB2_OUT4 0x400U // Input Flag Clear for CLB2_OUT4 Signal
#define XBAR_CLR2_CLB2_OUT5 0x800U // Input Flag Clear for CLB2_OUT5 Signal
#define XBAR_CLR2_CLB3_OUT4 0x1000U // Input Flag Clear for CLB3_OUT4 Signal
#define XBAR_CLR2_CLB3_OUT5 0x2000U // Input Flag Clear for CLB3_OUT5 Signal
#define XBAR_CLR2_CLB4_OUT4 0x4000U // Input Flag Clear for CLB4_OUT4 Signal
#define XBAR_CLR2_CLB4_OUT5 0x8000U // Input Flag Clear for CLB4_OUT5 Signal
#define XBAR_CLR2_ECAP1_OUT 0x10000U // Input Flag Clear for ECAP1.OUT Signal
#define XBAR_CLR2_ECAP2_OUT 0x20000U // Input Flag Clear for ECAP2.OUT Signal
#define XBAR_CLR2_ECAP3_OUT 0x40000U // Input Flag Clear for ECAP3.OUT Signal
#define XBAR_CLR2_ECAP4_OUT 0x80000U // Input Flag Clear for ECAP4.OUT Signal
#define XBAR_CLR2_ECAP5_OUT 0x100000U // Input Flag Clear for ECAP5.OUT Signal
#define XBAR_CLR2_ECAP6_OUT 0x200000U // Input Flag Clear for ECAP6.OUT Signal
#define XBAR_CLR2_EXTSYNCOUT 0x400000U // Input Flag Clear for EXTSYNCOUT Signal
#define XBAR_CLR2_ADCAEVT1 0x800000U // Input Flag Clear for ADCAEVT1 Signal
#define XBAR_CLR2_ADCAEVT2 0x1000000U // Input Flag Clear for ADCAEVT2 Signal
#define XBAR_CLR2_ADCAEVT3 0x2000000U // Input Flag Clear for ADCAEVT3 Signal
#define XBAR_CLR2_ADCAEVT4 0x4000000U // Input Flag Clear for ADCAEVT4 Signal
#define XBAR_CLR2_ADCBEVT1 0x8000000U // Input Flag Clear for ADCBEVT1 Signal
#define XBAR_CLR2_ADCBEVT2 0x10000000U // Input Flag Clear for ADCBEVT2 Signal
#define XBAR_CLR2_ADCBEVT3 0x20000000U // Input Flag Clear for ADCBEVT3 Signal
#define XBAR_CLR2_ADCBEVT4 0x40000000U // Input Flag Clear for ADCBEVT4 Signal
#define XBAR_CLR2_ADCCEVT1 0x80000000U // Input Flag Clear for ADCCEVT1 Signal
//*************************************************************************************************
//
// The following are defines for the bit fields in the XBARCLR3 register
//
//*************************************************************************************************
#define XBAR_CLR3_ADCCEVT2 0x1U // Input Flag Clear for ADCCEVT2 Signal
#define XBAR_CLR3_ADCCEVT3 0x2U // Input Flag Clear for ADCCEVT3 Signal
#define XBAR_CLR3_ADCCEVT4 0x4U // Input Flag Clear for ADCCEVT4 Signal
#define XBAR_CLR3_ADCDEVT1 0x8U // Input Flag Clear for ADCDEVT1 Signal
#define XBAR_CLR3_ADCDEVT2 0x10U // Input Flag Clear for ADCDEVT2 Signal
#define XBAR_CLR3_ADCDEVT3 0x20U // Input Flag Clear for ADCDEVT3 Signal
#define XBAR_CLR3_ADCDEVT4 0x40U // Input Flag Clear for ADCDEVT4 Signal
#define XBAR_CLR3_SD1FLT1_COMPL 0x80U // Input Flag Clear for SD1FLT1.COMPL Signal
#define XBAR_CLR3_SD1FLT1_COMPH 0x100U // Input Flag Clear for SD1FLT1.COMPH Signal
#define XBAR_CLR3_SD1FLT2_COMPL 0x200U // Input Flag Clear for SD1FLT2.COMPL Signal
#define XBAR_CLR3_SD1FLT2_COMPH 0x400U // Input Flag Clear for SD1FLT2.COMPH Signal
#define XBAR_CLR3_SD1FLT3_COMPL 0x800U // Input Flag Clear for SD1FLT3.COMPL Signal
#define XBAR_CLR3_SD1FLT3_COMPH 0x1000U // Input Flag Clear for SD1FLT3.COMPH Signal
#define XBAR_CLR3_SD1FLT4_COMPL 0x2000U // Input Flag Clear for SD1FLT4.COMPL Signal
#define XBAR_CLR3_SD1FLT4_COMPH 0x4000U // Input Flag Clear for SD1FLT4.COMPH Signal
#define XBAR_CLR3_SD2FLT1_COMPL 0x8000U // Input Flag Clear for SD2FLT1.COMPL Signal
#define XBAR_CLR3_SD2FLT1_COMPH 0x10000U // Input Flag Clear for SD2FLT1.COMPH Signal
#define XBAR_CLR3_SD2FLT2_COMPL 0x20000U // Input Flag Clear for SD2FLT2.COMPL Signal
#define XBAR_CLR3_SD2FLT2_COMPH 0x40000U // Input Flag Clear for SD2FLT2.COMPH Signal
#define XBAR_CLR3_SD2FLT3_COMPL 0x80000U // Input Flag Clear for SD2FLT3.COMPL Signal
#define XBAR_CLR3_SD2FLT3_COMPH 0x100000U // Input Flag Clear for SD2FLT3.COMPH Signal
#define XBAR_CLR3_SD2FLT4_COMPL 0x200000U // Input Flag Clear for SD2FLT4.COMPL Signal
#define XBAR_CLR3_SD2FLT4_COMPH 0x400000U // Input Flag Clear for SD2FLT4.COMPH Signal
#endif
28379d_P_SFRA/device/driverlib/inc/hw_xint.h
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//###########################################################################
//
// FILE: hw_xint.h
//
// TITLE: Definitions for the XINT registers.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef HW_XINT_H
#define HW_XINT_H
//*************************************************************************************************
//
// The following are defines for the XINT register offsets
//
//*************************************************************************************************
#define XINT_O_1CR 0x0U // XINT1 configuration register
#define XINT_O_2CR 0x1U // XINT2 configuration register
#define XINT_O_3CR 0x2U // XINT3 configuration register
#define XINT_O_4CR 0x3U // XINT4 configuration register
#define XINT_O_5CR 0x4U // XINT5 configuration register
#define XINT_O_1CTR 0x8U // XINT1 counter register
#define XINT_O_2CTR 0x9U // XINT2 counter register
#define XINT_O_3CTR 0xAU // XINT3 counter register
//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT1CR register
//
//*************************************************************************************************
#define XINT_1CR_ENABLE 0x1U // XINT1 Enable
#define XINT_1CR_POLARITY_S 2U
#define XINT_1CR_POLARITY_M 0xCU // XINT1 Polarity
//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT2CR register
//
//*************************************************************************************************
#define XINT_2CR_ENABLE 0x1U // XINT2 Enable
#define XINT_2CR_POLARITY_S 2U
#define XINT_2CR_POLARITY_M 0xCU // XINT2 Polarity
//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT3CR register
//
//*************************************************************************************************
#define XINT_3CR_ENABLE 0x1U // XINT3 Enable
#define XINT_3CR_POLARITY_S 2U
#define XINT_3CR_POLARITY_M 0xCU // XINT3 Polarity
//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT4CR register
//
//*************************************************************************************************
#define XINT_4CR_ENABLE 0x1U // XINT4 Enable
#define XINT_4CR_POLARITY_S 2U
#define XINT_4CR_POLARITY_M 0xCU // XINT4 Polarity
//*************************************************************************************************
//
// The following are defines for the bit fields in the XINT5CR register
//
//*************************************************************************************************
#define XINT_5CR_ENABLE 0x1U // XINT5 Enable
#define XINT_5CR_POLARITY_S 2U
#define XINT_5CR_POLARITY_M 0xCU // XINT5 Polarity
#endif
28379d_P_SFRA/device/driverlib/interrupt.c
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//###########################################################################
//
// FILE: interrupt.c
//
// TITLE: C28x Interrupt (PIE) driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "interrupt.h"
//*****************************************************************************
//
//! \internal
//! Clears the IFR flag in the CPU.
//!
//! \param group specifies the interrupt group to be cleared.
//!
//! This function clears the IFR flag. This switch is needed because the
//! clearing of the IFR can only be done with a constant.
//
//*****************************************************************************
static void Interrupt_clearIFR(uint16_t group)
{
switch(group)
{
case 0x0001U:
IFR &= ~(uint16_t)0x0001U;
break;
case 0x0002U:
IFR &= ~(uint16_t)0x0002U;
break;
case 0x0004U:
IFR &= ~(uint16_t)0x0004U;
break;
case 0x0008U:
IFR &= ~(uint16_t)0x0008U;
break;
case 0x0010U:
IFR &= ~(uint16_t)0x0010U;
break;
case 0x0020U:
IFR &= ~(uint16_t)0x0020U;
break;
case 0x0040U:
IFR &= ~(uint16_t)0x0040U;
break;
case 0x0080U:
IFR &= ~(uint16_t)0x0080U;
break;
case 0x0100U:
IFR &= ~(uint16_t)0x0100U;
break;
case 0x0200U:
IFR &= ~(uint16_t)0x0200U;
break;
case 0x0400U:
IFR &= ~(uint16_t)0x0400U;
break;
case 0x0800U:
IFR &= ~(uint16_t)0x0800U;
break;
case 0x1000U:
IFR &= ~(uint16_t)0x1000U;
break;
case 0x2000U:
IFR &= ~(uint16_t)0x2000U;
break;
case 0x4000U:
IFR &= ~(uint16_t)0x4000U;
break;
case 0x8000U:
IFR &= ~(uint16_t)0x8000U;
break;
default:
//
// Invalid group mask.
//
ASSERT((bool)false);
break;
}
}
//*****************************************************************************
//
// Interrupt_initModule
//
//*****************************************************************************
void
Interrupt_initModule(void)
{
//
// Disable and clear all interrupts at the CPU
//
(void)Interrupt_disableGlobal();
IER = 0x0000U;
IFR = 0x0000U;
//
// Clear all PIEIER registers
//
HWREGH(PIECTRL_BASE + PIE_O_IER1) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IER2) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IER3) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IER4) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IER5) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IER6) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IER7) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IER8) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IER9) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IER10) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IER11) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IER12) = 0U;
//
// Clear all PIEIFR registers
//
HWREGH(PIECTRL_BASE + PIE_O_IFR1) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IFR2) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IFR3) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IFR4) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IFR5) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IFR6) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IFR7) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IFR8) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IFR9) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IFR10) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IFR11) = 0U;
HWREGH(PIECTRL_BASE + PIE_O_IFR12) = 0U;
//
// Enable vector fetching from PIE block
//
HWREGH(PIECTRL_BASE + PIE_O_CTRL) |= PIE_CTRL_ENPIE;
}
//*****************************************************************************
//
//! The default interrupt handler.
//!
//! \return None.
//
//*****************************************************************************
__interrupt void Interrupt_defaultHandler(void)
{
uint16_t pieVect;
uint16_t vectID;
//
// Calculate the vector ID. If the vector is in the lower PIE, it's the
// offset of the vector that was fetched (bits 7:1 of PIECTRL.PIEVECT)
// divided by two.
//
pieVect = HWREGH(PIECTRL_BASE + PIE_O_CTRL);
vectID = (pieVect & 0xFEU) >> 1U;
//
// If the vector is in the upper PIE, the vector ID is 128 or higher.
//
if(pieVect >= 0x0E00U)
{
vectID += 128U;
}
//
// Something has gone wrong. An interrupt without a proper registered
// handler function has occurred. To help you debug the issue, local
// variable vectID contains the vector ID of the interrupt that occurred.
//
ESTOP0;
for(;;)
{
;
}
}
//*****************************************************************************
//
//! The default illegal instruction trap interrupt handler.
//!
//! \return None.
//
//*****************************************************************************
__interrupt void Interrupt_illegalOperationHandler(void)
{
//
// Something has gone wrong. The CPU has tried to execute an illegal
// instruction, generating an illegal instruction trap (ITRAP).
//
ESTOP0;
for(;;)
{
;
}
}
//*****************************************************************************
//
//! The default non-maskable interrupt handler.
//!
//! \return None.
//
//*****************************************************************************
__interrupt void Interrupt_nmiHandler(void)
{
//
// A non-maskable interrupt has occurred, indicating that a hardware error
// has occurred in the system. You can use SysCtl_getNMIFlagStatus() to
// to read the NMIFLG register and determine what caused the NMI.
//
ESTOP0;
for(;;)
{
;
}
}
//*****************************************************************************
//
// Interrupt_initVectorTable
//
//*****************************************************************************
void
Interrupt_initVectorTable(void)
{
uint16_t i;
EALLOW;
//
// We skip the first three locations because they are initialized by Boot
// ROM with boot variables.
//
for(i = 3U; i < 224U; i++)
{
HWREG(PIEVECTTABLE_BASE + (2U * i)) =
(uint32_t)Interrupt_defaultHandler;
}
//
// NMI and ITRAP get their own handlers.
//
HWREG(PIEVECTTABLE_BASE + ((INT_NMI >> 16U) * 2U)) =
(uint32_t)Interrupt_nmiHandler;
HWREG(PIEVECTTABLE_BASE + ((INT_ILLEGAL >> 16U) * 2U)) =
(uint32_t)Interrupt_illegalOperationHandler;
EDIS;
}
//*****************************************************************************
//
//Interrupt_enable
//
//*****************************************************************************
void
Interrupt_enable(uint32_t interruptNumber)
{
bool intsDisabled;
uint16_t intGroup;
uint16_t groupMask;
uint16_t vectID;
vectID = (uint16_t)(interruptNumber >> 16U);
//
// Globally disable interrupts but save status
//
intsDisabled = Interrupt_disableGlobal();
//
// PIE Interrupts
//
if(vectID >= 0x20U)
{
intGroup = (uint16_t)(((interruptNumber & 0xFF00UL) >> 8U) - 1U);
groupMask = (uint16_t)1U << intGroup;
HWREGH((PIECTRL_BASE + PIE_O_IER1 + (intGroup * 2U))) |=
(uint16_t)1U << ((interruptNumber & 0xFFU) - 1U);
//
// Enable PIE Group Interrupt
//
IER |= groupMask;
}
//
// INT13, INT14, DLOGINT, & RTOSINT
//
else if((vectID >= 0x0DU) && (vectID <= 0x10U))
{
IER |= (uint16_t)1U << (vectID - 1U);
}
else
{
//
// Other interrupts
//
}
//
// Re-enable interrupts if they were enabled
//
if(!intsDisabled)
{
(void)Interrupt_enableGlobal();
}
}
//*****************************************************************************
//
// Interrupt_disable
//
//*****************************************************************************
void
Interrupt_disable(uint32_t interruptNumber)
{
bool intsDisabled;
uint16_t intGroup;
uint16_t groupMask;
uint16_t vectID;
vectID = (uint16_t)(interruptNumber >> 16U);
intsDisabled = Interrupt_disableGlobal();
//
// PIE Interrupts
//
if(vectID >= 0x20U)
{
intGroup = (uint16_t)(((interruptNumber & 0xFF00UL) >> 8U) - 1U);
groupMask = (uint16_t)1U << intGroup;
//
// Disable individual PIE interrupt
//
HWREGH((PIECTRL_BASE + PIE_O_IER1 + (intGroup * 2U))) &=
~(1U << ((interruptNumber & 0xFFUL) - 1U));
//
// Wait for any pending interrupts to get to the CPU
//
NOP;
NOP;
NOP;
NOP;
NOP;
Interrupt_clearIFR(groupMask);
//
// Acknowledge any interrupts
//
HWREGH(PIECTRL_BASE + PIE_O_ACK) = groupMask;
}
//
// INT13, INT14, DLOGINT, & RTOSINT
//
else if((vectID >= 0x0DU) && (vectID <= 0x10U))
{
IER &= ~((uint16_t)1U << (vectID - 1U));
//
// Wait for any pending interrupts to get to the CPU
//
NOP;
NOP;
NOP;
NOP;
NOP;
Interrupt_clearIFR((uint16_t)1U << (vectID - 1U));
}
else
{
//
// Other interrupts
//
}
//
// Re-enable interrupts if they were enabled
//
if(!intsDisabled)
{
(void)Interrupt_enableGlobal();
}
}
28379d_P_SFRA/device/driverlib/interrupt.h
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//###########################################################################
//
// FILE: interrupt.h
//
// TITLE: C28x Interrupt (PIE) driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef INTERRUPT_H
#define INTERRUPT_H
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
#ifdef __TMS320C28XX__
//*****************************************************************************
//
//! \addtogroup interrupt_api Interrupt
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "inc/hw_ints.h"
#include "inc/hw_memmap.h"
#include "inc/hw_pie.h"
#include "inc/hw_types.h"
#include "cpu.h"
#include "debug.h"
#ifndef DOXYGEN_PDF_IGNORE
//*****************************************************************************
//
// The following are values that can be passed to the Interrupt_enableInCPU()
// and Interrupt_disableInCPU() functions as the cpuInterrupt parameter.
//
//*****************************************************************************
#define INTERRUPT_CPU_INT1 0x1U //!< CPU Interrupt Number 1
#define INTERRUPT_CPU_INT2 0x2U //!< CPU Interrupt Number 2
#define INTERRUPT_CPU_INT3 0x4U //!< CPU Interrupt Number 3
#define INTERRUPT_CPU_INT4 0x8U //!< CPU Interrupt Number 4
#define INTERRUPT_CPU_INT5 0x10U //!< CPU Interrupt Number 5
#define INTERRUPT_CPU_INT6 0x20U //!< CPU Interrupt Number 6
#define INTERRUPT_CPU_INT7 0x40U //!< CPU Interrupt Number 7
#define INTERRUPT_CPU_INT8 0x80U //!< CPU Interrupt Number 8
#define INTERRUPT_CPU_INT9 0x100U //!< CPU Interrupt Number 9
#define INTERRUPT_CPU_INT10 0x200U //!< CPU Interrupt Number 10
#define INTERRUPT_CPU_INT11 0x400U //!< CPU Interrupt Number 11
#define INTERRUPT_CPU_INT12 0x800U //!< CPU Interrupt Number 12
#define INTERRUPT_CPU_INT13 0x1000U //!< CPU Interrupt Number 13
#define INTERRUPT_CPU_INT14 0x2000U //!< CPU Interrupt Number 14
#define INTERRUPT_CPU_DLOGINT 0x4000U //!< CPU Data Log Interrupt
#define INTERRUPT_CPU_RTOSINT 0x8000U //!< CPU RTOS Interrupt
//*****************************************************************************
//
// The following are values that can be passed to the Interrupt_clearACKGroup()
// function as the group parameter.
//
//*****************************************************************************
#define INTERRUPT_ACK_GROUP1 0x1U //!< Acknowledge PIE Interrupt Group 1
#define INTERRUPT_ACK_GROUP2 0x2U //!< Acknowledge PIE Interrupt Group 2
#define INTERRUPT_ACK_GROUP3 0x4U //!< Acknowledge PIE Interrupt Group 3
#define INTERRUPT_ACK_GROUP4 0x8U //!< Acknowledge PIE Interrupt Group 4
#define INTERRUPT_ACK_GROUP5 0x10U //!< Acknowledge PIE Interrupt Group 5
#define INTERRUPT_ACK_GROUP6 0x20U //!< Acknowledge PIE Interrupt Group 6
#define INTERRUPT_ACK_GROUP7 0x40U //!< Acknowledge PIE Interrupt Group 7
#define INTERRUPT_ACK_GROUP8 0x80U //!< Acknowledge PIE Interrupt Group 8
#define INTERRUPT_ACK_GROUP9 0x100U //!< Acknowledge PIE Interrupt Group 9
#define INTERRUPT_ACK_GROUP10 0x200U //!< Acknowledge PIE Interrupt Group 10
#define INTERRUPT_ACK_GROUP11 0x400U //!< Acknowledge PIE Interrupt Group 11
#define INTERRUPT_ACK_GROUP12 0x800U //!< Acknowledge PIE Interrupt Group 12
#endif
//*****************************************************************************
//
// Prototypes for the APIs.
//
//*****************************************************************************
//*****************************************************************************
//
//! \internal
//! The default interrupt handler.
//!
//! This is the default interrupt handler. The Interrupt_initVectorTable()
//! function sets all vectors to this function. Also, when an interrupt is
//! unregistered using the Interrupt_unregister() function, this handler takes
//! its place. This should never be called during normal operation.
//!
//! The ESTOP0 statement is for debug purposes only. Remove and replace with an
//! appropriate error handling routine for your program.
//!
//! \return None.
//
//*****************************************************************************
extern void
Interrupt_defaultHandler(void);
//*****************************************************************************
//
//! \internal
//! The default illegal instruction trap interrupt handler.
//!
//! This is the default interrupt handler for an illegal instruction trap
//! (ITRAP). The Interrupt_initVectorTable() function sets the appropriate
//! vector to this function. This should never be called during normal
//! operation.
//!
//! The ESTOP0 statement is for debug purposes only. Remove and replace with
//! an appropriate error handling routine for your program.
//!
//! \return None.
//
//*****************************************************************************
extern void
Interrupt_illegalOperationHandler(void);
//*****************************************************************************
//
//! \internal
//! The default non-maskable interrupt handler.
//!
//! This is the default interrupt handler for a non-maskable interrupt (NMI).
//! The Interrupt_initVectorTable() function sets the appropriate vector to
//! this function. This should never be called during normal operation.
//!
//! The ESTOP0 statement is for debug purposes only. Remove and replace with an
//! appropriate error handling routine for your program.
//!
//! \return None.
//
//*****************************************************************************
extern void
Interrupt_nmiHandler(void);
//*****************************************************************************
//
//! Allows the CPU to process interrupts.
//!
//! This function clears the global interrupt mask bit (INTM) in the CPU,
//! allowing the processor to respond to interrupts.
//!
//! \return Returns \b true if interrupts were disabled when the function was
//! called or \b false if they were initially enabled.
//
//*****************************************************************************
static inline bool
Interrupt_enableGlobal(void)
{
//
// Enable processor interrupts.
//
return(((__enable_interrupts() & 0x1U) != 0U) ? true : false);
}
//*****************************************************************************
//
//! Stops the CPU from processing interrupts.
//!
//! This function sets the global interrupt mask bit (INTM) in the CPU,
//! preventing the processor from receiving maskable interrupts.
//!
//! \return Returns \b true if interrupts were already disabled when the
//! function was called or \b false if they were initially enabled.
//
//*****************************************************************************
static inline bool
Interrupt_disableGlobal(void)
{
//
// Disable processor interrupts.
//
return(((__disable_interrupts() & 0x1U) != 0U) ? true : false);
}
//*****************************************************************************
//
//! Registers a function to be called when an interrupt occurs.
//!
//! \param interruptNumber specifies the interrupt in question.
//! \param handler is a pointer to the function to be called.
//!
//! This function is used to specify the handler function to be called when the
//! given interrupt is asserted to the processor. When the interrupt occurs,
//! if it is enabled (via Interrupt_enable()), the handler function will be
//! called in interrupt context. Since the handler function can preempt other
//! code, care must be taken to protect memory or peripherals that are accessed
//! by the handler and other non-handler code.
//!
//! The available \e interruptNumber values are supplied in
//! <tt>inc/hw_ints.h</tt>.
//!
//! \note This function assumes that the PIE has been enabled. See
//! Interrupt_initModule().
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_register(uint32_t interruptNumber, void (*handler)(void))
{
uint32_t address;
//
// Calculate appropriate address for the interrupt number
//
address = (uint32_t)PIEVECTTABLE_BASE +
(((interruptNumber & 0xFFFF0000U) >> 16U) * 2U);
//
// Copy ISR address into PIE table
//
EALLOW;
HWREG(address) = (uint32_t)handler;
EDIS;
}
//*****************************************************************************
//
//! Unregisters the function to be called when an interrupt occurs.
//!
//! \param interruptNumber specifies the interrupt in question.
//!
//! This function is used to indicate that a default handler
//! Interrupt_defaultHandler() should be called when the given interrupt is
//! asserted to the processor. Call Interrupt_disable() to disable
//! the interrupt before calling this function.
//!
//! The available \e interruptNumber values are supplied in
//! <tt>inc/hw_ints.h</tt>.
//!
//! \sa Interrupt_register() for important information about registering
//! interrupt handlers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_unregister(uint32_t interruptNumber)
{
uint32_t address;
//
// Calculate appropriate address for the interrupt number
//
address = (uint32_t)PIEVECTTABLE_BASE +
(((interruptNumber & 0xFFFF0000U) >> 16U) * 2U);
//
// Copy default ISR address into PIE table
//
EALLOW;
HWREG(address) = (uint32_t)Interrupt_defaultHandler;
EDIS;
}
//*****************************************************************************
//
//! Enables CPU interrupt channels
//!
//! \param cpuInterrupt specifies the CPU interrupts to be enabled.
//!
//! This function enables the specified interrupts in the CPU. The
//! \e cpuInterrupt parameter is a logical OR of the values
//! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14,
//! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT.
//!
//! \note Note that interrupts 1-12 correspond to the PIE groups with those
//! same numbers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_enableInCPU(uint16_t cpuInterrupt)
{
//
// Set the interrupt bits in the CPU.
//
IER |= cpuInterrupt;
}
//*****************************************************************************
//
//! Disables CPU interrupt channels
//!
//! \param cpuInterrupt specifies the CPU interrupts to be disabled.
//!
//! This function disables the specified interrupts in the CPU. The
//! \e cpuInterrupt parameter is a logical OR of the values
//! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14,
//! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT.
//!
//! \note Note that interrupts 1-12 correspond to the PIE groups with those
//! same numbers.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_disableInCPU(uint16_t cpuInterrupt)
{
//
// Clear the interrupt bits in the CPU.
//
IER &= ~cpuInterrupt;
}
//*****************************************************************************
//
//! Acknowledges PIE Interrupt Group
//!
//! \param group specifies the interrupt group to be acknowledged.
//!
//! The specified interrupt group is acknowledged and clears any interrupt
//! flag within that respective group.
//!
//! The \e group parameter must be a logical OR of the following:
//! \b INTERRUPT_ACK_GROUP1, \b INTERRUPT_ACK_GROUP2, \b INTERRUPT_ACK_GROUP3
//! \b INTERRUPT_ACK_GROUP4, \b INTERRUPT_ACK_GROUP5, \b INTERRUPT_ACK_GROUP6
//! \b INTERRUPT_ACK_GROUP7, \b INTERRUPT_ACK_GROUP8, \b INTERRUPT_ACK_GROUP9
//! \b INTERRUPT_ACK_GROUP10, \b INTERRUPT_ACK_GROUP11,
//! \b INTERRUPT_ACK_GROUP12.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_clearACKGroup(uint16_t group)
{
//
// Set interrupt group acknowledge bits
//
HWREGH(PIECTRL_BASE + PIE_O_ACK) = group;
}
//*****************************************************************************
//
//! Enables the PIE block.
//!
//! This function enables the vector fetching for the peripheral interrupts by
//! enabling the PIE block.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_enablePIE(void)
{
HWREGH(PIECTRL_BASE + PIE_O_CTRL) |= PIE_CTRL_ENPIE;
}
//*****************************************************************************
//
//! Disables the PIE block.
//!
//! This function disables the vector fetching for the peripheral interrupts by
//! disabling the PIE block. PIEACK, PIEIFR, and PIEIER registers can be
//! accessed even when the PIE block is disabled.
//!
//! \return None.
//
//*****************************************************************************
static inline void
Interrupt_disablePIE(void)
{
HWREGH(PIECTRL_BASE + PIE_O_CTRL) &= ~PIE_CTRL_ENPIE;
}
//*****************************************************************************
//
//! Initializes the PIE control registers by setting them to a known state.
//!
//! This function initializes the PIE control registers. After globally
//! disabling interrupts and enabling the PIE, it clears all of the PIE
//! interrupt enable bits and interrupt flags.
//!
//! \return None.
//
//*****************************************************************************
extern void
Interrupt_initModule(void);
//*****************************************************************************
//
//! Initializes the PIE vector table by setting all vectors to a default
//! handler function.
//!
//! \return None.
//
//*****************************************************************************
extern void
Interrupt_initVectorTable(void);
//*****************************************************************************
//
//! Enables an interrupt.
//!
//! \param interruptNumber specifies the interrupt to be enabled.
//!
//! The specified interrupt is enabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! The available \e interruptNumber values are supplied in
//! <tt>inc/hw_ints.h</tt>.
//!
//! \return None.
//
//*****************************************************************************
extern void
Interrupt_enable(uint32_t interruptNumber);
//*****************************************************************************
//
//! Disables an interrupt.
//!
//! \param interruptNumber specifies the interrupt to be disabled.
//!
//! The specified interrupt is disabled in the interrupt controller. Other
//! enables for the interrupt (such as at the peripheral level) are unaffected
//! by this function.
//!
//! The available \e interruptNumber values are supplied in
//! <tt>inc/hw_ints.h</tt>.
//!
//! \return None.
//
//*****************************************************************************
extern void
Interrupt_disable(uint32_t interruptNumber);
//*****************************************************************************
//
// Extern compiler intrinsic prototypes. See compiler User's Guide for details.
//
//*****************************************************************************
extern uint16_t __disable_interrupts(void);
extern uint16_t __enable_interrupts(void);
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
#endif // #ifdef __TMS320C28XX__
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // INTERRUPT_H
28379d_P_SFRA/device/driverlib/ipc.c
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//###########################################################################
//
// FILE: ipc.c
//
// TITLE: C28x IPC driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "ipc.h"
//
// Macros internal to the IPC driver
//
#define IPC_ADDR_OFFSET_NOCHANGE 2U
#define IPC_ADDR_OFFSET_MUL2 4U
#define IPC_ADDR_OFFSET_DIV2 1U
#define IPC_ADDR_OFFSET_CORR(addr, corr) (((addr) * (corr)) / 2U)
#if IPC_MSGQ_SUPPORT == 1U
//
// Global Circular Buffer Definitions
//
#pragma DATA_SECTION(IPC_CPU1_To_CPU2_PutBuffer, "MSGRAM_CPU1_TO_CPU2")
#pragma DATA_SECTION(IPC_CPU1_To_CPU2_GetBuffer, "MSGRAM_CPU2_TO_CPU1")
//
// IPC_CPU1_To_CPU2_PutBuffer acts as IPC_CPU2_To_CPU1_GetBuffer and
// IPC_CPU1_To_CPU2_GetBuffer acts as IPC_CPU2_To_CPU1_PutBuffer
//
IPC_PutBuffer_t IPC_CPU1_To_CPU2_PutBuffer;
IPC_GetBuffer_t IPC_CPU1_To_CPU2_GetBuffer;
#endif
const IPC_Instance_t IPC_Instance[IPC_TOTAL_NUM] = {
/* IPC_CPU1_L_CPU2_R */
{
.IPC_Flag_Ctr_Reg = (volatile IPC_Flag_Ctr_Reg_t *) IPC_BASE,
.IPC_SendCmd_Reg = (volatile IPC_SendCmd_Reg_t *)
(IPC_BASE + 0x10U),
.IPC_RecvCmd_Reg = (volatile IPC_RecvCmd_Reg_t *)
(IPC_BASE + 0x18U),
.IPC_Boot_Pump_Reg = (volatile IPC_Boot_Pump_Reg_t *)
(IPC_BASE + 0x20U),
.IPC_IntNum = {INT_IPC_0, INT_IPC_1, INT_IPC_2, INT_IPC_3,
0U, 0U, 0U, 0U},
.IPC_MsgRam_LtoR = CPU1_TO_CPU2_MSG_RAM_BASE,
.IPC_MsgRam_RtoL = CPU2_TO_CPU1_MSG_RAM_BASE,
.IPC_Offset_Corr = IPC_ADDR_OFFSET_NOCHANGE
#if IPC_MSGQ_SUPPORT == 1U
,
.IPC_PutBuffer = &IPC_CPU1_To_CPU2_PutBuffer,
.IPC_GetBuffer = &IPC_CPU1_To_CPU2_GetBuffer
#endif
},
/* IPC_CPU2_L_CPU1_R */
{
.IPC_Flag_Ctr_Reg = (volatile IPC_Flag_Ctr_Reg_t *) IPC_BASE,
.IPC_SendCmd_Reg = (volatile IPC_SendCmd_Reg_t *)
(IPC_BASE + 0x18U),
.IPC_RecvCmd_Reg = (volatile IPC_RecvCmd_Reg_t *)
(IPC_BASE + 0x10U),
.IPC_Boot_Pump_Reg = (volatile IPC_Boot_Pump_Reg_t *)
(IPC_BASE + 0x20U),
.IPC_IntNum = {INT_IPC_0, INT_IPC_1, INT_IPC_2, INT_IPC_3,
0U, 0U, 0U, 0U},
.IPC_MsgRam_LtoR = CPU2_TO_CPU1_MSG_RAM_BASE,
.IPC_MsgRam_RtoL = CPU1_TO_CPU2_MSG_RAM_BASE,
.IPC_Offset_Corr = IPC_ADDR_OFFSET_NOCHANGE
#if IPC_MSGQ_SUPPORT == 1U
,
.IPC_PutBuffer = (IPC_PutBuffer_t *)&IPC_CPU1_To_CPU2_GetBuffer,
.IPC_GetBuffer = (IPC_GetBuffer_t *)&IPC_CPU1_To_CPU2_PutBuffer
#endif
}
};
//*****************************************************************************
//
// IPC_sendCommand
//
//*****************************************************************************
bool IPC_sendCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable,
uint32_t command, uint32_t addr, uint32_t data)
{
bool ret;
//
// Check whether the flags are not busy
//
if((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flags) == 0U)
{
ret = true;
if(addrCorrEnable)
{
//
// Update the command registers. ADDR register holds the offset
// from the base address of the MSG RAM
//
IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDCOM = command;
IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDDATA = data;
IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDADDR =
addr - IPC_Instance[ipcType].IPC_MsgRam_LtoR;
}
else
{
//
// Update the command registers. addr param remains as is.
//
IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDCOM = command;
IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDDATA = data;
IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDADDR = addr;
}
//
// Set the flags to indicate the remote core
//
IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_SET = flags;
}
else
{
ret = false;
}
return(ret);
}
//*****************************************************************************
//
// IPC_readCommand
//
//*****************************************************************************
bool IPC_readCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable,
uint32_t *command, uint32_t *addr, uint32_t *data)
{
bool ret;
uint32_t addrReg;
//
// Check whether the flags are not empty
//
if((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flags) != 0U)
{
ret = true;
//
// Read the command registers
//
*command = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVCOM;
addrReg = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVADDR;
*data = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVDATA;
if(addrCorrEnable)
{
//
// Calculate the address form the offset
//
*addr = IPC_Instance[ipcType].IPC_MsgRam_RtoL +
IPC_ADDR_OFFSET_CORR(addrReg,
IPC_Instance[ipcType].IPC_Offset_Corr);
}
else
{
*addr = addrReg;
}
}
else
{
ret = false;
}
return(ret);
}
//*****************************************************************************
//
// IPC_registerInterrupt
//
//*****************************************************************************
void IPC_registerInterrupt(IPC_Type_t ipcType, uint32_t ipcInt,
void (*pfnHandler)(void))
{
//
// Check for arguments
//
ASSERT(ipcInt <= IPC_INT3);
//
// Get the corresponding interrupt number
//
uint32_t intNum = IPC_Instance[ipcType].IPC_IntNum[ipcInt];
//
// Register the interrupt handler
//
Interrupt_register(intNum, pfnHandler);
//
// Enable the interrupt
//
Interrupt_enable(intNum);
}
//*****************************************************************************
//
// IPC_unregisterInterrupt
//
//*****************************************************************************
void IPC_unregisterInterrupt(IPC_Type_t ipcType, uint32_t ipcInt)
{
//
// Check for arguments
//
ASSERT(ipcInt <= IPC_INT3);
//
// Get the corresponding interrupt number
//
uint32_t intNum = IPC_Instance[ipcType].IPC_IntNum[ipcInt];
//
// Disable the interrupt.
//
Interrupt_disable(intNum);
//
// Unregister the interrupt handler.
//
Interrupt_unregister(intNum);
}
#if IPC_MSGQ_SUPPORT == 1U
//*****************************************************************************
//
// IPCinitMessageQueue
//
//*****************************************************************************
void IPC_initMessageQueue(IPC_Type_t ipcType,
volatile IPC_MessageQueue_t *msgQueue,
uint32_t ipcInt_L, uint32_t ipcInt_R)
{
//
// Check for arguments
//
ASSERT(msgQueue != NULL);
ASSERT(ipcInt_L < IPC_NUM_OF_INTERRUPTS);
ASSERT(ipcInt_R < IPC_NUM_OF_INTERRUPTS);
IPC_PutBuffer_t *putBuffer = IPC_Instance[ipcType].IPC_PutBuffer;
IPC_GetBuffer_t *getBuffer = IPC_Instance[ipcType].IPC_GetBuffer;
//
// L->R Put Buffer and Index Initialization
//
msgQueue->PutBuffer = putBuffer->Buffer[ipcInt_R];
msgQueue->PutWriteIndex = &(putBuffer->PutWriteIndex[ipcInt_R]);
msgQueue->GetReadIndex = &(putBuffer->GetReadIndex[ipcInt_L]);
msgQueue->PutFlag = (uint32_t)1U << ipcInt_R;
//
// L->R Get Buffer and Index Initialization
//
msgQueue->GetBuffer = getBuffer->Buffer[ipcInt_L];
msgQueue->GetWriteIndex = &(getBuffer->GetWriteIndex[ipcInt_L]);
msgQueue->PutReadIndex = &(getBuffer->PutReadIndex[ipcInt_R]);
//
// Initialize PutBuffer WriteIndex = 0 and GetBuffer ReadIndex = 0
//
*(msgQueue->PutWriteIndex) = 0U;
*(msgQueue->GetReadIndex) = 0U;
}
//*****************************************************************************
//
// IPC_sendMessageToQueue
//
//*****************************************************************************
bool IPC_sendMessageToQueue(IPC_Type_t ipcType,
volatile IPC_MessageQueue_t *msgQueue,
bool addrCorrEnable, IPC_Message_t *msg, bool block)
{
//
// Check for arguments
//
ASSERT(msgQueue != NULL);
ASSERT(msg != NULL);
uint16_t writeIndex;
uint16_t readIndex;
bool ret = true;
writeIndex = *(msgQueue->PutWriteIndex);
readIndex = *(msgQueue->PutReadIndex);
//
// Wait until Put Buffer slot is free
//
while(((writeIndex + 1U) & IPC_MAX_BUFFER_INDEX) == readIndex)
{
//
// If designated as a "Blocking" function, and Put buffer is full,
// return immediately with fail status.
//
if(!block)
{
ret = false;
break;
}
readIndex = *(msgQueue->PutReadIndex);
}
if(ret != false)
{
//
// When slot is free, Write Message to PutBuffer, update PutWriteIndex,
// and set the CPU IPC INT Flag
//
msgQueue->PutBuffer[writeIndex] = *msg;
if(addrCorrEnable)
{
msgQueue->PutBuffer[writeIndex].address -=
IPC_Instance[ipcType].IPC_MsgRam_LtoR;
}
writeIndex = (writeIndex + 1U) & IPC_MAX_BUFFER_INDEX;
*(msgQueue->PutWriteIndex) = writeIndex;
IPC_setFlagLtoR(ipcType, msgQueue->PutFlag);
}
return(ret);
}
//*****************************************************************************
//
// IPC_readMessageFromQueue
//
//*****************************************************************************
bool IPC_readMessageFromQueue(IPC_Type_t ipcType,
volatile IPC_MessageQueue_t *msgQueue,
bool addrCorrEnable, IPC_Message_t *msg, bool block)
{
//
// Check for arguments
//
ASSERT(msgQueue != NULL);
ASSERT(msg != NULL);
uint16_t writeIndex;
uint16_t readIndex;
bool ret = true;
writeIndex = *(msgQueue->GetWriteIndex);
readIndex = *(msgQueue->GetReadIndex);
//
// Loop while GetBuffer is empty
//
while(writeIndex == readIndex)
{
//
// If designated as a "Blocking" function, and Get buffer is empty,
// return immediately with fail status.
//
if(!block)
{
ret = false;
break;
}
writeIndex = *(msgQueue->GetWriteIndex);
}
if(ret != false)
{
//
// If there is a message in GetBuffer, Read Message and update
// the ReadIndex
//
*msg = msgQueue->GetBuffer[readIndex];
if(addrCorrEnable)
{
msg->address = IPC_Instance[ipcType].IPC_MsgRam_RtoL +
IPC_ADDR_OFFSET_CORR(msg->address,
IPC_Instance[ipcType].IPC_Offset_Corr);
}
readIndex = (readIndex + 1U) & IPC_MAX_BUFFER_INDEX;
*(msgQueue->GetReadIndex) = readIndex;
}
return(ret);
}
#endif
28379d_P_SFRA/device/driverlib/ipc.h
+880
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//###########################################################################
//
// FILE: ipc.h
//
// TITLE: C28x IPC driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef IPC_H
#define IPC_H
//*****************************************************************************
//
// If building with a C++ compiler, make all of the definitions in this header
// have a C binding.
//
//*****************************************************************************
#ifdef __cplusplus
extern "C"
{
#endif
//*****************************************************************************
//
//! \addtogroup ipc_api IPC
//! \brief This module is used for inter-processor communications.
//! @{
//
//*****************************************************************************
#include <stdbool.h>
#include <stdint.h>
#include "debug.h"
#include "inc/hw_memmap.h"
#include "inc/hw_types.h"
#include "inc/hw_ipc.h"
#include "inc/hw_ints.h"
#include "interrupt.h"
//*****************************************************************************
//
// Defines for the APIs
//
//*****************************************************************************
//*****************************************************************************
//
// Driver configuration macros
//
//*****************************************************************************
#define IPC_MSGQ_SUPPORT 1U
//
// Number of IPC messages in circular buffer (must be interval of 2)
//
#define IPC_BUFFER_SIZE 4U
//
// Number of IPC interrupts using circular buffer (must be same number on both
// CPUs)
//
#define IPC_NUM_OF_INTERRUPTS 4U
//*****************************************************************************
//
// Values that can be passed as parameter flags in all the IPC API functions.
//
//*****************************************************************************
#ifndef IPC_FLAGS_DEFINED
#define IPC_FLAGS_DEFINED
#define IPC_NO_FLAG 0x00000000U //!< NO FLAG
#define IPC_FLAG0 0x00000001U //!< IPC FLAG 0
#define IPC_FLAG1 0x00000002U //!< IPC FLAG 1
#define IPC_FLAG2 0x00000004U //!< IPC FLAG 2
#define IPC_FLAG3 0x00000008U //!< IPC FLAG 3
#define IPC_FLAG4 0x00000010U //!< IPC FLAG 4
#define IPC_FLAG5 0x00000020U //!< IPC FLAG 5
#define IPC_FLAG6 0x00000040U //!< IPC FLAG 6
#define IPC_FLAG7 0x00000080U //!< IPC FLAG 7
#define IPC_FLAG8 0x00000100U //!< IPC FLAG 8
#define IPC_FLAG9 0x00000200U //!< IPC FLAG 9
#define IPC_FLAG10 0x00000400U //!< IPC FLAG 10
#define IPC_FLAG11 0x00000800U //!< IPC FLAG 11
#define IPC_FLAG12 0x00001000U //!< IPC FLAG 12
#define IPC_FLAG13 0x00002000U //!< IPC FLAG 13
#define IPC_FLAG14 0x00004000U //!< IPC FLAG 14
#define IPC_FLAG15 0x00008000U //!< IPC FLAG 15
#define IPC_FLAG16 0x00010000U //!< IPC FLAG 16
#define IPC_FLAG17 0x00020000U //!< IPC FLAG 17
#define IPC_FLAG18 0x00040000U //!< IPC FLAG 18
#define IPC_FLAG19 0x00080000U //!< IPC FLAG 19
#define IPC_FLAG20 0x00100000U //!< IPC FLAG 20
#define IPC_FLAG21 0x00200000U //!< IPC FLAG 21
#define IPC_FLAG22 0x00400000U //!< IPC FLAG 22
#define IPC_FLAG23 0x00800000U //!< IPC FLAG 23
#define IPC_FLAG24 0x01000000U //!< IPC FLAG 24
#define IPC_FLAG25 0x02000000U //!< IPC FLAG 25
#define IPC_FLAG26 0x04000000U //!< IPC FLAG 26
#define IPC_FLAG27 0x08000000U //!< IPC FLAG 27
#define IPC_FLAG28 0x10000000U //!< IPC FLAG 28
#define IPC_FLAG29 0x20000000U //!< IPC FLAG 29
#define IPC_FLAG30 0x40000000U //!< IPC FLAG 30
#define IPC_FLAG31 0x80000000U //!< IPC FLAG 31
#define IPC_FLAG_ALL 0xFFFFFFFFU //!< All IPC flags
#endif
//*****************************************************************************
//
// Values that can be passed as parameter ipcInt in
// IPC_registerInterrupt and IPC_unregisterInterrupt functions.
// Please refer to the datasheet for the actual number of interrupts available
// for each IPC instance
//
//*****************************************************************************
#define IPC_INT0 0x0U //!< IPC Interrupt 0
#define IPC_INT1 0x1U //!< IPC Interrupt 1
#define IPC_INT2 0x2U //!< IPC Interrupt 2
#define IPC_INT3 0x3U //!< IPC Interrupt 3
#define IPC_INT4 0x4U //!< IPC Interrupt 4
#define IPC_INT5 0x5U //!< IPC Interrupt 5
#define IPC_INT6 0x6U //!< IPC Interrupt 6
#define IPC_INT7 0x7U //!< IPC Interrupt 7
//*****************************************************************************
//
// Values that can be passed as parameter addrCorrEnable in
// IPC_sendCommand, IPC_readCommand, IPC_sendMessageToQueue and
// IPC_readMessageFromQueue functions.
//
//*****************************************************************************
#define IPC_ADDR_CORRECTION_ENABLE true
#define IPC_ADDR_CORRECTION_DISABLE false
//*****************************************************************************
//
// Values that can be passed as parameter block in
// IPC_sendMessageToQueue and IPC_readMessageFromQueue functions.
//
//*****************************************************************************
#define IPC_BLOCKING_CALL true
#define IPC_NONBLOCKING_CALL false
//*****************************************************************************
//
// Internal macros used for message queue implementation
//
//*****************************************************************************
#define IPC_MAX_BUFFER_INDEX (IPC_BUFFER_SIZE - 1U)
//*****************************************************************************
//
// Enums for the APIs
//
//*****************************************************************************
//*****************************************************************************
//
//! Values that can be passed as parameter \e ipcType in all the driver
//! functions
//
//*****************************************************************************
typedef enum
{
IPC_CPU1_L_CPU2_R, //!< CPU1 - Local core, CPU2 - Remote core
IPC_CPU2_L_CPU1_R, //!< CPU2 - Local core, CPU1 - Remote core
IPC_TOTAL_NUM
}IPC_Type_t;
//*****************************************************************************
//
// Internal structs for register and messaage queue accesses
//
//*****************************************************************************
typedef struct
{
uint32_t IPC_ACK;
uint32_t IPC_STS;
uint32_t IPC_SET;
uint32_t IPC_CLR;
uint32_t IPC_FLG;
uint32_t IPC_RSVDREG;
uint32_t IPC_COUNTERL;
uint32_t IPC_COUNTERH;
}IPC_Flag_Ctr_Reg_t;
typedef struct
{
uint32_t IPC_SENDCOM;
uint32_t IPC_SENDADDR;
uint32_t IPC_SENDDATA;
uint32_t IPC_REMOTEREPLY;
}IPC_SendCmd_Reg_t;
typedef struct
{
uint32_t IPC_RECVCOM;
uint32_t IPC_RECVADDR;
uint32_t IPC_RECVDATA;
uint32_t IPC_LOCALREPLY;
}IPC_RecvCmd_Reg_t;
typedef struct
{
uint32_t IPC_BOOTSTS;
uint32_t IPC_BOOTMODE;
}IPC_Boot_Pump_Reg_t;
#if IPC_MSGQ_SUPPORT == 1U
typedef struct
{
uint32_t command;
uint32_t address;
uint32_t dataw1;
uint32_t dataw2;
}IPC_Message_t;
typedef struct
{
IPC_Message_t Buffer[IPC_NUM_OF_INTERRUPTS][IPC_BUFFER_SIZE];
uint16_t PutWriteIndex[IPC_NUM_OF_INTERRUPTS];
uint16_t GetReadIndex[IPC_NUM_OF_INTERRUPTS];
}IPC_PutBuffer_t;
typedef struct
{
IPC_Message_t Buffer[IPC_NUM_OF_INTERRUPTS][IPC_BUFFER_SIZE];
uint16_t GetWriteIndex[IPC_NUM_OF_INTERRUPTS];
uint16_t PutReadIndex[IPC_NUM_OF_INTERRUPTS];
}IPC_GetBuffer_t;
#endif
//*****************************************************************************
//
// Internal struct used to store the required information regarding an IPC
// instance
//
//*****************************************************************************
typedef struct
{
volatile IPC_Flag_Ctr_Reg_t *IPC_Flag_Ctr_Reg;
volatile IPC_SendCmd_Reg_t *IPC_SendCmd_Reg;
volatile IPC_RecvCmd_Reg_t *IPC_RecvCmd_Reg;
volatile IPC_Boot_Pump_Reg_t *IPC_Boot_Pump_Reg;
uint32_t IPC_IntNum[8U];
uint32_t IPC_MsgRam_LtoR;
uint32_t IPC_MsgRam_RtoL;
uint32_t IPC_Offset_Corr;
#if IPC_MSGQ_SUPPORT == 1U
IPC_PutBuffer_t *IPC_PutBuffer;
IPC_GetBuffer_t *IPC_GetBuffer;
#endif
}IPC_Instance_t;
extern const IPC_Instance_t IPC_Instance[IPC_TOTAL_NUM];
#if IPC_MSGQ_SUPPORT == 1U
//*****************************************************************************
//
// A structure that defines an IPC message queue. These
// fields are used by the IPC drivers, and normally it is not necessary for
// user software to directly read or write fields in the table.
//
//*****************************************************************************
typedef struct
{
IPC_Message_t * PutBuffer;
uint32_t PutFlag;
uint16_t * PutWriteIndex;
uint16_t * PutReadIndex;
IPC_Message_t * GetBuffer;
uint16_t * GetWriteIndex;
uint16_t * GetReadIndex;
} IPC_MessageQueue_t;
#endif
//*****************************************************************************
//
// API Function prototypes
//
//*****************************************************************************
//*****************************************************************************
//
//! Local core sets Local to Remote IPC Flag
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param flags is the IPC flag mask for the flags being set
//!
//! This function will allow the Local core system to set the designated IPC
//! flags to send to the Remote core system. The \e flags parameter can be any
//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31.
//!
//! \return None.
//
//*****************************************************************************
static inline void
IPC_setFlagLtoR(IPC_Type_t ipcType, uint32_t flags)
{
IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_SET = flags;
}
//*****************************************************************************
//
//! Local core clears Local to Remote IPC Flag
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param flags is the IPC flag mask for the flags being cleared
//!
//! This function will allow the Local core system to clear the designated IPC
//! flags sent to the Remote core system. The \e flags parameter can be any
//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31.
//!
//! \return None.
//
//*****************************************************************************
static inline void
IPC_clearFlagLtoR(IPC_Type_t ipcType, uint32_t flags)
{
IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_CLR = flags;
}
//*****************************************************************************
//
//! Local core acknowledges Remote to Local IPC Flag.
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param flags is the IPC flag mask for the flags being acknowledged.
//!
//! This function will allow the Local core system to acknowledge/clear the IPC
//! flag set by the Remote core system. The \e flags parameter can be any of
//! the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31.
//!
//! \return None.
//
//*****************************************************************************
static inline void
IPC_ackFlagRtoL(IPC_Type_t ipcType, uint32_t flags)
{
IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_ACK = flags;
}
//*****************************************************************************
//
//! Determines whether the given IPC flags are busy or not.
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param flags is the Local to Remote IPC flag masks to check the status of
//!
//! Allows the caller to determine whether the designated Local to Remote
//! IPC flags are pending. The \e flags parameter can be any of the IPC flag
//! values: \b IPC_FLAG0 - \b IPC_FLAG31.
//!
//! \return Returns \b true if the any of the designated IPC flags are busy
//! or \b false if all the designated IPC flags are free.
//
//*****************************************************************************
static inline bool
IPC_isFlagBusyLtoR(IPC_Type_t ipcType, uint32_t flags)
{
return((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flags) != 0U);
}
//*****************************************************************************
//
//! Determines whether the given Remote to Local IPC flags are busy or not.
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param flags is the Remote to Local IPC Flag masks to check the status of
//!
//! Allows the caller to determine whether the designated Remote to Local
//! IPC flags are pending. The \e flags parameter can be any of the IPC flag
//! values: \b IPC_FLAG0 - \b IPC_FLAG31.
//!
//! \return Returns \b true if the any of the designated IPC flags are busy
//! or \b false if all the designated IPC flags are free.
//
//*****************************************************************************
static inline bool
IPC_isFlagBusyRtoL(IPC_Type_t ipcType, uint32_t flags)
{
return((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flags) != 0U);
}
//*****************************************************************************
//
//! Wait for the remote core to send a flag
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param flag is the Remote to Local IPC flag mask to wait for
//!
//! Allows the caller to wait for the Remote to Local flag to be send by
//! the remote core. The \e flags parameter can be any of the IPC flag
//! values: \b IPC_FLAG0 - \b IPC_FLAG31.
//!
//! \return None
//
//*****************************************************************************
static inline void
IPC_waitForFlag(IPC_Type_t ipcType, uint32_t flag)
{
while((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flag) == 0U)
{
}
}
//*****************************************************************************
//
//! Wait for the IPC flag to be acknowledged
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param flag is the IPC flag mask for which ack is pending
//!
//! Allows the caller to wait for the IPC flag to be acknowledged by the
//! remote core. The \e flagsparameter can be any of the IPC flag values:
//! \b IPC_FLAG0 - \b IPC_FLAG31.
//!
//! \return None
//
//*****************************************************************************
static inline void
IPC_waitForAck(IPC_Type_t ipcType, uint32_t flag)
{
while((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flag) != 0U)
{
}
}
//*****************************************************************************
//
//! Synchronises the two cores
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param flag is the IPC flag mask with which synchronisation is done
//!
//! Allows the local and remote cores to synchronise. Neither core will return
//! from this function call before the other core enters it.
//!
//! \note Must be called with same flag mask on both the cores
//!
//! \return None
//
//*****************************************************************************
static inline void
IPC_sync(IPC_Type_t ipcType, uint32_t flag)
{
IPC_setFlagLtoR(ipcType, flag);
IPC_waitForFlag(ipcType, flag);
IPC_ackFlagRtoL(ipcType, flag);
IPC_waitForAck(ipcType, flag);
}
//*****************************************************************************
//
//! Initialize IPC
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//
//! This function initializes IPC by clearing all the flags
//!
//! \return None
//
//*****************************************************************************
static inline void
IPC_init(IPC_Type_t ipcType)
{
IPC_clearFlagLtoR(ipcType, IPC_FLAG_ALL);
}
//*****************************************************************************
//
//! Sends a command to the Remote core
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param flags is the IPC flag mask for the flags to be set
//! \param addrCorrEnable is the flag used to determine whether or not to
//! convert the addr parameter to remote core's address space
//! \param command is the 32-bit command value
//! \param addr is the 32-bit address to be sent as part of command
//! \param data is the 32-bit data to be sent as part of command
//!
//! Allows the caller to send a command to the remote core. A command consists
//! of a unique command value, a 32-bit address and a 32-bit data. The function
//! also sends the designated flags to the remote core.
//! There may be differences in the address spaces of Local and Remote core.
//! For example in case of F2838X device, the address spaces of C28x core and
//! CM core are different. In case the \e addr refers to an address in the IPC
//! MSG RAM, \e addrCorrEnable param may be used to correct the address mismatch
//!
//! The \e flags parameter can be any of the IPC flag values: \b IPC_FLAG0 -
//! \b IPC_FLAG31.
//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE
//! (converts the address to remote core's address space) or
//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter)
//!
//! The application shall use the function IPC_getResponse to read the response
//! sent by the remote core.
//!
//! \note The application is expected to wait until the the response is
//! received before sending another command.
//!
//! \note \e addrCorrEnable parameter must be kept same on the sending and
//! receiving cores
//!
//! \return Returns \b true if the command is sent properly and \b false if
//! the designated flags were busy and hence command was not sent.
//
//*****************************************************************************
extern bool
IPC_sendCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable,
uint32_t command, uint32_t addr, uint32_t data);
//*****************************************************************************
//
//! Reads a command sent by the Remote core
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param flags is the IPC flag mask for the flags sent by the remote core
//! \param addrCorrEnable is the flag used to determine whether or not to
//! convert the addr parameter to remote core's address space
//! \param command is the 32-bit pointer at which the command value is read to
//! \param addr is the 32-bit pointer at which address value is read to
//! \param data is the 32-bit pointer at which the data is read to
//!
//! Allows the caller to read a command sent by the remote core. A command
//! consists of a unique command value, a 32-bit address and a 32-bit data.
//! There may be differences in the address spaces of Local and Remote core.
//! For example in case of F2838X device, the address spaces of C28x core and
//! CM core are different. In case the \e addr refers to an address in the IPC
//! MSG RAM, \e addrCorrEnable param may be used to correct the address mismatch
//!
//! The \e flags parameter can be any of the IPC flag values: \b IPC_FLAG0 -
//! \b IPC_FLAG31.
//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE
//! (converts the address to remote core's address space) or
//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter)
//!
//! \note The application is expected to acknowledge the flag and send a
//! response (if needed) after reading the command
//!
//! \note \e addrCorrEnable parameter must be kept same on the sending and
//! receiving cores
//!
//! \return Returns \b true if the command is read properly and \b false if
//! the designated flags were empty and hence command was not read.
//
//*****************************************************************************
extern bool
IPC_readCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable,
uint32_t *command, uint32_t *addr, uint32_t *data);
//*****************************************************************************
//
//! Sends the response to the command sent by remote core.
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param data is the 32-bit value of the response to be sent
//!
//! Allows the caller to send a response to the command previously sent by the
//! remote core
//!
//! \return None.
//
//*****************************************************************************
static inline void
IPC_sendResponse(IPC_Type_t ipcType, uint32_t data)
{
IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_LOCALREPLY = data;
}
//*****************************************************************************
//
//! Reads the response from the remote core.
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//!
//! Allows the caller to read the response sent by the remote core to the
//! command previously sent by the local core
//!
//! \return the 32-bit value of the response.
//
//*****************************************************************************
static inline uint32_t
IPC_getResponse(IPC_Type_t ipcType)
{
return(IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_REMOTEREPLY);
}
//*****************************************************************************
//
//! Sets the BOOTMODE register.
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param mode is the 32-bit value to be set
//!
//! Allows the caller to set the BOOTMODE register.
//!
//! \note This function shall be called by CPU1 only.
//!
//! \return None
//
//*****************************************************************************
static inline void
IPC_setBootMode(IPC_Type_t ipcType, uint32_t mode)
{
ASSERT(ipcType == IPC_CPU1_L_CPU2_R);
IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTMODE = mode;
}
//*****************************************************************************
//
//! Reads the BOOTMODE register.
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//!
//! Allows the caller to read the BOOTMODE register.
//!
//!
//! \return 32-bit value of the BOOOTMODE register
//
//*****************************************************************************
static inline uint32_t
IPC_getBootMode(IPC_Type_t ipcType)
{
return(IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTMODE);
}
//*****************************************************************************
//
//! Sets the BOOTSTS register.
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param status is the 32-bit value to be set
//!
//! Allows the caller to set the BOOTSTS register.
//!
//! \note This function shall be called by CPU2 and CM only
//!
//! \note This function shall be called by CPU2 only.
//!
//! \return None.
//
//*****************************************************************************
static inline void
IPC_setBootStatus(IPC_Type_t ipcType, uint32_t status)
{
ASSERT(ipcType == IPC_CPU2_L_CPU1_R);
IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTSTS = status;
}
//*****************************************************************************
//
//! Reads the BOOTSTS register.
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//!
//! Allows the caller to set the BOOTMODE register.
//!
//!
//! \return 32-bit value of the BOOOTSTS register
//
//*****************************************************************************
static inline uint32_t
IPC_getBootStatus(IPC_Type_t ipcType)
{
return(IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTSTS);
}
//*****************************************************************************
//
//! Reads the timestamp counter value.
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//!
//! Allows the caller to read the IPC timestamp counter value.
//!
//! \return 64-bit counter value.
//
//*****************************************************************************
static inline uint64_t
IPC_getCounter(IPC_Type_t ipcType)
{
//
// Get the Counter High and Low values. Read to the Counter low register
// saves the value of Counter High register.
//
uint32_t ctrL = IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_COUNTERL;
uint32_t ctrH = IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_COUNTERH;
//
// Return the 64-bit value of the counter
//
return(((uint64_t)ctrH << 32) | ((uint64_t)ctrL));
}
//*****************************************************************************
//
//! Registers an interrupt handler for IPC
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param ipcInt is the Flag number for which interrupt is being registered
//! \param pfnHandler is the pointer to ISR function
//!
//! This function registers the handler to be called when an IPC interrupt
//! occurs. This function enables the global interrupt in the interrupt
//! controller.
//! The \e ipcInt parameter can be any of the IPC flag values:\b IPC_INT0 -
//! \b IPC_INT7. IPC_INT0 corresponds to IPC Flag 0 interrupt and so on.
//
//*****************************************************************************
extern void
IPC_registerInterrupt(IPC_Type_t ipcType, uint32_t ipcInt,
void (*pfnHandler)(void));
//*****************************************************************************
//
//! Unregisters an interrupt handler for IPC
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param ipcInt is the Flag number for which interrupt is being unregistered
//!
//! This function clears the handler to be called when an IPC interrupt
//! occurs. This function also masks off the interrupt in the interrupt
//! controller so that the interrupt handler no longer is called.
//! The \e ipcInt parameter can be any of the IPC flag values:\b IPC_INT0 -
//! \b IPC_INT7. IPC_INT0 corresponds to IPC Flag 0 interrupt and so on.
//
//*****************************************************************************
extern void
IPC_unregisterInterrupt(IPC_Type_t ipcType, uint32_t ipcInt);
#if IPC_MSGQ_SUPPORT == 1U
//*****************************************************************************
//
//! Initializes the IPC message queue
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance
//! \param ipcInt_L specifies the interrupt number on the local core used by
//! the message queue .
//! \param ipcInt_R specifies the interrupt number on the remote core used by
//! the message queue.
//!
//! This function initializes the IPC message queue with circular buffer
//! and index addresses for an IPC interrupt pair. The
//! \e ipcInt_L and \e ipcInt_R parameters can be one of the following values:
//! \b IPC_INT0, \b IPC_INT1, \b IPC_INT2, \b IPC_INT3.
//!
//! \note If an interrupt is currently in use by an \e IPC_MessageQueue_t
//! instance, that particular interrupt should not be tied to a second
//! \e IPC_MessageQueue_t instance.
//!
//! \note For a particular ipcInt_L - ipcInt_R pair, there must be an instance
//! of IPC_MessageQueue_t defined and initialized on both the locakl and remote
//! systems.
//!
//! \return None.
//
//*****************************************************************************
extern void
IPC_initMessageQueue(IPC_Type_t ipcType, volatile IPC_MessageQueue_t *msgQueue,
uint32_t ipcInt_L, uint32_t ipcInt_R);
//*****************************************************************************
//
//! Sends a message into the messageQueue.
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance
//! \param addrCorrEnable is the flag used to determine whether or not to
//! convert the addr parameter to remote core's address space
//! \param msg specifies the address of the \e IPC_Message_t instance to be
//! sent to message queue.
//! \param block specifies whether to allow function to block until the buffer
//! has a free slot
//!
//! This function checks if there is a free slot in the message queue. If so, it
//! puts the message pointed to by \e msg into the free and sets the
//! appropriate IPC interrupt flag
//!
//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE
//! (converts the address to remote core's address space) or
//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter)
//! The \e block parameter can be one of the following values:
//! \b IPC_BLOCKING_CALL or \b IPC_NONBLOCKING_CALL.
//!
//! \return \b false if the queue is full. \b true if the message is
//! successfully sent.
//
//*****************************************************************************
extern bool
IPC_sendMessageToQueue(IPC_Type_t ipcType,
volatile IPC_MessageQueue_t *msgQueue,
bool addrCorrEnable, IPC_Message_t *msg, bool block);
//*****************************************************************************
//
//! Reads a message from the messageQueue.
//!
//! \param ipcType is the enum corresponding to the IPC instance used
//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance
//! \param addrCorrEnable is the flag used to determine whether or not to
//! convert the addr parameter to remote core's address space
//! \param msg specifies the address of the \e IPC_Message_t instance to which
//! the message needs to be read
//! \param block specifies whether to allow function to block until a message
//! is available in the message queue
//!
//! This function checks if there is a message in the message queue. If so, it
//! reads the message and writes to the address pointed to by \e msg into.
//!
//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE
//! (converts the address to remote core's address space) or
//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter)
//! The \e block parameter can be one of the following values:
//! \b IPC_BLOCKING_CALL or \b IPC_NONBLOCKING_CALL.
//!
//! \return \b false if the queue is empty. \b true if the message successfully
//! read.
//
//*****************************************************************************
extern bool
IPC_readMessageFromQueue(IPC_Type_t ipcType,
volatile IPC_MessageQueue_t *msgQueue,
bool addrCorrEnable, IPC_Message_t *msg, bool block);
#endif
//*****************************************************************************
//
// Close the Doxygen group.
//! @}
//
//*****************************************************************************
//*****************************************************************************
//
// Mark the end of the C bindings section for C++ compilers.
//
//*****************************************************************************
#ifdef __cplusplus
}
#endif
#endif // IPC_H
28379d_P_SFRA/device/driverlib/mcbsp.c
+1621
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28379d_P_SFRA/device/driverlib/mcbsp.h
+3340
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28379d_P_SFRA/device/driverlib/memcfg.c
+701
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@@ -0,0 +1,701 @@
//###########################################################################
//
// FILE: memcfg.c
//
// TITLE: C28x RAM config driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "memcfg.h"
//*****************************************************************************
//
// MemCfg_lockConfig
//
//*****************************************************************************
void
MemCfg_lockConfig(uint32_t memSections)
{
//
// Check the arguments.
//
ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) ||
(memSections == MEMCFG_SECT_ALL));
//
// Set the bit that blocks writes to the sections' configuration registers.
//
EALLOW;
switch(memSections & MEMCFG_SECT_TYPE_MASK)
{
case MEMCFG_SECT_TYPE_D:
HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) |= MEMCFG_SECT_NUM_MASK &
memSections;
break;
case MEMCFG_SECT_TYPE_LS:
HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) |= MEMCFG_SECT_NUM_MASK &
memSections;
break;
case MEMCFG_SECT_TYPE_GS:
HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) |= MEMCFG_SECT_NUM_MASK &
memSections;
break;
case MEMCFG_SECT_TYPE_MASK:
//
// Lock configuration for all sections.
//
HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) |= MEMCFG_SECT_NUM_MASK &
MEMCFG_SECT_DX_ALL;
HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) |= MEMCFG_SECT_NUM_MASK &
MEMCFG_SECT_LSX_ALL;
HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) |= MEMCFG_SECT_NUM_MASK &
MEMCFG_SECT_GSX_ALL;
break;
default:
//
// Do nothing. Invalid memSections. Make sure you aren't OR-ing
// values for two different types of memory sections.
//
break;
}
EDIS;
}
//*****************************************************************************
//
// MemCfg_unlockConfig
//
//*****************************************************************************
void
MemCfg_unlockConfig(uint32_t memSections)
{
//
// Check the arguments.
//
ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) ||
(memSections == MEMCFG_SECT_ALL));
//
// Clear the bit that blocks writes to the sections' configuration
// registers.
//
EALLOW;
switch(memSections & MEMCFG_SECT_TYPE_MASK)
{
case MEMCFG_SECT_TYPE_D:
HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) &= ~(MEMCFG_SECT_NUM_MASK &
memSections);
break;
case MEMCFG_SECT_TYPE_LS:
HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK &
memSections);
break;
case MEMCFG_SECT_TYPE_GS:
HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK &
memSections);
break;
case MEMCFG_SECT_TYPE_MASK:
//
// Unlock configuration for all sections.
//
HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) &=
~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_DX_ALL));
HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &=
~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_LSX_ALL));
HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &=
~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_GSX_ALL));
break;
default:
//
// Do nothing. Invalid memSections. Make sure you aren't OR-ing
// values for two different types of memory sections.
//
break;
}
EDIS;
}
//*****************************************************************************
//
// MemCfg_commitConfig
//
//*****************************************************************************
void
MemCfg_commitConfig(uint32_t memSections)
{
//
// Check the arguments.
//
ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) ||
(memSections == MEMCFG_SECT_ALL));
//
// Set the bit that permanently blocks writes to the sections'
// configuration registers.
//
EALLOW;
switch(memSections & MEMCFG_SECT_TYPE_MASK)
{
case MEMCFG_SECT_TYPE_D:
HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
memSections;
break;
case MEMCFG_SECT_TYPE_LS:
HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
memSections;
break;
case MEMCFG_SECT_TYPE_GS:
HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
memSections;
break;
case MEMCFG_SECT_TYPE_MASK:
//
// Commit configuration for all sections.
//
HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
MEMCFG_SECT_DX_ALL;
HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
MEMCFG_SECT_LSX_ALL;
HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT) |= MEMCFG_SECT_NUM_MASK &
MEMCFG_SECT_GSX_ALL;
break;
default:
//
// Do nothing. Invalid memSections. Make sure you aren't OR-ing
// values for two different types of RAM.
//
break;
}
EDIS;
}
//*****************************************************************************
//
// MemCfg_setProtection
//
//*****************************************************************************
void
MemCfg_setProtection(uint32_t memSection, uint32_t protectMode)
{
uint32_t shiftVal = 0U;
uint32_t maskVal;
uint32_t regVal;
uint32_t sectionNum;
uint32_t regOffset;
//
// Check the arguments.
//
ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS));
//
// Calculate how far the protect mode value needs to be shifted. Each
// section number is represented by a bit in the lower word of memSection
// and 8 bits in the corresponding ACCPROT register.
//
sectionNum = memSection & MEMCFG_SECT_NUM_MASK;
while(sectionNum != 1U)
{
sectionNum = sectionNum >> 1U;
shiftVal += 8U;
}
//
// Calculate register offset. Also, make sure the shift value is no greater
// than 31.
//
regOffset = (shiftVal & ~(0x1FU)) >> 4U;
shiftVal &= 0x0001FU;
maskVal = (uint32_t)MEMCFG_XACCPROTX_M << shiftVal;
regVal = protectMode << shiftVal;
//
// Write the access protection mode into the appropriate field
//
EALLOW;
switch(memSection & MEMCFG_SECT_TYPE_MASK)
{
case MEMCFG_SECT_TYPE_D:
HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) &= ~maskVal;
HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) |= regVal;
break;
case MEMCFG_SECT_TYPE_LS:
HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) &= ~maskVal;
HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) |= regVal;
break;
case MEMCFG_SECT_TYPE_GS:
HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) &= ~maskVal;
HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) |= regVal;
break;
default:
//
// Do nothing. Invalid memSection.
//
break;
}
EDIS;
}
//*****************************************************************************
//
// MemCfg_setLSRAMControllerSel
//
//*****************************************************************************
void
MemCfg_setLSRAMControllerSel(uint32_t ramSection,
MemCfg_LSRAMControllerSel controllerSel)
{
uint32_t shiftVal;
uint32_t temp;
//
// Check the arguments.
//
ASSERT((ramSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS);
//
// Calculate how far the controller select value needs to be shifted. Each
// section number is represented by a bit in the lower word of ramSection
// and 2 bits in the corresponding MSEL register.
//
shiftVal = 0U;
temp = MEMCFG_SECT_NUM_MASK & ramSection;
while(temp != 1U)
{
temp = temp >> 1U;
shiftVal += 2U;
}
//
// Write the controller select setting into the appropriate field
//
EALLOW;
HWREG(MEMCFG_BASE + MEMCFG_O_LSXMSEL) =
(HWREG(MEMCFG_BASE + MEMCFG_O_LSXMSEL) &
~((uint32_t)MEMCFG_LSXMSEL_MSEL_LS0_M << shiftVal)) |
((uint32_t)controllerSel << shiftVal);
EDIS;
}
//*****************************************************************************
//
// MemCfg_setGSRAMControllerSel
//
//*****************************************************************************
void
MemCfg_setGSRAMControllerSel(uint32_t ramSections,
MemCfg_GSRAMControllerSel controllerSel)
{
uint32_t sectionNum;
//
// Check the arguments.
//
ASSERT((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS);
//
// We only need the section number bits for this function.
//
sectionNum = ramSections & MEMCFG_SECT_NUM_MASK;
//
// Write the controller select setting into the appropriate field.
//
EALLOW;
if(controllerSel == MEMCFG_GSRAMCONTROLLER_CPU1)
{
HWREG(MEMCFG_BASE + MEMCFG_O_GSXMSEL) &= ~sectionNum;
}
else
{
HWREG(MEMCFG_BASE + MEMCFG_O_GSXMSEL) |= sectionNum;
}
EDIS;
}
//*****************************************************************************
//
// MemCfg_setTestMode
//
//*****************************************************************************
void
MemCfg_setTestMode(uint32_t memSection, MemCfg_TestMode testMode)
{
uint32_t shiftVal = 0U;
uint32_t maskVal;
uint32_t regVal;
uint32_t sectionNum;
//
// Check the arguments.
//
ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) ||
((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG));
//
// Calculate how far the protect mode value needs to be shifted. Each
// section number is represented by a bit in the lower word of memSection
// and 2 bits in the corresponding TEST register.
//
sectionNum = memSection & MEMCFG_SECT_NUM_MASK;
while(sectionNum != 1U)
{
sectionNum = sectionNum >> 1U;
shiftVal += 2U;
}
maskVal = (uint32_t)MEMCFG_XTEST_M << shiftVal;
regVal = (uint32_t)testMode << shiftVal;
//
// Write the test mode into the appropriate field
//
EALLOW;
switch(memSection & MEMCFG_SECT_TYPE_MASK)
{
case MEMCFG_SECT_TYPE_D:
HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) &= ~maskVal;
HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) |= regVal;
break;
case MEMCFG_SECT_TYPE_LS:
HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) &= ~maskVal;
HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) |= regVal;
break;
case MEMCFG_SECT_TYPE_GS:
HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) &= ~maskVal;
HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) |= regVal;
break;
case MEMCFG_SECT_TYPE_MSG:
HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) &= ~maskVal;
HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) |= regVal;
break;
default:
//
// Do nothing. Invalid memSection.
//
break;
}
EDIS;
}
//*****************************************************************************
//
// MemCfg_initSections
//
//*****************************************************************************
void
MemCfg_initSections(uint32_t ramSections)
{
//
// Check the arguments.
//
ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) ||
((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) ||
(ramSections == MEMCFG_SECT_ALL));
//
// Set the bit in the various initialization registers that starts
// initialization.
//
EALLOW;
switch(ramSections & MEMCFG_SECT_TYPE_MASK)
{
case MEMCFG_SECT_TYPE_D:
HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT) |= MEMCFG_SECT_NUM_MASK &
ramSections;
break;
case MEMCFG_SECT_TYPE_LS:
HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT) |= MEMCFG_SECT_NUM_MASK &
ramSections;
break;
case MEMCFG_SECT_TYPE_GS:
HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT) |= MEMCFG_SECT_NUM_MASK &
ramSections;
break;
case MEMCFG_SECT_TYPE_MSG:
HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK &
ramSections;
break;
case MEMCFG_SECT_TYPE_MASK:
//
// Initialize all sections.
//
HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT) |= MEMCFG_SECT_NUM_MASK &
MEMCFG_SECT_DX_ALL;
HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT) |= MEMCFG_SECT_NUM_MASK &
MEMCFG_SECT_LSX_ALL;
HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT) |= MEMCFG_SECT_NUM_MASK &
MEMCFG_SECT_GSX_ALL;
HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK &
MEMCFG_SECT_MSGX_ALL;
break;
default:
//
// Do nothing. Invalid ramSections. Make sure you aren't OR-ing
// values for two different types of RAM.
//
break;
}
EDIS;
}
//*****************************************************************************
//
// MemCfg_getInitStatus
//
//*****************************************************************************
bool
MemCfg_getInitStatus(uint32_t ramSections)
{
uint32_t status;
//
// Check the arguments.
//
ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) ||
((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) ||
((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) ||
((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) ||
(ramSections == MEMCFG_SECT_ALL));
//
// Read registers containing the initialization complete status.
//
switch(ramSections & MEMCFG_SECT_TYPE_MASK)
{
case MEMCFG_SECT_TYPE_D:
status = HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE);
break;
case MEMCFG_SECT_TYPE_LS:
status = HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE);
break;
case MEMCFG_SECT_TYPE_GS:
status = HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE);
break;
case MEMCFG_SECT_TYPE_MSG:
status = HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE);
break;
case MEMCFG_SECT_TYPE_MASK:
//
// Return the overall status.
//
if((HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE) ==
(MEMCFG_SECT_DX_ALL & MEMCFG_SECT_NUM_MASK)) &&
(HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE) ==
(MEMCFG_SECT_LSX_ALL & MEMCFG_SECT_NUM_MASK)) &&
(HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE) ==
(MEMCFG_SECT_GSX_ALL & MEMCFG_SECT_NUM_MASK)) &&
(HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE) ==
(MEMCFG_SECT_MSGX_ALL & MEMCFG_SECT_NUM_MASK)))
{
status = MEMCFG_SECT_NUM_MASK;
}
else
{
status = 0U;
}
break;
default:
//
// Invalid ramSections. Make sure you aren't OR-ing values for two
// different types of RAM.
//
status = 0U;
break;
}
return((ramSections & status) == (ramSections & MEMCFG_SECT_NUM_MASK));
}
//*****************************************************************************
//
// MemCfg_getViolationAddress
//
//*****************************************************************************
uint32_t
MemCfg_getViolationAddress(uint32_t intFlag)
{
uint32_t address;
uint32_t stsNumber;
//
// Calculate the the address of the desired violation address register.
//
if((intFlag & MEMCFG_MVIOL_MASK) != 0U)
{
stsNumber = intFlag >> MEMCFG_MVIOL_SHIFT;
address = ACCESSPROTECTION_BASE + MEMCFG_O_MCPUFAVADDR;
}
else
{
stsNumber = intFlag;
address = ACCESSPROTECTION_BASE + MEMCFG_O_NMCPURDAVADDR;
}
while(stsNumber > 1U)
{
stsNumber = stsNumber >> 1U;
address += (uint32_t)(MEMCFG_O_NMCPUWRAVADDR - MEMCFG_O_NMCPURDAVADDR);
}
//
// Read and return the access violation address at the calculated location.
//
return(HWREG(address));
}
//*****************************************************************************
//
// MemCfg_getCorrErrorAddress
//
//*****************************************************************************
uint32_t
MemCfg_getCorrErrorAddress(uint32_t stsFlag)
{
//
// Check the arguments.
//
if(stsFlag != MEMCFG_CERR_CPUREAD)
{
//
// Currently, the only correctable error address that can be read
// from a register is one for a CPU read error (MEMCFG_CERR_CPUREAD).
// For the sake of keeping this function portable to possible future
// devices with other error types, it still takes a stsFlag parameter.
//
ASSERT((bool)false);
}
//
// Read and return the error address.
//
return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CCPUREADDR));
}
//*****************************************************************************
//
// MemCfg_getUncorrErrorAddress
//
//*****************************************************************************
uint32_t
MemCfg_getUncorrErrorAddress(uint32_t stsFlag)
{
uint32_t address;
uint32_t temp;
//
// Calculate the the address of the desired error address register.
//
address = MEMORYERROR_BASE + MEMCFG_O_UCCPUREADDR;
temp = stsFlag;
while(temp > 1U)
{
temp = temp >> 1U;
address += (uint32_t)(MEMCFG_O_UCDMAREADDR - MEMCFG_O_UCCPUREADDR);
}
//
// Read and return the error address at the calculated location.
//
return(HWREG(address));
}
28379d_P_SFRA/device/driverlib/memcfg.h
+1266
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28379d_P_SFRA/device/driverlib/pin_map.h
+894
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@@ -0,0 +1,894 @@
//###########################################################################
//
// FILE: pin_map.h
//
// TITLE: Definitions of pin mux info for gpio.c.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef __PIN_MAP_H__
#define __PIN_MAP_H__
//*****************************************************************************
// 0x00000003 = MUX register value
// 0x0000000C = GMUX register value
// 0x0000FF00 = Shift amount within mux registers
// 0xFFFF0000 = Offset of MUX register
//*****************************************************************************
#define GPIO_0_GPIO0 0x00060000U
#define GPIO_0_EPWM1A 0x00060001U
#define GPIO_0_SDAA 0x00060006U
#define GPIO_1_GPIO1 0x00060200U
#define GPIO_1_EPWM1B 0x00060201U
#define GPIO_1_MFSRB 0x00060203U
#define GPIO_1_SCLA 0x00060206U
#define GPIO_2_GPIO2 0x00060400U
#define GPIO_2_EPWM2A 0x00060401U
#define GPIO_2_OUTPUTXBAR1 0x00060405U
#define GPIO_2_SDAB 0x00060406U
#define GPIO_3_GPIO3 0x00060600U
#define GPIO_3_EPWM2B 0x00060601U
#define GPIO_3_OUTPUTXBAR2 0x00060602U
#define GPIO_3_MCLKRB 0x00060603U
#define GPIO_3_SCLB 0x00060606U
#define GPIO_4_GPIO4 0x00060800U
#define GPIO_4_EPWM3A 0x00060801U
#define GPIO_4_OUTPUTXBAR3 0x00060805U
#define GPIO_4_CANTXA 0x00060806U
#define GPIO_5_GPIO5 0x00060A00U
#define GPIO_5_EPWM3B 0x00060A01U
#define GPIO_5_MFSRA 0x00060A02U
#define GPIO_5_OUTPUTXBAR3 0x00060A03U
#define GPIO_5_CANRXA 0x00060A06U
#define GPIO_6_GPIO6 0x00060C00U
#define GPIO_6_EPWM4A 0x00060C01U
#define GPIO_6_OUTPUTXBAR4 0x00060C02U
#define GPIO_6_EPWMSYNCO 0x00060C03U
#define GPIO_6_EQEP3A 0x00060C05U
#define GPIO_6_CANTXB 0x00060C06U
#define GPIO_7_GPIO7 0x00060E00U
#define GPIO_7_EPWM4B 0x00060E01U
#define GPIO_7_MCLKRA 0x00060E02U
#define GPIO_7_OUTPUTXBAR5 0x00060E03U
#define GPIO_7_EQEP3B 0x00060E05U
#define GPIO_7_CANRXB 0x00060E06U
#define GPIO_8_GPIO8 0x00061000U
#define GPIO_8_EPWM5A 0x00061001U
#define GPIO_8_CANTXB 0x00061002U
#define GPIO_8_ADCSOCAO 0x00061003U
#define GPIO_8_EQEP3S 0x00061005U
#define GPIO_8_SCITXDA 0x00061006U
#define GPIO_9_GPIO9 0x00061200U
#define GPIO_9_EPWM5B 0x00061201U
#define GPIO_9_SCITXDB 0x00061202U
#define GPIO_9_OUTPUTXBAR6 0x00061203U
#define GPIO_9_EQEP3I 0x00061205U
#define GPIO_9_SCIRXDA 0x00061206U
#define GPIO_10_GPIO10 0x00061400U
#define GPIO_10_EPWM6A 0x00061401U
#define GPIO_10_CANRXB 0x00061402U
#define GPIO_10_ADCSOCBO 0x00061403U
#define GPIO_10_EQEP1A 0x00061405U
#define GPIO_10_SCITXDB 0x00061406U
#define GPIO_10_UPP_WAIT 0x0006140FU
#define GPIO_11_GPIO11 0x00061600U
#define GPIO_11_EPWM6B 0x00061601U
#define GPIO_11_SCIRXDB 0x00061602U
#define GPIO_11_OUTPUTXBAR7 0x00061603U
#define GPIO_11_EQEP1B 0x00061605U
#define GPIO_11_UPP_STRT 0x0006160FU
#define GPIO_12_GPIO12 0x00061800U
#define GPIO_12_EPWM7A 0x00061801U
#define GPIO_12_CANTXB 0x00061802U
#define GPIO_12_MDXB 0x00061803U
#define GPIO_12_EQEP1S 0x00061805U
#define GPIO_12_SCITXDC 0x00061806U
#define GPIO_12_UPP_ENA 0x0006180FU
#define GPIO_13_GPIO13 0x00061A00U
#define GPIO_13_EPWM7B 0x00061A01U
#define GPIO_13_CANRXB 0x00061A02U
#define GPIO_13_MDRB 0x00061A03U
#define GPIO_13_EQEP1I 0x00061A05U
#define GPIO_13_SCIRXDC 0x00061A06U
#define GPIO_13_UPP_D7 0x00061A0FU
#define GPIO_14_GPIO14 0x00061C00U
#define GPIO_14_EPWM8A 0x00061C01U
#define GPIO_14_SCITXDB 0x00061C02U
#define GPIO_14_MCLKXB 0x00061C03U
#define GPIO_14_OUTPUTXBAR3 0x00061C06U
#define GPIO_14_UPP_D6 0x00061C0FU
#define GPIO_15_GPIO15 0x00061E00U
#define GPIO_15_EPWM8B 0x00061E01U
#define GPIO_15_SCIRXDB 0x00061E02U
#define GPIO_15_MFSXB 0x00061E03U
#define GPIO_15_OUTPUTXBAR4 0x00061E06U
#define GPIO_15_UPP_D5 0x00061E0FU
#define GPIO_16_GPIO16 0x00080000U
#define GPIO_16_SPISIMOA 0x00080001U
#define GPIO_16_CANTXB 0x00080002U
#define GPIO_16_OUTPUTXBAR7 0x00080003U
#define GPIO_16_EPWM9A 0x00080005U
#define GPIO_16_SD1_D1 0x00080007U
#define GPIO_16_UPP_D4 0x0008000FU
#define GPIO_17_GPIO17 0x00080200U
#define GPIO_17_SPISOMIA 0x00080201U
#define GPIO_17_CANRXB 0x00080202U
#define GPIO_17_OUTPUTXBAR8 0x00080203U
#define GPIO_17_EPWM9B 0x00080205U
#define GPIO_17_SD1_C1 0x00080207U
#define GPIO_17_UPP_D3 0x0008020FU
#define GPIO_18_GPIO18 0x00080400U
#define GPIO_18_SPICLKA 0x00080401U
#define GPIO_18_SCITXDB 0x00080402U
#define GPIO_18_CANRXA 0x00080403U
#define GPIO_18_EPWM10A 0x00080405U
#define GPIO_18_SD1_D2 0x00080407U
#define GPIO_18_UPP_D2 0x0008040FU
#define GPIO_19_GPIO19 0x00080600U
#define GPIO_19_SPISTEA 0x00080601U
#define GPIO_19_SCIRXDB 0x00080602U
#define GPIO_19_CANTXA 0x00080603U
#define GPIO_19_EPWM10B 0x00080605U
#define GPIO_19_SD1_C2 0x00080607U
#define GPIO_19_UPP_D1 0x0008060FU
#define GPIO_20_GPIO20 0x00080800U
#define GPIO_20_EQEP1A 0x00080801U
#define GPIO_20_MDXA 0x00080802U
#define GPIO_20_CANTXB 0x00080803U
#define GPIO_20_EPWM11A 0x00080805U
#define GPIO_20_SD1_D3 0x00080807U
#define GPIO_20_UPP_D0 0x0008080FU
#define GPIO_21_GPIO21 0x00080A00U
#define GPIO_21_EQEP1B 0x00080A01U
#define GPIO_21_MDRA 0x00080A02U
#define GPIO_21_CANRXB 0x00080A03U
#define GPIO_21_EPWM11B 0x00080A05U
#define GPIO_21_SD1_C3 0x00080A07U
#define GPIO_21_UPP_CLK 0x00080A0FU
#define GPIO_22_GPIO22 0x00080C00U
#define GPIO_22_EQEP1S 0x00080C01U
#define GPIO_22_MCLKXA 0x00080C02U
#define GPIO_22_SCITXDB 0x00080C03U
#define GPIO_22_EPWM12A 0x00080C05U
#define GPIO_22_SPICLKB 0x00080C06U
#define GPIO_22_SD1_D4 0x00080C07U
#define GPIO_23_GPIO23 0x00080E00U
#define GPIO_23_EQEP1I 0x00080E01U
#define GPIO_23_MFSXA 0x00080E02U
#define GPIO_23_SCIRXDB 0x00080E03U
#define GPIO_23_EPWM12B 0x00080E05U
#define GPIO_23_SPISTEB 0x00080E06U
#define GPIO_23_SD1_C4 0x00080E07U
#define GPIO_24_GPIO24 0x00081000U
#define GPIO_24_OUTPUTXBAR1 0x00081001U
#define GPIO_24_EQEP2A 0x00081002U
#define GPIO_24_MDXB 0x00081003U
#define GPIO_24_SPISIMOB 0x00081006U
#define GPIO_24_SD2_D1 0x00081007U
#define GPIO_25_GPIO25 0x00081200U
#define GPIO_25_OUTPUTXBAR2 0x00081201U
#define GPIO_25_EQEP2B 0x00081202U
#define GPIO_25_MDRB 0x00081203U
#define GPIO_25_SPISOMIB 0x00081206U
#define GPIO_25_SD2_C1 0x00081207U
#define GPIO_26_GPIO26 0x00081400U
#define GPIO_26_OUTPUTXBAR3 0x00081401U
#define GPIO_26_EQEP2I 0x00081402U
#define GPIO_26_MCLKXB 0x00081403U
#define GPIO_26_SPICLKB 0x00081406U
#define GPIO_26_SD2_D2 0x00081407U
#define GPIO_27_GPIO27 0x00081600U
#define GPIO_27_OUTPUTXBAR4 0x00081601U
#define GPIO_27_EQEP2S 0x00081602U
#define GPIO_27_MFSXB 0x00081603U
#define GPIO_27_SPISTEB 0x00081606U
#define GPIO_27_SD2_C2 0x00081607U
#define GPIO_28_GPIO28 0x00081800U
#define GPIO_28_SCIRXDA 0x00081801U
#define GPIO_28_EM1CS4N 0x00081802U
#define GPIO_28_OUTPUTXBAR5 0x00081805U
#define GPIO_28_EQEP3A 0x00081806U
#define GPIO_28_SD2_D3 0x00081807U
#define GPIO_29_GPIO29 0x00081A00U
#define GPIO_29_SCITXDA 0x00081A01U
#define GPIO_29_EM1SDCKE 0x00081A02U
#define GPIO_29_OUTPUTXBAR6 0x00081A05U
#define GPIO_29_EQEP3B 0x00081A06U
#define GPIO_29_SD2_C3 0x00081A07U
#define GPIO_30_GPIO30 0x00081C00U
#define GPIO_30_CANRXA 0x00081C01U
#define GPIO_30_EM1CLK 0x00081C02U
#define GPIO_30_OUTPUTXBAR7 0x00081C05U
#define GPIO_30_EQEP3S 0x00081C06U
#define GPIO_30_SD2_D4 0x00081C07U
#define GPIO_31_GPIO31 0x00081E00U
#define GPIO_31_CANTXA 0x00081E01U
#define GPIO_31_EM1WEN 0x00081E02U
#define GPIO_31_OUTPUTXBAR8 0x00081E05U
#define GPIO_31_EQEP3I 0x00081E06U
#define GPIO_31_SD2_C4 0x00081E07U
#define GPIO_32_GPIO32 0x00460000U
#define GPIO_32_SDAA 0x00460001U
#define GPIO_32_EM1CS0N 0x00460002U
#define GPIO_33_GPIO33 0x00460200U
#define GPIO_33_SCLA 0x00460201U
#define GPIO_33_EM1RNW 0x00460202U
#define GPIO_34_GPIO34 0x00460400U
#define GPIO_34_OUTPUTXBAR1 0x00460401U
#define GPIO_34_EM1CS2N 0x00460402U
#define GPIO_34_SDAB 0x00460406U
#define GPIO_34_OFSD_2_N 0x0046040FU
#define GPIO_35_GPIO35 0x00460600U
#define GPIO_35_SCIRXDA 0x00460601U
#define GPIO_35_EM1CS3N 0x00460602U
#define GPIO_35_SCLB 0x00460606U
#define GPIO_35_IID 0x0046060FU
#define GPIO_36_GPIO36 0x00460800U
#define GPIO_36_SCITXDA 0x00460801U
#define GPIO_36_EM1WAIT 0x00460802U
#define GPIO_36_CANRXA 0x00460806U
#define GPIO_36_ISESSEND 0x0046080FU
#define GPIO_37_GPIO37 0x00460A00U
#define GPIO_37_OUTPUTXBAR2 0x00460A01U
#define GPIO_37_EM1OEN 0x00460A02U
#define GPIO_37_CANTXA 0x00460A06U
#define GPIO_37_IAVALID 0x00460A0FU
#define GPIO_38_GPIO38 0x00460C00U
#define GPIO_38_EM1A0 0x00460C02U
#define GPIO_38_SCITXDC 0x00460C05U
#define GPIO_38_CANTXB 0x00460C06U
#define GPIO_39_GPIO39 0x00460E00U
#define GPIO_39_EM1A1 0x00460E02U
#define GPIO_39_SCIRXDC 0x00460E05U
#define GPIO_39_CANRXB 0x00460E06U
#define GPIO_40_GPIO40 0x00461000U
#define GPIO_40_EM1A2 0x00461002U
#define GPIO_40_SDAB 0x00461006U
#define GPIO_41_GPIO41 0x00461200U
#define GPIO_41_EM1A3 0x00461202U
#define GPIO_41_EMU1 0x00461203U
#define GPIO_41_SCLB 0x00461206U
#define GPIO_42_GPIO42 0x00461400U
#define GPIO_42_SDAA 0x00461406U
#define GPIO_42_SCITXDA 0x0046140FU
#define GPIO_43_GPIO43 0x00461600U
#define GPIO_43_SCLA 0x00461606U
#define GPIO_43_SCIRXDA 0x0046160FU
#define GPIO_44_GPIO44 0x00461800U
#define GPIO_44_EM1A4 0x00461802U
#define GPIO_44_IXRCV 0x0046180FU
#define GPIO_45_GPIO45 0x00461A00U
#define GPIO_45_EM1A5 0x00461A02U
#define GPIO_45_IDM 0x00461A0FU
#define GPIO_46_GPIO46 0x00461C00U
#define GPIO_46_EM1A6 0x00461C02U
#define GPIO_46_SCIRXDD 0x00461C06U
#define GPIO_46_IDP 0x00461C0FU
#define GPIO_47_GPIO47 0x00461E00U
#define GPIO_47_EM1A7 0x00461E02U
#define GPIO_47_SCITXDD 0x00461E06U
#define GPIO_47_OFSD_1_N 0x00461E0FU
#define GPIO_48_GPIO48 0x00480000U
#define GPIO_48_OUTPUTXBAR3 0x00480001U
#define GPIO_48_EM1A8 0x00480002U
#define GPIO_48_SCITXDA 0x00480006U
#define GPIO_48_SD1_D1 0x00480007U
#define GPIO_49_GPIO49 0x00480200U
#define GPIO_49_OUTPUTXBAR4 0x00480201U
#define GPIO_49_EM1A9 0x00480202U
#define GPIO_49_SCIRXDA 0x00480206U
#define GPIO_49_SD1_C1 0x00480207U
#define GPIO_50_GPIO50 0x00480400U
#define GPIO_50_EQEP1A 0x00480401U
#define GPIO_50_EM1A10 0x00480402U
#define GPIO_50_SPISIMOC 0x00480406U
#define GPIO_50_SD1_D2 0x00480407U
#define GPIO_51_GPIO51 0x00480600U
#define GPIO_51_EQEP1B 0x00480601U
#define GPIO_51_EM1A11 0x00480602U
#define GPIO_51_SPISOMIC 0x00480606U
#define GPIO_51_SD1_C2 0x00480607U
#define GPIO_52_GPIO52 0x00480800U
#define GPIO_52_EQEP1S 0x00480801U
#define GPIO_52_EM1A12 0x00480802U
#define GPIO_52_SPICLKC 0x00480806U
#define GPIO_52_SD1_D3 0x00480807U
#define GPIO_53_GPIO53 0x00480A00U
#define GPIO_53_EQEP1I 0x00480A01U
#define GPIO_53_EM1D31 0x00480A02U
#define GPIO_53_EM2D15 0x00480A03U
#define GPIO_53_SPISTEC 0x00480A06U
#define GPIO_53_SD1_C3 0x00480A07U
#define GPIO_54_GPIO54 0x00480C00U
#define GPIO_54_SPISIMOA 0x00480C01U
#define GPIO_54_EM1D30 0x00480C02U
#define GPIO_54_EM2D14 0x00480C03U
#define GPIO_54_EQEP2A 0x00480C05U
#define GPIO_54_SCITXDB 0x00480C06U
#define GPIO_54_SD1_D4 0x00480C07U
#define GPIO_55_GPIO55 0x00480E00U
#define GPIO_55_SPISOMIA 0x00480E01U
#define GPIO_55_EM1D29 0x00480E02U
#define GPIO_55_EM2D13 0x00480E03U
#define GPIO_55_EQEP2B 0x00480E05U
#define GPIO_55_SCIRXDB 0x00480E06U
#define GPIO_55_SD1_C4 0x00480E07U
#define GPIO_56_GPIO56 0x00481000U
#define GPIO_56_SPICLKA 0x00481001U
#define GPIO_56_EM1D28 0x00481002U
#define GPIO_56_EM2D12 0x00481003U
#define GPIO_56_EQEP2S 0x00481005U
#define GPIO_56_SCITXDC 0x00481006U
#define GPIO_56_SD2_D1 0x00481007U
#define GPIO_57_GPIO57 0x00481200U
#define GPIO_57_SPISTEA 0x00481201U
#define GPIO_57_EM1D27 0x00481202U
#define GPIO_57_EM2D11 0x00481203U
#define GPIO_57_EQEP2I 0x00481205U
#define GPIO_57_SCIRXDC 0x00481206U
#define GPIO_57_SD2_C1 0x00481207U
#define GPIO_58_GPIO58 0x00481400U
#define GPIO_58_MCLKRA 0x00481401U
#define GPIO_58_EM1D26 0x00481402U
#define GPIO_58_EM2D10 0x00481403U
#define GPIO_58_OUTPUTXBAR1 0x00481405U
#define GPIO_58_SPICLKB 0x00481406U
#define GPIO_58_SD2_D2 0x00481407U
#define GPIO_58_SPISIMOA 0x0048140FU
#define GPIO_59_GPIO59 0x00481600U
#define GPIO_59_MFSRA 0x00481601U
#define GPIO_59_EM1D25 0x00481602U
#define GPIO_59_EM2D9 0x00481603U
#define GPIO_59_OUTPUTXBAR2 0x00481605U
#define GPIO_59_SPISTEB 0x00481606U
#define GPIO_59_SD2_C2 0x00481607U
#define GPIO_59_SPISOMIA 0x0048160FU
#define GPIO_60_GPIO60 0x00481800U
#define GPIO_60_MCLKRB 0x00481801U
#define GPIO_60_EM1D24 0x00481802U
#define GPIO_60_EM2D8 0x00481803U
#define GPIO_60_OUTPUTXBAR3 0x00481805U
#define GPIO_60_SPISIMOB 0x00481806U
#define GPIO_60_SD2_D3 0x00481807U
#define GPIO_60_SPICLKA 0x0048180FU
#define GPIO_61_GPIO61 0x00481A00U
#define GPIO_61_MFSRB 0x00481A01U
#define GPIO_61_EM1D23 0x00481A02U
#define GPIO_61_EM2D7 0x00481A03U
#define GPIO_61_OUTPUTXBAR4 0x00481A05U
#define GPIO_61_SPISOMIB 0x00481A06U
#define GPIO_61_SD2_C3 0x00481A07U
#define GPIO_61_SPISTEA 0x00481A0FU
#define GPIO_62_GPIO62 0x00481C00U
#define GPIO_62_SCIRXDC 0x00481C01U
#define GPIO_62_EM1D22 0x00481C02U
#define GPIO_62_EM2D6 0x00481C03U
#define GPIO_62_EQEP3A 0x00481C05U
#define GPIO_62_CANRXA 0x00481C06U
#define GPIO_62_SD2_D4 0x00481C07U
#define GPIO_63_GPIO63 0x00481E00U
#define GPIO_63_SCITXDC 0x00481E01U
#define GPIO_63_EM1D21 0x00481E02U
#define GPIO_63_EM2D5 0x00481E03U
#define GPIO_63_EQEP3B 0x00481E05U
#define GPIO_63_CANTXA 0x00481E06U
#define GPIO_63_SD2_C4 0x00481E07U
#define GPIO_63_SPISIMOB 0x00481E0FU
#define GPIO_64_GPIO64 0x00860000U
#define GPIO_64_EM1D20 0x00860002U
#define GPIO_64_EM2D4 0x00860003U
#define GPIO_64_EQEP3S 0x00860005U
#define GPIO_64_SCIRXDA 0x00860006U
#define GPIO_64_SPISOMIB 0x0086000FU
#define GPIO_65_GPIO65 0x00860200U
#define GPIO_65_EM1D19 0x00860202U
#define GPIO_65_EM2D3 0x00860203U
#define GPIO_65_EQEP3I 0x00860205U
#define GPIO_65_SCITXDA 0x00860206U
#define GPIO_65_SPICLKB 0x0086020FU
#define GPIO_66_GPIO66 0x00860400U
#define GPIO_66_EM1D18 0x00860402U
#define GPIO_66_EM2D2 0x00860403U
#define GPIO_66_SDAB 0x00860406U
#define GPIO_66_SPISTEB 0x0086040FU
#define GPIO_67_GPIO67 0x00860600U
#define GPIO_67_EM1D17 0x00860602U
#define GPIO_67_EM2D1 0x00860603U
#define GPIO_68_GPIO68 0x00860800U
#define GPIO_68_EM1D16 0x00860802U
#define GPIO_68_EM2D0 0x00860803U
#define GPIO_69_GPIO69 0x00860A00U
#define GPIO_69_EM1D15 0x00860A02U
#define GPIO_69_EMU0 0x00860A03U
#define GPIO_69_SCLB 0x00860A06U
#define GPIO_69_SPISIMOC 0x00860A0FU
#define GPIO_70_GPIO70 0x00860C00U
#define GPIO_70_EM1D14 0x00860C02U
#define GPIO_70_EMU0 0x00860C03U
#define GPIO_70_CANRXA 0x00860C05U
#define GPIO_70_SCITXDB 0x00860C06U
#define GPIO_70_SPISOMIC 0x00860C0FU
#define GPIO_71_GPIO71 0x00860E00U
#define GPIO_71_EM1D13 0x00860E02U
#define GPIO_71_EMU1 0x00860E03U
#define GPIO_71_CANTXA 0x00860E05U
#define GPIO_71_SCIRXDB 0x00860E06U
#define GPIO_71_SPICLKC 0x00860E0FU
#define GPIO_72_GPIO72 0x00861000U
#define GPIO_72_EM1D12 0x00861002U
#define GPIO_72_CANTXB 0x00861005U
#define GPIO_72_SCITXDC 0x00861006U
#define GPIO_72_SPISTEC 0x0086100FU
#define GPIO_73_GPIO73 0x00861200U
#define GPIO_73_EM1D11 0x00861202U
#define GPIO_73_XCLKOUT 0x00861203U
#define GPIO_73_CANRXB 0x00861205U
#define GPIO_73_SCIRXDC 0x00861206U
#define GPIO_74_GPIO74 0x00861400U
#define GPIO_74_EM1D10 0x00861402U
#define GPIO_75_GPIO75 0x00861600U
#define GPIO_75_EM1D9 0x00861602U
#define GPIO_76_GPIO76 0x00861800U
#define GPIO_76_EM1D8 0x00861802U
#define GPIO_76_SCITXDD 0x00861806U
#define GPIO_77_GPIO77 0x00861A00U
#define GPIO_77_EM1D7 0x00861A02U
#define GPIO_77_SCIRXDD 0x00861A06U
#define GPIO_78_GPIO78 0x00861C00U
#define GPIO_78_EM1D6 0x00861C02U
#define GPIO_78_EQEP2A 0x00861C06U
#define GPIO_79_GPIO79 0x00861E00U
#define GPIO_79_EM1D5 0x00861E02U
#define GPIO_79_EQEP2B 0x00861E06U
#define GPIO_80_GPIO80 0x00880000U
#define GPIO_80_EM1D4 0x00880002U
#define GPIO_80_EQEP2S 0x00880006U
#define GPIO_81_GPIO81 0x00880200U
#define GPIO_81_EM1D3 0x00880202U
#define GPIO_81_EQEP2I 0x00880206U
#define GPIO_82_GPIO82 0x00880400U
#define GPIO_82_EM1D2 0x00880402U
#define GPIO_83_GPIO83 0x00880600U
#define GPIO_83_EM1D1 0x00880602U
#define GPIO_84_GPIO84 0x00880800U
#define GPIO_84_SCITXDA 0x00880805U
#define GPIO_84_MDXB 0x00880806U
#define GPIO_84_MDXA 0x0088080FU
#define GPIO_85_GPIO85 0x00880A00U
#define GPIO_85_EM1D0 0x00880A02U
#define GPIO_85_SCIRXDA 0x00880A05U
#define GPIO_85_MDRB 0x00880A06U
#define GPIO_85_MDRA 0x00880A0FU
#define GPIO_86_GPIO86 0x00880C00U
#define GPIO_86_EM1A13 0x00880C02U
#define GPIO_86_EM1CAS 0x00880C03U
#define GPIO_86_SCITXDB 0x00880C05U
#define GPIO_86_MCLKXB 0x00880C06U
#define GPIO_86_MCLKXA 0x00880C0FU
#define GPIO_87_GPIO87 0x00880E00U
#define GPIO_87_EM1A14 0x00880E02U
#define GPIO_87_EM1RAS 0x00880E03U
#define GPIO_87_SCIRXDB 0x00880E05U
#define GPIO_87_MFSXB 0x00880E06U
#define GPIO_87_MFSXA 0x00880E0FU
#define GPIO_88_GPIO88 0x00881000U
#define GPIO_88_EM1A15 0x00881002U
#define GPIO_88_EM1DQM0 0x00881003U
#define GPIO_89_GPIO89 0x00881200U
#define GPIO_89_EM1A16 0x00881202U
#define GPIO_89_EM1DQM1 0x00881203U
#define GPIO_89_SCITXDC 0x00881206U
#define GPIO_90_GPIO90 0x00881400U
#define GPIO_90_EM1A17 0x00881402U
#define GPIO_90_EM1DQM2 0x00881403U
#define GPIO_90_SCIRXDC 0x00881406U
#define GPIO_91_GPIO91 0x00881600U
#define GPIO_91_EM1A18 0x00881602U
#define GPIO_91_EM1DQM3 0x00881603U
#define GPIO_91_SDAA 0x00881606U
#define GPIO_92_GPIO92 0x00881800U
#define GPIO_92_EM1A19 0x00881802U
#define GPIO_92_EM1BA1 0x00881803U
#define GPIO_92_SCLA 0x00881806U
#define GPIO_93_GPIO93 0x00881A00U
#define GPIO_93_EM1A20 0x00881A02U
#define GPIO_93_EM1BA0 0x00881A03U
#define GPIO_93_SCITXDD 0x00881A06U
#define GPIO_94_GPIO94 0x00881C00U
#define GPIO_94_EM1A21 0x00881C02U
#define GPIO_94_SCIRXDD 0x00881C06U
#define GPIO_95_GPIO95 0x00881E00U
#define GPIO_96_GPIO96 0x00C60000U
#define GPIO_96_EM2DQM1 0x00C60003U
#define GPIO_96_EQEP1A 0x00C60005U
#define GPIO_97_GPIO97 0x00C60200U
#define GPIO_97_EM2DQM0 0x00C60203U
#define GPIO_97_EQEP1B 0x00C60205U
#define GPIO_98_GPIO98 0x00C60400U
#define GPIO_98_EM2A0 0x00C60403U
#define GPIO_98_EQEP1S 0x00C60405U
#define GPIO_99_GPIO99 0x00C60600U
#define GPIO_99_EM2A1 0x00C60603U
#define GPIO_99_EQEP1I 0x00C60605U
#define GPIO_100_GPIO100 0x00C60800U
#define GPIO_100_EM2A2 0x00C60803U
#define GPIO_100_EQEP2A 0x00C60805U
#define GPIO_100_SPISIMOC 0x00C60806U
#define GPIO_101_GPIO101 0x00C60A00U
#define GPIO_101_EM2A3 0x00C60A03U
#define GPIO_101_EQEP2B 0x00C60A05U
#define GPIO_101_SPISOMIC 0x00C60A06U
#define GPIO_102_GPIO102 0x00C60C00U
#define GPIO_102_EM2A4 0x00C60C03U
#define GPIO_102_EQEP2S 0x00C60C05U
#define GPIO_102_SPICLKC 0x00C60C06U
#define GPIO_103_GPIO103 0x00C60E00U
#define GPIO_103_EM2A5 0x00C60E03U
#define GPIO_103_EQEP2I 0x00C60E05U
#define GPIO_103_SPISTEC 0x00C60E06U
#define GPIO_104_GPIO104 0x00C61000U
#define GPIO_104_SDAA 0x00C61001U
#define GPIO_104_EM2A6 0x00C61003U
#define GPIO_104_EQEP3A 0x00C61005U
#define GPIO_104_SCITXDD 0x00C61006U
#define GPIO_105_GPIO105 0x00C61200U
#define GPIO_105_SCLA 0x00C61201U
#define GPIO_105_EM2A7 0x00C61203U
#define GPIO_105_EQEP3B 0x00C61205U
#define GPIO_105_SCIRXDD 0x00C61206U
#define GPIO_106_GPIO106 0x00C61400U
#define GPIO_106_EM2A8 0x00C61403U
#define GPIO_106_EQEP3S 0x00C61405U
#define GPIO_106_SCITXDC 0x00C61406U
#define GPIO_107_GPIO107 0x00C61600U
#define GPIO_107_EM2A9 0x00C61603U
#define GPIO_107_EQEP3I 0x00C61605U
#define GPIO_107_SCIRXDC 0x00C61606U
#define GPIO_108_GPIO108 0x00C61800U
#define GPIO_108_EM2A10 0x00C61803U
#define GPIO_109_GPIO109 0x00C61A00U
#define GPIO_109_EM2A11 0x00C61A03U
#define GPIO_110_GPIO110 0x00C61C00U
#define GPIO_110_EM2WAIT 0x00C61C03U
#define GPIO_111_GPIO111 0x00C61E00U
#define GPIO_111_EM2BA0 0x00C61E03U
#define GPIO_112_GPIO112 0x00C80000U
#define GPIO_112_EM2BA1 0x00C80003U
#define GPIO_113_GPIO113 0x00C80200U
#define GPIO_113_EM2CAS 0x00C80203U
#define GPIO_114_GPIO114 0x00C80400U
#define GPIO_114_EM2RAS 0x00C80403U
#define GPIO_115_GPIO115 0x00C80600U
#define GPIO_115_EM2CS0N 0x00C80603U
#define GPIO_116_GPIO116 0x00C80800U
#define GPIO_116_EM2CS2N 0x00C80803U
#define GPIO_117_GPIO117 0x00C80A00U
#define GPIO_117_EM2SDCKE 0x00C80A03U
#define GPIO_118_GPIO118 0x00C80C00U
#define GPIO_118_EM2CLK 0x00C80C03U
#define GPIO_119_GPIO119 0x00C80E00U
#define GPIO_119_EM2RNW 0x00C80E03U
#define GPIO_120_GPIO120 0x00C81000U
#define GPIO_120_EM2WEN 0x00C81003U
#define GPIO_120_USB0PFLT 0x00C8100FU
#define GPIO_121_GPIO121 0x00C81200U
#define GPIO_121_EM2OEN 0x00C81203U
#define GPIO_121_USB0EPEN 0x00C8120FU
#define GPIO_122_GPIO122 0x00C81400U
#define GPIO_122_SPISIMOC 0x00C81406U
#define GPIO_122_SD1_D1 0x00C81407U
#define GPIO_122_ODISCHRGVBUS 0x00C8140FU
#define GPIO_123_GPIO123 0x00C81600U
#define GPIO_123_SPISOMIC 0x00C81606U
#define GPIO_123_SD1_C1 0x00C81607U
#define GPIO_123_OCHRGVBUS 0x00C8160FU
#define GPIO_124_GPIO124 0x00C81800U
#define GPIO_124_SPICLKC 0x00C81806U
#define GPIO_124_SD1_D2 0x00C81807U
#define GPIO_124_ODMPULLDN 0x00C8180FU
#define GPIO_125_GPIO125 0x00C81A00U
#define GPIO_125_SPISTEC 0x00C81A06U
#define GPIO_125_SD1_C2 0x00C81A07U
#define GPIO_125_ODPPULLDN 0x00C81A0FU
#define GPIO_126_GPIO126 0x00C81C00U
#define GPIO_126_SD1_D3 0x00C81C07U
#define GPIO_126_OLSD_2_N 0x00C81C0FU
#define GPIO_127_GPIO127 0x00C81E00U
#define GPIO_127_SD1_C3 0x00C81E07U
#define GPIO_127_OLSD_1_N 0x00C81E0FU
#define GPIO_128_GPIO128 0x01060000U
#define GPIO_128_SD1_D4 0x01060007U
#define GPIO_128_OIDPULLUP 0x0106000FU
#define GPIO_129_GPIO129 0x01060200U
#define GPIO_129_SD1_C4 0x01060207U
#define GPIO_129_OSPEED 0x0106020FU
#define GPIO_130_GPIO130 0x01060400U
#define GPIO_130_SD2_D1 0x01060407U
#define GPIO_130_OSUSPEND 0x0106040FU
#define GPIO_131_GPIO131 0x01060600U
#define GPIO_131_SD2_C1 0x01060607U
#define GPIO_131_OOE 0x0106060FU
#define GPIO_132_GPIO132 0x01060800U
#define GPIO_132_SD2_D2 0x01060807U
#define GPIO_132_ODMSE1 0x0106080FU
#define GPIO_133_GPIO133 0x01060A00U
#define GPIO_133_SD2_C2 0x01060A07U
#define GPIO_133_ODPDAT 0x01060A0FU
#define GPIO_134_GPIO134 0x01060C00U
#define GPIO_134_SD2_D3 0x01060C07U
#define GPIO_134_IVBUSVALID 0x01060C0FU
#define GPIO_135_GPIO135 0x01060E00U
#define GPIO_135_SCITXDA 0x01060E06U
#define GPIO_135_SD2_C3 0x01060E07U
#define GPIO_136_GPIO136 0x01061000U
#define GPIO_136_SCIRXDA 0x01061006U
#define GPIO_136_SD2_D4 0x01061007U
#define GPIO_137_GPIO137 0x01061200U
#define GPIO_137_SCITXDB 0x01061206U
#define GPIO_137_SD2_C4 0x01061207U
#define GPIO_138_GPIO138 0x01061400U
#define GPIO_138_SCIRXDB 0x01061406U
#define GPIO_139_GPIO139 0x01061600U
#define GPIO_139_SCIRXDC 0x01061606U
#define GPIO_140_GPIO140 0x01061800U
#define GPIO_140_SCITXDC 0x01061806U
#define GPIO_141_GPIO141 0x01061A00U
#define GPIO_141_SCIRXDD 0x01061A06U
#define GPIO_142_GPIO142 0x01061C00U
#define GPIO_142_SCITXDD 0x01061C06U
#define GPIO_143_GPIO143 0x01061E00U
#define GPIO_144_GPIO144 0x01080000U
#define GPIO_145_GPIO145 0x01080200U
#define GPIO_145_EPWM1A 0x01080201U
#define GPIO_146_GPIO146 0x01080400U
#define GPIO_146_EPWM1B 0x01080401U
#define GPIO_147_GPIO147 0x01080600U
#define GPIO_147_EPWM2A 0x01080601U
#define GPIO_148_GPIO148 0x01080800U
#define GPIO_148_EPWM2B 0x01080801U
#define GPIO_149_GPIO149 0x01080A00U
#define GPIO_149_EPWM3A 0x01080A01U
#define GPIO_150_GPIO150 0x01080C00U
#define GPIO_150_EPWM3B 0x01080C01U
#define GPIO_151_GPIO151 0x01080E00U
#define GPIO_151_EPWM4A 0x01080E01U
#define GPIO_152_GPIO152 0x01081000U
#define GPIO_152_EPWM4B 0x01081001U
#define GPIO_153_GPIO153 0x01081200U
#define GPIO_153_EPWM5A 0x01081201U
#define GPIO_154_GPIO154 0x01081400U
#define GPIO_154_EPWM5B 0x01081401U
#define GPIO_155_GPIO155 0x01081600U
#define GPIO_155_EPWM6A 0x01081601U
#define GPIO_156_GPIO156 0x01081800U
#define GPIO_156_EPWM6B 0x01081801U
#define GPIO_157_GPIO157 0x01081A00U
#define GPIO_157_EPWM7A 0x01081A01U
#define GPIO_158_GPIO158 0x01081C00U
#define GPIO_158_EPWM7B 0x01081C01U
#define GPIO_159_GPIO159 0x01081E00U
#define GPIO_159_EPWM8A 0x01081E01U
#define GPIO_160_GPIO160 0x01460000U
#define GPIO_160_EPWM8B 0x01460001U
#define GPIO_161_GPIO161 0x01460200U
#define GPIO_161_EPWM9A 0x01460201U
#define GPIO_162_GPIO162 0x01460400U
#define GPIO_162_EPWM9B 0x01460401U
#define GPIO_163_GPIO163 0x01460600U
#define GPIO_163_EPWM10A 0x01460601U
#define GPIO_164_GPIO164 0x01460800U
#define GPIO_164_EPWM10B 0x01460801U
#define GPIO_165_GPIO165 0x01460A00U
#define GPIO_165_EPWM11A 0x01460A01U
#define GPIO_166_GPIO166 0x01460C00U
#define GPIO_166_EPWM11B 0x01460C01U
#define GPIO_167_GPIO167 0x01460E00U
#define GPIO_167_EPWM12A 0x01460E01U
#define GPIO_168_GPIO168 0x01461000U
#define GPIO_168_EPWM12B 0x01461001U
#endif // PIN_MAP_H
28379d_P_SFRA/device/driverlib/pin_map_legacy.h
+95
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//###########################################################################
//
// FILE: pin_map.h
//
// TITLE: Legacy definitions of pin mux info for gpio.c.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#ifndef __PIN_MAP_LEGACY_H__
#define __PIN_MAP_LEGACY_H__
#include "pin_map.h"
//*****************************************************************************
// Legacy pinmuxing MACROS - Retained for portability across devices ONLY
// Not recommended for new users
//*****************************************************************************
#define GPIO_16_SD_D1 GPIO_16_SD1_D1
#define GPIO_17_SD_C1 GPIO_17_SD1_C1
#define GPIO_18_SD_D2 GPIO_18_SD1_D2
#define GPIO_19_SD_C2 GPIO_19_SD1_C2
#define GPIO_20_SD_D3 GPIO_20_SD1_D3
#define GPIO_21_SD_C3 GPIO_21_SD1_C3
#define GPIO_22_SD_D4 GPIO_22_SD1_D4
#define GPIO_23_SD_C4 GPIO_23_SD1_C4
#define GPIO_24_SD_D5 GPIO_24_SD2_D1
#define GPIO_25_SD_C5 GPIO_25_SD2_C1
#define GPIO_26_SD_D6 GPIO_26_SD2_D2
#define GPIO_27_SD_C6 GPIO_27_SD2_C2
#define GPIO_28_SD_D7 GPIO_28_SD2_D3
#define GPIO_29_SD_C7 GPIO_29_SD2_C3
#define GPIO_30_SD_D8 GPIO_30_SD2_D4
#define GPIO_31_SD_C8 GPIO_31_SD2_C4
#define GPIO_36_EM1WAIT1 GPIO_36_EM1WAIT
#define GPIO_110_EM2WAIT1 GPIO_110_EM2WAIT
#define GPIO_115_EM2CS0 GPIO_115_EM2CS0N
#define GPIO_116_EM2CS2 GPIO_116_EM2CS2N
#define GPIO_132_ODMSE0 GPIO_132_ODMSE1
#endif // __PIN_MAP_LEGACY_H__
28379d_P_SFRA/device/driverlib/sci.c
+421
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//###########################################################################
//
// FILE: sci.c
//
// TITLE: C28x SCI driver.
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "sci.h"
//*****************************************************************************
//
// SCI_setConfig
//
//*****************************************************************************
void
SCI_setConfig(uint32_t base, uint32_t lspclkHz, uint32_t baud, uint32_t config)
{
uint32_t divider;
//
// Check the arguments.
// Is the required baud rate greater than the maximum rate supported?
//
ASSERT(SCI_isBaseValid(base));
ASSERT(baud != 0U);
ASSERT((baud * 16U) <= lspclkHz);
//
// Stop the SCI.
//
SCI_disableModule(base);
//
// Compute the baud rate divider.
//
divider = ((lspclkHz / (baud * 8U)) - 1U);
//
// Set the baud rate.
//
HWREGH(base + SCI_O_HBAUD) = (divider & 0xFF00U) >> 8U;
HWREGH(base + SCI_O_LBAUD) = divider & 0x00FFU;
//
// Set parity, data length, and number of stop bits.
//
HWREGH(base + SCI_O_CCR) = ((HWREGH(base + SCI_O_CCR) &
~(SCI_CONFIG_PAR_MASK |
SCI_CONFIG_STOP_MASK |
SCI_CONFIG_WLEN_MASK)) | config);
//
// Start the SCI.
//
SCI_enableModule(base);
}
//*****************************************************************************
//
// SCI_writeCharArray
//
//*****************************************************************************
void
SCI_writeCharArray(uint32_t base, const uint16_t * const array,
uint16_t length)
{
//
// Check the arguments.
//
ASSERT(SCI_isBaseValid(base));
uint16_t i;
//
// Check if FIFO enhancement is enabled.
//
if(SCI_isFIFOEnabled(base))
{
//
// FIFO is enabled.
// For loop to write (Blocking) 'length' number of characters
//
for(i = 0U; i < length; i++)
{
//
// Wait until space is available in the transmit FIFO.
//
while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX16)
{
}
//
// Send a char.
//
HWREGH(base + SCI_O_TXBUF) = array[i];
}
}
else
{
//
// FIFO is not enabled.
// For loop to write (Blocking) 'length' number of characters
//
for(i = 0U; i < length; i++)
{
//
// Wait until space is available in the transmit buffer.
//
while(!SCI_isSpaceAvailableNonFIFO(base))
{
}
//
// Send a char.
//
HWREGH(base + SCI_O_TXBUF) = array[i];
}
}
}
//*****************************************************************************
//
// SCI_readCharArray
//
//*****************************************************************************
void
SCI_readCharArray(uint32_t base, uint16_t * const array, uint16_t length)
{
//
// Check the arguments.
//
ASSERT(SCI_isBaseValid(base));
uint16_t i;
//
// Check if FIFO enhancement is enabled.
//
if(SCI_isFIFOEnabled(base))
{
//
// FIFO is enabled.
// For loop to read (Blocking) 'length' number of characters
//
for(i = 0U; i < length; i++)
{
//
// Wait until a character is available in the receive FIFO.
//
while(SCI_getRxFIFOStatus(base) == SCI_FIFO_RX0)
{
}
//
// Return the character from the receive buffer.
//
array[i] = (uint16_t)
(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M);
}
}
else
{
//
// FIFO is not enabled.
// For loop to read (Blocking) 'length' number of characters
//
for(i = 0U; i < length; i++)
{
//
// Wait until a character is available in the receive buffer.
//
while(!SCI_isDataAvailableNonFIFO(base))
{
}
//
// Return the character from the receive buffer.
//
array[i] = (uint16_t)
(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M);
}
}
}
//*****************************************************************************
//
// SCI_enableInterrupt
//
//*****************************************************************************
void
SCI_enableInterrupt(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
ASSERT(SCI_isBaseValid(base));
//
// Enable the specified interrupts.
//
if((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR)
{
HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_RXERRINTENA;
}
if((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT)
{
HWREGH(base + SCI_O_CTL2) |= SCI_CTL2_RXBKINTENA;
}
if((intFlags & SCI_INT_TXRDY) == SCI_INT_TXRDY)
{
HWREGH(base + SCI_O_CTL2) |= SCI_CTL2_TXINTENA;
}
if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF)
{
HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFFIENA;
}
if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF)
{
HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFIENA;
}
}
//*****************************************************************************
//
// SCI_disableInterrupt
//
//*****************************************************************************
void
SCI_disableInterrupt(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
ASSERT(SCI_isBaseValid(base));
//
// Disable the specified interrupts.
//
if((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR)
{
HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_RXERRINTENA;
}
if((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT)
{
HWREGH(base + SCI_O_CTL2) &= ~SCI_CTL2_RXBKINTENA;
}
if((intFlags & SCI_INT_TXRDY) == SCI_INT_TXRDY)
{
HWREGH(base + SCI_O_CTL2) &= ~SCI_CTL2_TXINTENA;
}
if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF)
{
HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_TXFFIENA;
}
if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF)
{
HWREGH(base + SCI_O_FFRX) &= ~SCI_FFRX_RXFFIENA;
}
}
//*****************************************************************************
//
// SCI_getInterruptStatus
//
//*****************************************************************************
uint32_t
SCI_getInterruptStatus(uint32_t base)
{
uint32_t interruptStatus = 0;
//
// Check the arguments.
//
ASSERT(SCI_isBaseValid(base));
//
// Return the interrupt status.
//
if((HWREGH(base + SCI_O_CTL2) & SCI_CTL2_TXRDY) == SCI_CTL2_TXRDY)
{
interruptStatus |= SCI_INT_TXRDY;
}
if((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXERROR) == SCI_RXST_RXERROR)
{
interruptStatus |= SCI_INT_RXERR;
}
if(((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXRDY) == SCI_RXST_RXRDY) ||
((HWREGH(base + SCI_O_RXST) & SCI_RXST_BRKDT) == SCI_RXST_BRKDT))
{
interruptStatus |= SCI_INT_RXRDY_BRKDT;
}
if((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_TXFFINT) == SCI_FFTX_TXFFINT)
{
interruptStatus |= SCI_INT_TXFF;
}
if((HWREGH(base + SCI_O_FFRX) & SCI_FFRX_RXFFINT) == SCI_FFRX_RXFFINT)
{
interruptStatus |= SCI_INT_RXFF;
}
if((HWREGH(base + SCI_O_RXST) & SCI_RXST_FE) == SCI_RXST_FE)
{
interruptStatus |= SCI_INT_FE;
}
if((HWREGH(base + SCI_O_RXST) & SCI_RXST_OE) == SCI_RXST_OE)
{
interruptStatus |= SCI_INT_OE;
}
if((HWREGH(base + SCI_O_RXST) & SCI_RXST_PE) == SCI_RXST_PE)
{
interruptStatus |= SCI_INT_PE;
}
return(interruptStatus);
}
//*****************************************************************************
//
// SCI_clearInterruptStatus
//
//*****************************************************************************
void
SCI_clearInterruptStatus(uint32_t base, uint32_t intFlags)
{
//
// Check the arguments.
//
ASSERT(SCI_isBaseValid(base));
//
// Clear the requested interrupt sources.
//
if(((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR) ||
((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT) ||
((intFlags & SCI_INT_FE) == SCI_INT_FE) ||
((intFlags & SCI_INT_OE) == SCI_INT_OE) ||
((intFlags & SCI_INT_PE) == SCI_INT_PE))
{
SCI_performSoftwareReset(base);
}
if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF)
{
HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFFINTCLR;
}
if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF)
{
HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFINTCLR;
}
}
//*****************************************************************************
//
// SCI_setBaud
//
//*****************************************************************************
void SCI_setBaud(uint32_t base, uint32_t lspclkHz, uint32_t baud)
{
uint32_t divider;
//
// Compute the baud rate divider {ROUND TO NEAREST INTEGER}
//
divider = ((float)((float)lspclkHz / ((float)baud * 8.0F)) - 1.0F) + 0.5F;
//
// Set the baud rate.
//
HWREGH(base + SCI_O_HBAUD) = (divider & 0xFF00U) >> 8U;
HWREGH(base + SCI_O_LBAUD) = divider & 0x00FFU;
}
//*****************************************************************************
//
// SCI_setWakeFlag
//
//*****************************************************************************
void SCI_setWakeFlag(uint32_t base)
{
//
// Check the arguments.
//
ASSERT(SCI_isBaseValid(base));
//
// Set the TX wake flag bit to indicate
// that the next frame is an address frame.
//
HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_TXWAKE;
}
28379d_P_SFRA/device/driverlib/sci.h
+1646
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28379d_P_SFRA/device/driverlib/sdfm.c
+188
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@@ -0,0 +1,188 @@
//###########################################################################
//
// FILE: sdfm.c
//
// TITLE: C28x SDFM Driver
//
//###########################################################################
//
// C2000Ware v6.00.01.00
//
// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
//
// Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the
// distribution.
//
// Neither the name of Texas Instruments Incorporated nor the names of
// its contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// $
//###########################################################################
#include "sdfm.h"
//*****************************************************************************
//
// Defines for filter configurations. Not intended for use by application code.
//
//*****************************************************************************
//
// Get filter oversampling ratio
//
#define SDFM_GET_OSR(C) ((C) >> 8U)
//
// Maximum acceptable comparator filter oversampling ratio
//
#define SDFM_MAX_COMP_FILTER_OSR 31U
//
// Maximum acceptable data filter oversampling ratio
//
#define SDFM_MAX_DATA_FILTER_OSR 255U
//
// Get the filter type
//
#define SDFM_GET_FILTER_TYPE(C) ((C) & 0x30U)
//
// Get the filter number
//
#define SDFM_GET_FILTER_NUMBER(C) ((C) & 0x3U)
//
// Get data shift value
//
#define SDFM_GET_SHIFT_VALUE(C) (((C) >> 2U) & 0x1FU)
//*****************************************************************************
//
// SDFM_configComparator
//
//*****************************************************************************
void SDFM_configComparator(uint32_t base, uint16_t config1, uint32_t config2)
{
SDFM_FilterNumber filter;
uint16_t ratio;
SDFM_FilterType filterType;
filter = (SDFM_FilterNumber)(SDFM_GET_FILTER_NUMBER(config1));
ratio = SDFM_GET_OSR(config1);
filterType = (SDFM_FilterType)SDFM_GET_FILTER_TYPE(config1);
//
// Limit the oversampling ratio
//
if(ratio > SDFM_MAX_COMP_FILTER_OSR)
{
ratio = SDFM_MAX_COMP_FILTER_OSR;
}
//
// Set the comparator filter type
//
SDFM_setComparatorFilterType(base, filter, filterType);
//
// Set the comparator filter over sampling ratio
//
SDFM_setCompFilterOverSamplingRatio(base, filter, ratio);
//
// Set the comparator high threshold value
//
SDFM_setCompFilterHighThreshold(base, filter,
SDFM_GET_HIGH_THRESHOLD(config2));
//
// Set the comparator low threshold value
//
SDFM_setCompFilterLowThreshold(base, filter,
SDFM_GET_LOW_THRESHOLD(config2));
}
//*****************************************************************************
//
// SDFM_configDataFilter
//
//*****************************************************************************
void SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2)
{
SDFM_FilterNumber filter;
uint16_t ratio;
SDFM_FilterType filterType;
filter = (SDFM_FilterNumber)(SDFM_GET_FILTER_NUMBER(config1));
ratio = SDFM_GET_OSR(config1);
filterType = (SDFM_FilterType)SDFM_GET_FILTER_TYPE(config1);
//
// Limit the oversampling ratio
//
if(ratio > SDFM_MAX_DATA_FILTER_OSR)
{
ratio = SDFM_MAX_DATA_FILTER_OSR;
}
//
// Set the comparator filter type
//
SDFM_setFilterType(base, filter, filterType);
//
// Set the comparator filter over sampling ratio
//
SDFM_setFilterOverSamplingRatio(base, filter, ratio);
//
// If filter switch on
//
if((config2 & SDFM_FILTER_ENABLE) == SDFM_FILTER_ENABLE)
{
SDFM_enableFilter(base, filter);
}
else
{
SDFM_disableFilter(base, filter);
}
//
// Set output data format
//
SDFM_setOutputDataFormat(base, filter,
(SDFM_OutputDataFormat)(config2 & 0x1U));
//
// Set the shift value if data is in 16-bit 2's complement format
//
if((config2 & 0x1U) == (uint16_t)(SDFM_DATA_FORMAT_16_BIT))
{
SDFM_setDataShiftValue(base, filter, SDFM_GET_SHIFT_VALUE(config2));
}
}

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