209 lines
6.3 KiB
C
209 lines
6.3 KiB
C
//#############################################################################
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//
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// FILE: clockTree.h
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//
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// TITLE: Setups device clocking for examples.
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//
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//#############################################################################
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// $Copyright:
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// Copyright (C) 2026 Texas Instruments Incorporated - http://www.ti.com
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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#ifndef CLOCKTREE_H
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#define CLOCKTREE_H
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//*****************************************************************************
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//
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// Summary of SYSPLL related clock configuration
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//
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//*****************************************************************************
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//
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// Input Clock to SYSPLL (OSCCLK) = 10 MHz (INTOSC1 provides OSCCLK)
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//
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//##### SYSPLL ENABLED #####
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//
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// PLLRAWCLK = 400 MHz (Output of SYSPLL if enabled)
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// PLLSYSCLK = 200 MHz
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// CPU1CLK = 200 MHz
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// CPU2CLK = 200 MHz
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// CPU1_SYSCLK = 200 MHz
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// CPU2_SYSCLK = 200 MHz
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// LSPCLK = 50 MHz
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// EPWMCLK = 100 MHz
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//*****************************************************************************
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//
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// Macro definitions used in device.c (SYSPLL / LSPCLK)
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//
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//*****************************************************************************
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//
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// Input Clock to SYSPLL (OSCCLK) = INTOSC1 = 10 MHz
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//
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#define DEVICE_OSCSRC_FREQ 10000000U
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//
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// Define to pass to SysCtl_setClock(). Will configure the clock as follows:
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// SYSPLL ENABLED
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// SYSCLK = 200 MHz = 10 MHz (OSCCLK) * (40 (IMULT) + 0 (FMULT)) / 2 (SYSCLKDIVSEL)
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#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * (40 + 0)) / 2)
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//
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#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_OSC1 | SYSCTL_IMULT(40) | \
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SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2)| \
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SYSCTL_PLL_ENABLE)
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//
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// Define to pass to SysCtl_setLowSpeedClock().
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// Low Speed Clock (LSPCLK) = 200 MHz / 4 = 50 MHz
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//
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#define DEVICE_LSPCLK_CFG SYSCTL_LSPCLK_PRESCALE_4
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#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4)
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//*****************************************************************************
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//
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// Summary of AUXPLL related clock configuration
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//
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//*****************************************************************************
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//
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// Input Clock to AUXOSCCLK = 10 MHz (XTAL provides AUXOSCCLK)
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//
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//##### AUXPLL DISABLED #####
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//
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// AUXPLLRAWCLK = 200 MHz (Output of AUXPLL if enabled)
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// AUXPLLCLK = 5 MHz
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//
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//*****************************************************************************
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//
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// Macro definitions used in device.c (AUXPLL)
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//
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//*****************************************************************************
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//
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// Input Clock to AUXPLL (AUXOSCCLK) = XTAL = 10 MHz
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//
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#define DEVICE_AUXOSCSRC_FREQ 10000000U
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//
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// Define to pass to SysCtl_setAuxClock(). Will configure the clock as follows:
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// AUXPLL DISABLED
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// AUXPLLCLK = 5 MHz = 10 MHz (XTAL) / 2 (AUXCLKDIVSEL)
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#define DEVICE_AUXCLK_FREQ (DEVICE_AUXOSCSRC_FREQ / 2)
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//
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#define DEVICE_SETAUXCLOCK_CFG (SYSCTL_AUXPLL_OSCSRC_XTAL | SYSCTL_AUXPLL_IMULT(20) | \
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SYSCTL_AUXPLL_FMULT_NONE | SYSCTL_AUXPLL_DIV_2 | \
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SYSCTL_AUXPLL_DISABLE)
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//*****************************************************************************
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//
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// CPU1CLK / CPU2CLK Domain (200 MHz)
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//
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//*****************************************************************************
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// VCU
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// TMU
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// FPU
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// Flash
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// BOOTROM
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// Mx/DxRAM
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//
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//*****************************************************************************
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//
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// CPU1 SYSCLK Domain (200 MHz)
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//
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//*****************************************************************************
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// EPIE
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// LSxRAMs
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// CLAMessageRAM
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// DCSM
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//
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/////////////////////
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// Gated CPU1 SYSCLK
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/////////////////////
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// CPU1_CLA1
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// CPU1_DMA
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// CPU1_Timer
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// EMIF2
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// uPP
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//
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//*****************************************************************************
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//
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// CPU2 SYSCLK Domain (200 MHz)
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//
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//*****************************************************************************
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// EPIE
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// LSxRAMs
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// CLAMessageRAM
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// DCSM
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//
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/////////////////////
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// Gated CPU2 SYSCLK
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/////////////////////
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// CPU2_CLA1
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// CPU2_DMA
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// CPU2_Timer
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//
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//*****************************************************************************
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//
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// Gated Peripheral EPWM Domain (100 MHz)
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//
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//*****************************************************************************
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// EPWM
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// HRPWM
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//
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//*****************************************************************************
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//
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// Gated Peripheral SYSCLK Domain (200 MHz)
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//
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//*****************************************************************************
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// ADC
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// CMPSS
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// DAC
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// EPWM
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// ECAP
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// EQEP
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// I2C
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// SDFM
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// EMIF
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//
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//*****************************************************************************
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//
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// Gated LSPCLK Domain (50 MHz)
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//
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//*****************************************************************************
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// SCI
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// SPI
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// McBSP
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#endif // CLOCKTREE_H
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